No description available.

No description available.

Insulated Gate Bipolar Transistors (IGBTs) are popular power electronic switching devices with several advantages. However, they have been known to fail in the field when subjected to significant variations in power dissipation – known as power cycling. In the work presented here, a novel alternating-current (AC) power cycling test method for IGBTs together with their free-wheeling diodes is proposed and verified. A review of previous work revealed that the parameter that most affects IGBT lifetime under power cycling conditions is the variation in its junction-case temperature difference. Through simulation, the behaviour of a conventional single phase inverter (H-bridge) using simple pulse width modulation (PWM) control was quantified, and the effect of switching frequency and load power factor was studied. Results of the simulations and literature review were used to develop design criteria for a new AC test circuit. The new AC test circuit (a modified version of the conventional H-bridge) was then designed and its performance compared to the criteria and to the simulation results of the conventional circuit. The circuit was then built and its performance was validated. The circuit complied with the performance criteria, in particular the desired variation in 7jc, to an adequate degree of accuracy. The proposed test circuit is novel for several reasons. The stresses on devices used in a conventional H-bridge using a high power factor inductive load are reproduced using a low power factor inductive load, considerably reducing the energy cost of running such a test. IGBT switching losses are not actively reduced, as is normal practice, but instead are actively increased to generate the required losses. Free-wheeling diodes are also tested, but do not have significant switching losses, as the nature of the test circuit dictates that these be transferred to the IGBTs. The main drawback of the proposed test circuit is that a larger number of devices are needed; however, this tradeoff is necessary to obtain the energy cost savings provided by this circuit.

This thesis researchs the design of quadrature modulator consists of 120MHz quadrature modulator that is fabricated using hybrid elements and print circuit board (PCB) technology for digital signal generator and quadrature modulator monolithic-microwave integrated-circuit (MMIC) that is fabricated using GaAs heterojunction bipolar transistor (HBT) technology for Personal Communication Service (PCS) applications. The 120MHz quadrature modulator incorporates power divider/combiner, phase shifter and doubly balanced mixer; the design architecture, principle and measurement results of division are presented in this thesis. A quadrature modulator is implemented by combining every division and measures specifications accurately, comparing with that of Agilent ESG-D series digital signal generator with the same carrier frequency and digital modulation. The quadrature modulator MMIC for PCS applications incorporates phase shifter, Gilbert cell mixer, differential to single-ended converter and RF amplifier at output; the design architecture, principle and simulation results of division are presented in this thesis. A quadrature modulator is integrated by combining every division and simulates parameters strictly.For troublesome specification measurement of quadrature modulator, this thesis also presents measurement method and instrument setup detailedly.

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographic references (p.64-66).

S’inscrivant dans le cadre de la gestion de l’énergie dans l’habitat du programme SESAME du pôle de compétitivité S2E2, l’objectif de cette thèse est d’étudier et de proposer une structure d’interrupteur commandable à l’ouverture et à la fermeture, bidirectionnel en tension et en courant et à faible perte énergétique, destiné à connecter tout type de charges sur le réseau alternatif 230V/50Hz. Il n’existe pas à l’heure actuelle de composants interrupteurs monolithiques de ce type. La première partie du mémoire présente les interrupteurs électroniques existants. La deuxième partie, traite des interrupteurs électroniques à base de transistors MOS et des limites de cette technologie unipolaire en termes de compromis de minimisation de surface de puces et de minimisation de la dissipation de puissance. Nous montrons ensuite que l’on peut repousser ces limites en adoptant des solutions à base de transistors bipolaires de puissances et notamment avec des bases fines autoprotégées (Transistors GAT). Le quatrième chapitre présente les résultats d’une étude des caractéristiques à l’état passant et à l’état bloqué de transistors GAT et valide leur aptitude à fonctionner sur le réseau alternatif. Nous montrons plusieurs voies possibles d’amélioration des caractéristiques de ces transistors avant d’étudier leur comportement dans une fonction interrupteur. Nous terminons ce travail en démontrant l’intérêt de la commande des transistors GAT en mode de conduction inverse, intérêt qui nous conduit ensuite à proposer une structure d’interrupteur totalement novatrice, avec la réduction par deux du nombre de composants et donc une réduction accrue de la puissance dissipée dans l’interrupteur. / As part of the energy management for household appliances of the S2E2 competitive pole SESAME program, the objective of this thesis is to propose a bidirectional switch in current and voltage with full turn-off control and low energy loss, ensuring the control of all loads types connected to the mains. The first part of this thesis presents the advantages and disadvantages of discrete or monolithic switches. In the second part, we were interested in electronic switches composed of MOS transistors. Different associations strategies and controls will be tested to reduce the power dissipation of the switch on the one hand, and facilitate control of the device on the other hand. Then we turned to solutions based on power bipolar transistors. The last one, called GAT distinguished itself by its high current gain and its low voltage drop in the on state. By implementing around the active base heavily doped caissons which create a shielding effect, one can increase the structure performances. After the design of this component in our laboratory, the characteristics of the on state and the off state were improved to validate its functionality in AC mains. The study will then focus on different technologies to confirm its performances. Using low metallization resistance and assembly strategy intelligently defined, it has been demonstrated that the performance of this component can be increased. Finally, we proposed a new switch structure using only two transistors GAT. We show that the interesting GAT reverse mode characteristics permit to deflect the load current flowing in the diodes and delete them. So we reduced the important source of power dissipation in the switch.

Kyoto University (京都大学) / 0048 / 新制・課程博士 / 博士(工学) / 甲第16862号 / 工博第3583号 / 新制||工||1541(附属図書館) / 29537 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 木本 恒暢, 教授 藤田 静雄, 准教授 浅野 卓 / 学位規則第4条第1項該当

No description available.

Le travail réalisé au cours de cette thèse porte sur l’optimisation du transistor bipolaire à hétérojonction Si/SiGe:C pour les applications d’amplification de puissance pour les communications sans fils. Nous présentons tout d’abord la structure d’étude. Il s’agit du transistor bipolaire à hétérojonction Si/SiGe:C intégré en technologie BiCMOS 0.25µm sur plaques 200mm. La cellule dédiée à l’amplification de puissance est présentée. Une attention particulière est apportée aux phénomènes thermiques inhérents à ce type de cellules ainsi qu’aux solutions mises en œuvre pour les atténuer. Les diverses optimisations réalisées sur l’architecture du TBH sont détaillées. Ces optimisations touchent à la fois à la modification du procédé technologique et au dessin du transistor. Notre étude porte sur l’amélioration des performances petit et grand signal via l’optimisation des paramètres technologiques définissant la structure épitaxiale intrinsèque de base et de collecteur ainsi que des règles de dessin du transistor. Enfin, deux types d’architectures de TBH développées sont présentées. L’une de type simple polysilicium quasi auto-alignée qui s’intègre dans une technologie dédiée à l’amplification de puissance, l’autre présentant une structure double polysilicium également auto-alignée. / The present work deals with Si/SiGe:C heterojonction bipolar transistor optimization for power amplifier applications dedicated to wireless communications. We first present the investigated structure, a Si/SiGe:C heterojonction bipolar transistor integrated in a 0.25µm BiCMOS technology on 200 mm wafers. We discuss the cell dedicated to power amplification. We have paid attention to thermal phenomenon linked to this kind of cell and to possible dedicated solutions. Various optimizations realized on HBT architecture are detailed. These optimizations concern technological process modifications and transistor design. The main objective of this work is to improve both large and small signal characteristics. This is obtained by transistor design rule variations, collector and base intrinsic parameters optimization. Finally, two kind of developed HBT architectures are presented. One, simple polysilicium quasi self aligned, integrated in a technology dedicated to power amplification, the other one fully self aligned with double polysilicium structure.

The objective of the proposed work is to study the behavior of SiGe HBTs at cryogenic temperatures and its relation to device scaling and optimization. Not only is cryogenic operation of these devices required by space missions, but characterizing their cryogenic behavior also helps to investigate the performance limits of SiGe HBTs and provides essential information for further device scaling. Technology computer aided design (TCAD) and sophisticated on-wafer DC and RF measurements are essential in this research. Drift-diffusion (DD) theory is used to investigate a novel negative differential resistance (NDR) effect and a collector current kink effect in first-generation SiGe HBTs at deep cryogenic temperatures. A theory of positive feedback due to the enhanced heterojunction barrier effect at deep cryogenic temperatures is proposed to explain such effects. Intricate design of the germanium and base doping profiles can greatly suppress both carrier freezeout and the heterojunction barrier effect, leading to a significant improvement in the DC and RF performance for NASA lunar missions. Furthermore, cooling is used as a tuning knob to better understand the performance limits of SiGe HBTs. The consequences of cooling SiGe HBTs are in many ways similar to those of combined vertical and lateral device scaling. A case study of low-temperature DC and RF performance of prototype fourth-generation SiGe HBTs is presented. This study summarizes the performance of all three prototypes of these fourth-generation SiGe HBTs within the temperature range of 4.5 to 300 K. Temperature dependence of a fourth-generation SiGe CML gate delay is also examined, leading to record performance of Si-based IC. This work helps to analyze the key optimization issues associated with device scaling to terahertz speeds at room temperature. As an alternative method, an fT -doubler technique is presented as an attempt to reach half-terahertz speeds. In addition, a roadmap for terahertz device scaling is given, and the potential relevant physics associated with future device scaling are examined. Subsequently, a novel superjunction collector design is proposed for higher breakdown voltages. Hydrodynamic models are used for the TCAD studies that complete this part of the work. Finally, Monte Carlo simulations are explored in the analysis of aggressively-scaled SiGe HBTs.