The majority of signals, that need to be processed, are analog, which are continuous and can take an infinite number of values at any time instant. Precision of the analog signals are limited due to influence of distortion which leads to the use of digital signals for better performance and cost. Analog to Digital Converter (ADC), converts the continuous time signal to the discrete time signal. Most A/D converters are classified into two categories according to their sampling technique: nyquist rate ADC and oversampled ADC. The nyquist rate ADC operates at the sample frequency equal to twice the base-band frequency, whereas the oversampled ADC operates at the sample frequency greater than the nyquist frequency. The sigma delta ADC using the oversampling technique provides high resolution, low to medium speed, relaxed anti-aliasing requirements and various options for reconfiguration. On the contrary, resolution of the sigma delta ADC can be traded for high speed operation. Data sampling techniques plays a vital role in the sigma delta modulator and can be classified into discrete time sampling and continuous time sampling. Furthermore, the discrete time sampling technique can be implemented using the switched-capacitor (SC) integrator and the switched-current (SI) integrator circuits. The SC integrator technique provides high accuracy but occupies a larger area. Unlike the SC integrator, the SI integrator offers low input impedance and parasitic capacitance. This makes the SI integrator suitable for low supply voltage and high frequency applications. From a detailed literature study on the multi-bit sigma delta modulator, it is analyzed that, theneeds a highly linear digital to analogue converter (DAC) in its feedback path. The sigma delta modulators are very sensitive to linearity of the DAC which can degrade the performance without any attenuation. For this purpose T.C. Leslie and B. Singh proposed a Hybrid architecture using the multi-bit quantizer with a single bit DAC. The most significant bit is fed back to the DAC while the least significant bits are omitted. This omission requires a complex digital calibration to complete the analog to digital conversion process which is a small price to pay compared to the linearity requirements of the DAC. This project work describes the design of High-Speed Hybrid Current modeModulator with a single bit feedback DAC at the speed of 2.56GHz in a state-of-the-art 65 nm CMOS process. It comprises of both the analog and digital processing blocks, using T.C. Leslie and B. Singh architecture with the switched current integrator data sampling technique for low voltage, high speed operation. The whole system is verified mathematically in matlab and implemented using signal flow graphs and verilog a code. The analog blocks like switched current integrator, flash ADC and DAC are implemented in transistor level using a 65 nm CMOS technology and the functionality of each block is verified. Dynamic performance parameters such as SNR, SNDR and SFDR for different levels of abstraction matches the mathematical model performance characteristics.

Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mixed signal processing systems. In this thesis work, a 9-bitpipelined ADC with switch-current (SI) technique is designed and implemented in65 nm CMOS technology. The main focus of the thesis work is to implement thepipelined ADC in SI technique and to optimize the pipelined ADC for low power.The ADC has a stage resolution of 3 bits. The proposed architectures combine adifferential sample-and-hold amplifier, current comparator, binary-to-thermometerdecoder, a differential current-steering digital-to-analog converter, delay logic anddigital error correction block. The circuits are implemented at transistor level in 65nm CMOS technology. The static and dynamic performance metrics of pipelinedADC are evaluated. The simulations are carried out by Cadence Virtuoso SpectreCircuit Simulator 5.10. Matlab is used to determine the performance metrics ofADC.

Darbas skirtas precizinių kampo komparatorių išoriniams ir vidiniams temperatūriniams trikdžiams tirti. Jame sudarytas kalibravimo neapibrėžties modelis, identifikuoti ir išnagrinėti pagrindiniai kampo kalibravimo neapibrėžties sandai, apžvelgti precizinių matavimo įrenginių temperatūrinių paklaidų tyrimo metodai ir priemonės, pasirinkta temeratūrinių gradientų tyrimo metodika ir įranga. Remiantis pateiktomis precizinių kampo komparatorių schemomis, identifikuoti pagrindiniai temperatūrinių paklaidų šaltiniai. Atlikti temperatūrinių gradientų komparatoriaus ir atskirų jo šilumos šaltinių aplinkoje eksperimentiniai tyrimai. Tyrimų rezultatai statistiškai apdoroti, apibendrinti ir padarytos reikiamos išvados. Pateikti temperatūrinių komparatoriaus bazinių elementų temperatūrinių laukų ir deformacijų skaičiavimo rezultatai, atlikti remiantis eksperimentiniais tyrimais. Teikiamos rekomendacijos temperatūriniams kalibravimo paklaidoms mažinti. Darbo apimtis – 74 p. teksto be priedų, 44 iliustracijos, 21 bibliografinis šaltinis. Atskirai pridedami darbo priedai. / The research investigates external and internal temperature disturbance in precision angle comparators.The research consists of the model of calibration uncertainty, identification and analysis of the main components of calibration uncertainty, the review of the methods and implements used for the analysis of the measurement errors which occur in precision measurement mechanisms; furthermore, there is indicated choice of methodology and equipment necessary for the analysis of temperature gradient investigation. According to the given schemes of precision angle comparators, there are identified the basic source of temperature errors. The experimental research of temperature gradient comparator and its separate source of warmth has been carried out. The results were produced and summarized as well as some respective conclusions were reached. According to the experimental research, there are produced some computation results concerning the temperature fields of base elements of temperature comparators. Finally, some recommendations are formulated concerning the reduction of the errors of temperature calibration. Thesis consist of: 74 p. text without appendixes, 44 pictures, 21 bibliographical entries. Appendixes included.

[pt] Esta Dissertação de Mestrado apresenta uma metodologia para analisar transformadores para instrumentos (TI) em geral, e vários tipos de transformadores de corrente (TC-s) para medição. O funcionamento e as características dos transformadores de potencial (TP-s) e dos TC-s estão sendo analisados, usando-se as ferramentas tradicionais (circuito equivalente e representação fasorial). O tratamento generalizado facilita a comparação entre TP-s e TC-s e a análise qualitativa dos parâmetros que influenciam os erros de relação e de ângulo de fase.Após verificação geral, quatro tipos de TC-s estão sendo estudados detalhadamente. Para analisar construções eletromagnéticas mais complexas, um método não tradicional está sendo aplicado. Usando-se as representações fasoriais,realiza-se o cálculo baseando-se nas equações elétricas e nas equações magnéticas. O erro complexo do TC é o resultado das soluções destas equações, e vem expresso em função dos parâmetros de construção. Os resultados facilitam comparar o desempenho de vários tipos de TC-s existentes e/ou a serem projetados. Um programa de simulação, utilizando a linguagem C no ambiente LabWindows/CVI - C for Virtual Instrumentation (National Instruments), foi desenvolvido com base nas equações para o cálculo do erro. O programa analisa o comportamento de 4 tipos de TC-s, existentes e/ou a serem projetados, quanto ao erro de relação e ao ângulo de fase. A partir do tipo de material, da dimensão do núcleo e do tipo de enrolamentos, em modo interativo, pode-se escolher várias combinações dos parâmetros em etapas repetidas. A eficiência do método aplicado foi verificada e comprovada. Os resultados são coerentes e quando usados no programa de simulação, resultam em um novo método para analisar, projetar ou escolher um TC para uma finalidade específica. / [en] This dissertation for a master degree presents a methodology to analyse Instrument Transformers in general terms and several types of Current Transformers (CT`s) for measurements, in details.At first, operation and characteristics of Potential Transformers (PT` s) and that of CT` s are analysed, using traditional tools (as equivalent circuits and fasorial representation). The generalised treatment facilitates the comparison between PT` s and CT` s as well as a qualitative analysis of the parameters influencing the ratio and phase errors. After giving a general view, four types of CT` s are studied in details. To analyse complex electromagnetic constructions, a non-traditional method is applied. By using fasorial representations, calculus is based on defining separate groups of electrical and magnetic equations to describe a device. The result of the solution of this set of equations is the complex error of the CT, which is being expressed exclusively in terms of parameters of the construction. The results facilitate the comparison of the performance of various types of CT` s, that exist or are to be designed. A simulation program, using language C, in the ambient of LabWindows/CVI - C for Virtual Instrumentation (National Instruments), was developed, in order to calculate the errors, based upon the equations obtained. The program is capable of specifying the parameters and analysing the characteristics of four types of CT` s, representing finally the ratio and phase errors, in terms of the variation of the current or that of the load. Characteristics of various magnet ic materials, dimensions ofstandardized toroidal cores and that of wires can be specified, stored and selected thereafter. The program facilitates experimenting with various combinations of parameters in an interactive mode and to approximate optimised constructions in iterative steps. Efficiency of the method was verified and proved. The results are coherent and when are used in the simulation program, represent a new method to analyse an existing CT or to design a new one, or to select the most adequate model for a specific purpose.

The diploma thesis deals with the description of selected optical systems in length metrology. The main benefit of this work is the design and implementation of a sensor with the VIONiCplus optical system and the application of this measuring system to length comparators. The work contains experimental verification of the use of an optical system with a resolution of 2.5 nm for sensors and length comparators with recommendations for practical use.

In master´s thesis I deal with analysing of decision-making in PPP projects and searching for an optimal solutions. On an example of hypothetical project there is shown a decision making process which consists from three main parts: cost evaluation, revenue evaluation and risk identification. The result of this analyse is based on a public sector comparator where you can demonostrate suitability or unsuitability of particular PPP offers coming from private sphere.

Dans un contexte de besoin grandissant en précision dans la mesure des faibles courants pour les instituts nationaux de métrologie, l’industrie, les fabricants d’instruments et la physique fondamentale, l’étude des dispositifs à un électron (SET) capables de générer un courant continu directement proportionnel à une fréquence et la charge élémentaire, couplés à un amplificateur de courant très performant, le comparateur cryogénique de courant (CCC), devient pertinente pour réaliser un étalon quantique de courant. Dans ce contexte, les travaux ont été poursuivis au LNE sur l’étude de nouveaux dispositifs SET et le développement de nouveaux CCC. Durant cette thèse, un montage expérimental a été mis en place afin d’évaluer les performances d’un nouveau CCC, constitué d’une conception originale et de 30 000 tours. Les résultats expérimentaux obtenus sont satisfaisant par rapport aux objectifs fixés, que ce soit en termes de résolution en courant, d’erreurs, de stabilité des mesures et de reproductibilité. Le CCC développé durant la thèse peut donc être utilisé pour quantifier de manière métrologique les dispositifs à un électron. De plus, une modélisation réalisée à partir d’un schéma électrique équivalent a été mis en place afin de simuler le comportement réel du CCC en prenant en compte les aspects magnétiques et électriques mis en jeu. Cette simulation a permis la quantification de l’erreur due aux fuites de courants au travers des capacités parasites entourant les enroulements. Les résultats de la simulation indiquent que cette erreur atteint 10 10 à la fréquence de travail, ce qui est inférieure de deux ordres de grandeurs à l’erreur maximale tolérable : 10-8. Les résultats expérimentaux et de modélisation fournissent de nouveaux éléments d’amélioration de la conception de CCCs de grand gain. Enfin, la modélisation développée, une fois insérée dans une routine d’optimisation, pourra aussi être un outil de conception des CCCs très utile. / In a context of growing need of precision in measuring low currents for national metrology institutes, industry, instrument manufacturers and fundamental physics, study of single-electron tunneling (SET) devices capable of generating a direct current directly proportional to the frequency and the elementary charge, coupled with a high performance current amplifier, the cryogenic current comparator (CCC), becomes relevant to realize a quantum current standard. In this framework, at LNE, study of new SET devices and the development of CCCs continues. In this thesis, an experimental setup was implemented to evaluate the performance of a new CCC, consisting of a new design and 30 000 turns. The experimental results fulfill our goals, whether in terms of current resolution, errors, measurement stability and reproducibility. The CCC developed during the thesis can thus be used to metrologically quantify SET devices. In addition, a model based on an equivalent circuit diagram has been developed to simulate the actual behavior of the CCC, taking into account the magnetic and electrical aspects involved. This simulation allows the quantification of the error due to currents leakage through parasitic capacitances surrounding the windings. Results of the simulation indicate that this error reaches 10 10, which is less, by two orders of magnitude, than the maximum tolerable error: 10 8. Results obtained experimentally and by simulation provide new improvement elements in the design of high ratio CCCs. The developed model, once inserted into an optimization routine, can also be a very useful design tool of CCCs.

L’imagerie constitue un axe majeur de l’exploration de l’univers et de la Terre depuis l’espace, que l’on se trouve dans le domaine du visible ou non. Ainsi dans le domaine spatial, les données sont le plus souvent récupérées par un capteur CCD (Charge-Coupled Device, ou Dispositif à Transfert de Charge (DTC)) qui fournit des tensions analogiques vers un convertisseur analogique-numérique (CAN), dont la sortie sera transmise à une chaîne de traitement, puis envoyée sur terre. Ainsi, les CAN sont des éléments clés dans l’imagerie par satellite. De leur précision et de leur vitesse va dépendre la qualité de la représentativité de la chaîne de signaux binaires. Il est donc crucial de réaliser une conversion de données de grande qualité (vitesse, précision) tout en s’assurant de la résistance du CAN à l’environnement radiatif. L’objectif de cette thèse est d’améliorer la robustesse à l’environnement spatial, tout en optimisant les performances, de plusieurs fonctions élémentaires d’un convertisseur analogique-numérique de type pipeline 14bits,5MS/s, réalisées en technologie XFAB 0,18µm. Les trois fonctions ciblées sont les interrupteurs (notamment la résolution des problèmes liés au phénomène d’injection de charges en environnement spatial), les comparateurs (durcissement) et l’amplificateur à capacités commutées (amélioration du gain par une technique prédictive sans pénaliser la puissance consommée). / Imaging is a major issue in the observation of the Universe and the Earth from space, whether in the visible domain or not. Thus, in the spatial field, data is often gathered by a CCD (charge-Coupled Device) sensor, that supplies analog voltages to an Analog-to-Digital Converter (ADC), which outputs will be delivered to a processing chain, and then sent to earth. Consequently, ADCs are key elements in satellite imaging. Their precision and speed will indeed define the quality and the representativeness of the binary signal. It is then crucial to perform a high quality (speed & precision) conversion of the data, while making sure that the ADC can cope with the harsh irradiative environment. The purpose of this thesis is to improve the robustness to the space environment (hardening), while optimizing the performances, of several elementary devices that compose a 14 bits, 5MS/s pipeline ADC, made with the XFAB 180nm technology. The three targeted functions are the switches (especially the problems linked to coping with the charge injection problems in a space environment), the comparators (hardening) and the switched-capacitor amplifier (gain boosting through a predictive architecture with no penalty on the power consumption).

No description available.

Rapid evolution of integrated circuit technologies has paved a way to develop smaller and energy efficient biomedical devices which has put stringent requirements on data acquisition systems. These implantable devices are compact and have a very small footprint. Once implanted these devices need to rely on non-rechargeable batteries to sustain a life span of up to 10 years. Analog-to-digital converters (ADCs) are key components in these power limited systems. Therefore, development of ADCs with medium resolution (8-10 bits) and sampling rate (1 MHz) have been of great importance. This thesis presents an 8-bit successive approximation register (SAR) ADC incorporating an asynchronous control logic to avoid external high frequency clock, a dynamic comparator to improve linearity and a differential charger-distribution DAC with a monotonic capacitor switching procedure to achieve better power efficiency. This ADC is developed on a 0.18um TSMC process using Cadence Integrated Circuit design tools. At a sampling rate of 1MS/s and a supply voltage of 1.8V, this 8-bit SAR ADC achieves an effective number of bits (ENOB) of 7.39 and consumes 227.3uW of power, resulting in an energy efficient figure of merit (FOM) of 0.338pJ/conversion-step. Measured results show that the proposed SAR ADC achieves a spurious-free dynamic range (SFDR) of 57.40dB and a signal-to-noise and distortion ratio (SNDR) of 46.27dB. Including pad-ring measured chip area is 0.335sq-mm with the ADC core taking up only 0.055sq-mm