Digital-to-Analog Converters (DAC) form the feedback element in sigma-delta modulators. Any non-linearity in the DAC directly degrades the linearity of the modulator at low and medium frequencies. Hence, there is a need for designing highly linear DACs when used in high performance sigma-delta modulators. In this work, the impact of current mismatch on the linearity performance (IM3 and SQNR) of a 4-bit current steering DAC is analyzed. A selective calibration technique is proposed that is aimed at reducing the area occupancy of conventional linearization circuits. A statistical element selection algorithm for linearizing DACs is proposed. Current sources within the required accuracy are selected from a large set of current sources available. As compared with existing calibration techniques, this technique achieves higher accuracy and is more robust to variations in process and temperature. In contrast to existing data weighted averaging techniques, this technique does not degrade SNR performance of the ADC. A 5th order, 500 MS/s, 20 MHz sigma-delta modulator macro-model was used to test the linearity of the DAC.

Due to its exceptional mechanical and electrical properties, graphene (one layer sheet of carbon atoms) has attracted a lot of attention since its discovery in 2004. The purpose of this research is to compare the Raman spectra of graphene with plasma treated graphene sheets which have been treated by changing the different parameters affecting the plasma treatment like gas flow, power and pressure and treatment time. The graphene we used for our high pressure studies are 4-5 layer CVD deposited graphene samples prepared by our collaborators in Dr. W. B. Choi’s group. First we report a Raman spectroscopy study of graphene on copper substrate at high pressures. Diamond anvil cell (DAC) was used to generate pressure. In situ Raman spectra were collected at pressures up to 10 GPa. The results indicate that the G band of graphene shifts with pressure significantly (about 5 cm-1/GPa) whereas the 2D band changes very little. The plasma treated samples were loaded into DAC. Raman spectrum was captured. Parts of the spectrum which were not related to the grapheme peak position were eliminated. The background was reduced. Peaks were found and fitted using FITYK software and the shift of each peak compared to its last position was observed when the pressure was increased. Next we studied plasma treated graphene samples treated with different partial pressure treatments under high pressure and compared them to each other using zirconia anvil cell with the same method.

This thesis deals with design and implementation of laboratory microcontroller system, based on ARM architecture. Purpose of this thesis is to teach programming. This system allows the user to work with the internal and external peripherals of the microcontroller, which are equipped with the system. This thesis includes creating a concept its peripheral solution and realization itself. A suitable development environment is determined for the system and the thesis includes sample solutions for the proposed tasks.

Uppsatsen behandlar lagförslaget om rapporteringsplikt för skatterådgivare enligt proposition 2019/20:74. I uppsatsen ställs lagförslaget mot ett rättssäkerhetsperspektiv för att utröna huruvida förslagna bestämmelser i propositionen är att anse som rättssäkra eller inte.

Broadband wireless communication systems demand power-efficient analog-to-digital converters (ADCs) in the GHz and medium resolution regime. While high-speed architectures such as the flash and pipelined ADCs are capable of GHz operations, their high-power consumption reduces their attractiveness for mobile applications. On the other hand, the successive-approximation-register (SAR) ADC has an excellent power efficiency, but its slow speed has traditionally limited it to MHz applications. This dissertation puts forth several novel techniques to significantly increase the speed and power efficiency of the SAR architecture and demonstrates them in a low-power 10-GHz SAR ADC suitable for broadband wireless communications. The proposed 8-bit, 10-GHz, 8× time-interleaved SAR ADC utilizes a constant-matching DAC with symmetrically grouped unit finger capacitors to maximize speed by reducing the total DAC capacitance to 32 fF and minimizing the bottom plate parasitic capacitance. The capacitance reduction also saves power as both the DAC size and the driving logic size are reduced. An optimized asynchronous comparator loop and smaller driver logic push the single channel speed of the SAR ADC to 1.25 GHz, thus minimizing the total number of timeinterleaved channels to 8 to reach 10 GHz. A dual-path bootstrapped switch improves the spurious-free dynamic range (SFDR) of the sampling by creating an auxiliary path to drive the non-linear N-well capacitance apart from the main signal path. Using these techniques, the ADC achieves a measured signal-to-noise-and-distortion ratio (SNDR) and SFDR of 36.9 dB and 59 dB, respectively with a Nyquist input while consuming 21 mW of power. The ADC demonstrates a record-breaking figure-of-merit of 37 fJ/conv.-step, which is more than 2× better than the next best published design, among reported ADCs of similar speeds and resolutions.

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In contemporary communication systems, Digital-to-Analog Converters (DAC), Signal Defined Radio (SDR) signal creation, and clock data recovery are essential components. DACs convert digital signals to analog signals, creating continuous waveforms. DACs provide versatility in the transmission of SDR by supporting a range of communication protocols. Clock data recovery enables precise signal recovery and synchronization at the receiver end. These elements work together to provide effective and high-quality communication systems across several sectors. With the development of quantum computing, these SDR systems also find extensive use in generating precisely timed signals for controlling components of a quantum computer and also for read-out operations from various specialized instruments. This thesis demonstrates an FPGA (Xilinx vcu118) with a DAC (Analog Devices AD9081) platform. It employs SDR for generating of periodic signals and also stream of bits which are then recovered using a simple Clock Data Recovery technique. The signal integrity of the generated signals and error-rate from the proposed Clock Data Recovery technique is also analyzed. / Master of Science / Communication systems in our networked world depend on key technologies to provide dependable connectivity. By converting digital data into continuous waveforms, Digital-to- Analog Converters (DACs) serve a crucial role in enabling the generation of various analog signals. This makes it possible for Software-Defined Radio (SDR) to produce a variety of modulated signals and enables smooth communication between various hardware and software systems. The Clock and Data Recovery (CDR) algorithms correct for clock fluctuations and phase offsets to provide precise signal recovery and synchronization. Together, these technologies improve communication networks' effectiveness and dependability, allowing seamless connectivity and enhancing our networked experiences. This thesis presents an SDR platform comprising Xilinx FPGA vcu118 and Analog Devices high-speed DAC/ADC AD9081. A CDR algorithm is also proposed to recover data from the signals generated by the DAC, and its effectiveness and error rate is also analyzed.

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