Approximate computing has been an emerging programming and system design paradigm that has been proposed as a way to overcome the power-wall problem that hinders the scaling of the next generation of both high-end and mobile computing systems. Towards this end, a lot of researchers have been studying the effects of approximation to applications and those hardware modifications that allow increased power benefits for reduced reliability. In this work, we focus on runtime system modifications and task-based programming models that enable software-controlled, user-driven approximate computing. We employ a systematic methodology that allows us to evaluate the potential energy and performance benefits of approximate computing using as building blocks unreliable hardware components. We present a set of extensions to OpenMP 4.0 that enable the programmer to define computations suitable for approximation. We introduce task-significance, a novel concept that describes the contribution of a task to the quality of the result. We use significance as a channel of communication from domain specific knowledge about applications towards the runtime-system, where we can optimise approximate execution depending on user constraints. Finally, we show extensions to the Linux kernel that enable it to operate seamlessly on top of unreliable memory and provide a user-space interface for memory allocation from the unreliable portion of the physical memory. Having this framework in place allowed us to identify what we call the refresh-by-access property of applications that use dynamic random-access memory (DRAM). We use this property to implement techniques for task-based applications that minimise the probability of errors when using unreliable memory enabling increased quality and power efficiency when using unreliable DRAM.

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High aspect ratio silicon etching used for DRAM manufacturing still remains as one of the biggest challenges in semiconductor fabrication, requiring well understood and characterized process fundamentals. In this study, physical and chemical interactions during etching silicon in capacitively coupled plasma discharges were investigated in detail for different HBr/NF3 mixed chemistries for single frequency as well as dual frequency operation and medium discharge pressures inside an industrial MERIE CCP reactor typically used for DRAM fabrication. Utilization of the dual frequency concept for separate control of ion energy and ion flux, as well as the impact on discharge properties and finally on etching at relevant substrate surfaces were studied systematically. The complex nature of multi frequency rf sheaths was both analyzed experimentally by applying mass resolved ion energy analysis, and from simulation of ion energy distributions by using a Hybrid Plasma Sheath Model. Discharge composition and etch processes were investigated by employing standard mass spectrometry, Appearance Potential Mass Spectrometry, Quantum Cascade Laser Absorption Spectroscopy, rf probe measurements, gravimetry and ellipsometry. An etch model is developed to explain limitations of silicon etching in HBr/NF3 discharges to achieve highly aniostropic etching. / Siliziumätzen mit hohen Aspektverhältnissen zur Herstellung von DRAM-Speicherstrukturen stellt nach wie vor eine der größten Herausforderungen in der Halbleiterherstellung dar und erfordert ein grundlegendes Prozessverständnis. Diese Studie beinhaltet eine umfassende und detaillierte Untersuchung physikalischer und chemischer Wechselwirkungen von Siliziumätzprozessen in kapazitiv gekoppelten HBr/NF3-Gasentladungen in einem kommerziellen, typischerweise für die DRAM-Fertigung eingesetzten MERIE CCP Reaktor mit Ein- und Zweifrequenzanregung bei mittleren Entladungsdrücken. Die Anwendung eines Zweifrequenzkonzeptes zur separaten Kontrolle von Ionenenergie und Ionenstromdichte, als auch deren Einfluss auf die Entladungseigenschaften und letztendlich auf das Ätzverhalten auf relevanten Substratoberflächen wurden systematisch untersucht. Die komplexe Natur von mehrfrequenzangeregten HF-Randschichten wurde sowohl experimentell über eine Anwendung von massenaufgelöster Ionenenergieanalyse als auch rechnerisch über Simulationen von Ionenenergieverteilungsfunktionen mit Hilfe eines hybriden Plasmarandschichtmodells analysiert. Gaszusammensetzungen verschiedener Entladungen und Ätzprozesse wurden mit Hilfe von Standard-Massenspektrometrie, Schwellwert-Massenspektrometrie, Quantenkaskaden-Laserabsorptionsspektroskopie, HF-Sondenmessungen, Gravimetrie und Ellipsometrie charakterisiert. Eine neuartige Modellvorstellung zum Siliziumätzen in HBr/NF3-Entladungsgemischen liefert eine plausible Erklärung für die Limitierung der Ätzrate zum Erreichen eines hoch anisotropen Ätzverhaltens.

Memory system design is increasingly influencing modern multi-core architectures from both performance and power perspectives. Both main memory latency and bandwidth have im-proved at a rate that is slower than the increase in processor core count and speed. Off-chip memory, primarily built from DRAM, has received significant attention in terms of architecture and design for higher performance. These performance improvement techniques include sophisticated memory access scheduling, use of multiple memory controllers, mitigating the impact of DRAM refresh cycles, and so on. At the same time, new non-volatile memory technologies have become increasingly viable in terms of performance and energy. These alternative technologies offer different performance characteristics as compared to traditional DRAM. With the advent of 3D stacking, on-chip memory in the form of 3D stacked DRAM has opened up avenues for addressing the bandwidth and latency limitations of off-chip memory. Stacked DRAM is expected to offer abundant capacity — 100s of MBs to a few GBs — at higher bandwidth and lower latency. Researchers have proposed to use this capacity as an extension to main memory, or as a large last-level DRAM cache. When leveraged as a cache, stacked DRAM provides opportunities and challenges for improving cache hit rate, access latency, and off-chip bandwidth. Thus, designing off-chip and on-chip memory systems for multi-core architectures is complex, compounded by the myriad architectural, design and technological choices, combined with the characteristics of application workloads. Applications have inherent spatial local-ity and access parallelism that influence the memory system response in terms of latency and bandwidth. In this thesis, we construct an analytical model of the off-chip main memory system to comprehend this diverse space and to study the impact of memory system parameters and work-load characteristics from latency and bandwidth perspectives. Our model, called ANATOMY, uses a queuing network formulation of the memory system parameterized with workload characteristics to obtain a closed form solution for the average miss penalty experienced by the last-level cache. We validate the model across a wide variety of memory configurations on four-core, eight-core and sixteen-core architectures. ANATOMY is able to predict memory latency with average errors of 8.1%, 4.1%and 9.7%over quad-core, eight-core and sixteen-core configurations respectively. Further, ANATOMY identifie better performing design points accurately thereby allowing architects and designers to explore the more promising design points in greater detail. We demonstrate the extensibility and applicability of our model by exploring a variety of memory design choices such as the impact of clock speed, benefit of multiple memory controllers, the role of banks and channel width, and so on. We also demonstrate ANATOMY’s ability to capture architectural elements such as memory scheduling mechanisms and impact of DRAM refresh cycles. In all of these studies, ANATOMY provides insight into sources of memory performance bottlenecks and is able to quantitatively predict the benefit of redressing them. An insight from the model suggests that the provisioning of multiple small row-buffers in each DRAM bank achieves better performance than the traditional one (large) row-buffer per bank design. Multiple row-buffers also enable newer performance improvement opportunities such as intra-bank parallelism between data transfers and row activations, and smart row-buffer allocation schemes based on workload demand. Our evaluation (both using the analytical model and detailed cycle-accurate simulation) shows that the proposed DRAM re-organization achieves significant speed-up as well as energy reduction. Next we examine the role of on-chip stacked DRAM caches at improving performance by reducing the load on off-chip main memory. We extend ANATOMY to cover DRAM caches. ANATOMY-Cache takes into account all the key parameters/design issues governing DRAM cache organization namely, where the cache metadata is stored and accessed, the role of cache block size and set associativity and the impact of block size on row-buffer hit rate and off-chip bandwidth. Yet the model is kept simple and provides a closed form solution for the aver-age miss penalty experienced by the last-level SRAM cache. ANATOMY-Cache is validated against detailed architecture simulations and shown to have latency estimation errors of 10.7% and 8.8%on average in quad-core and eight-core configurations respectively. An interesting in-sight from the model suggests that under high load, it is better to bypass the congested DRAM cache and leverage the available idle main memory bandwidth. We use this insight to propose a refresh reduction mechanism that virtually eliminates refresh overhead in DRAM caches. We implement a low-overhead hardware mechanism to record accesses to recent DRAM cache pages and refresh only these pages. Older cache pages are considered invalid and serviced from the (idle) main memory. This technique achieves average refresh reduction of 90% with resulting memory energy savings of 9%and overall performance improvement of 3.7%. Finally, we propose a new DRAM cache organization that achieves higher cache hit rate, lower latency and lower off-chip bandwidth demand. Called the Bi-Modal Cache, our cache organization brings three independent improvements together: (i) it enables parallel tag and data accesses, (ii) it eliminates a large fraction of tag accesses entirely by use of a novel way locator and (iii) it improves cache space utilization by organizing the cache sets as a combination of some big blocks (512B) and some small blocks (64B). The Bi-Modal Cache reduces hit latency by use of the way locator and parallel tag and data accesses. It improves hit rate by leveraging the cache capacity efficiently – blocks with low spatial reuse are allocated in the cache at 64B granularity thereby reducing both wasted off-chip bandwidth as well as cache internal fragmentation. Increased cache hit rate leads to reduction in off-chip bandwidth demand. Through detailed simulations, we demonstrate that the Bi-Modal Cache achieves overall performance improvement of 10.8%, 13.8% and 14.0% in quad-core, eight-core and sixteen-core workloads respectively over an aggressive baseline.

High aspect ratio silicon etching used for DRAM manufacturing still remains as one of the biggest challenges in semiconductor fabrication, requiring well understood and characterized process fundamentals. In this study, physical and chemical interactions during etching silicon in capacitively coupled plasma discharges were investigated in detail for different HBr/NF3 mixed chemistries for single frequency as well as dual frequency operation and medium discharge pressures inside an industrial MERIE CCP reactor typically used for DRAM fabrication. Utilization of the dual frequency concept for separate control of ion energy and ion flux, as well as the impact on discharge properties and finally on etching at relevant substrate surfaces were studied systematically. The complex nature of multi frequency rf sheaths was both analyzed experimentally by applying mass resolved ion energy analysis, and from simulation of ion energy distributions by using a Hybrid Plasma Sheath Model. Discharge composition and etch processes were investigated by employing standard mass spectrometry, Appearance Potential Mass Spectrometry, Quantum Cascade Laser Absorption Spectroscopy, rf probe measurements, gravimetry and ellipsometry. An etch model is developed to explain limitations of silicon etching in HBr/NF3 discharges to achieve highly aniostropic etching. / Siliziumätzen mit hohen Aspektverhältnissen zur Herstellung von DRAM-Speicherstrukturen stellt nach wie vor eine der größten Herausforderungen in der Halbleiterherstellung dar und erfordert ein grundlegendes Prozessverständnis. Diese Studie beinhaltet eine umfassende und detaillierte Untersuchung physikalischer und chemischer Wechselwirkungen von Siliziumätzprozessen in kapazitiv gekoppelten HBr/NF3-Gasentladungen in einem kommerziellen, typischerweise für die DRAM-Fertigung eingesetzten MERIE CCP Reaktor mit Ein- und Zweifrequenzanregung bei mittleren Entladungsdrücken. Die Anwendung eines Zweifrequenzkonzeptes zur separaten Kontrolle von Ionenenergie und Ionenstromdichte, als auch deren Einfluss auf die Entladungseigenschaften und letztendlich auf das Ätzverhalten auf relevanten Substratoberflächen wurden systematisch untersucht. Die komplexe Natur von mehrfrequenzangeregten HF-Randschichten wurde sowohl experimentell über eine Anwendung von massenaufgelöster Ionenenergieanalyse als auch rechnerisch über Simulationen von Ionenenergieverteilungsfunktionen mit Hilfe eines hybriden Plasmarandschichtmodells analysiert. Gaszusammensetzungen verschiedener Entladungen und Ätzprozesse wurden mit Hilfe von Standard-Massenspektrometrie, Schwellwert-Massenspektrometrie, Quantenkaskaden-Laserabsorptionsspektroskopie, HF-Sondenmessungen, Gravimetrie und Ellipsometrie charakterisiert. Eine neuartige Modellvorstellung zum Siliziumätzen in HBr/NF3-Entladungsgemischen liefert eine plausible Erklärung für die Limitierung der Ätzrate zum Erreichen eines hoch anisotropen Ätzverhaltens.

台灣DRAM晶圓廠目前所面臨的經營環境完全不是企業本身所能掌握的，但從發展的過程、歷史的軌跡及可能的演變，可觀察到台灣各晶圓廠，其實早已蘊釀且發展出”符合”自己的策略。本研究從基本供需問題為出發點，以影響決策之所處經營環境為背景，發現三點結論：第一、資源受限，限定策略彈性：台灣DRAM業者，在進入產業後因產能與資源有限，使經營規模受到限制，往往面臨環境變化時，用以抗衡變化的資源限制了策略彈性，也弱化應變的企業能力，半導體晶圓廠需要規模經濟藉以配置資源來因應變革，那一個晶圓廠在成長過程中的資源彈性越大(如組織資源之產能擴張、資產、能力交互運用)，企業日後的發展就易順遂；第二、企業經營者有其絕對的影響力，影響企業存活的手段：企業經營者在面對策略決策點時，誰的洞悉力夠、誰較有見解、誰愈能分辨產業潮流觀念的真偽(如十二吋廠趨勢)、誰具備較高風險承擔的能力，誰就能帶領企業走向活路，經營者的策略執著與一定程度的策略彈性同等重要，但在缺乏策略彈性及企業能力被弱化的前提下，很難兼顧到既要營運卓越，又要技術創新，遑論做好整合的工作，唯一可確定的是，企業領導人務必要求變、要創新，以求企業之生存；第三、策略聯盟合作模式：為了彌補前兩點的不足，台灣DRAM業者勢必要與產業內的佼佼者合作，不論技術研發、產能分享或分擔風險，誰的組合最好，誰就能勝出。至於選擇何種技術研發標的(即企業能力)、如何尋找好的技術合作夥伴、如何集中資源即時開發、並進一步擴大產品線組合規劃以回收投資或避開風險，是每一個台灣DRAM晶圓廠過去幾年來走過的歷程，也是未來幾年在思考企業策略時的必要方向。

台灣DRAM產業隨著國內幾座12吋廠的陸續加入營運，即將在全球DRAM產業中扮演舉足輕重的角色。就DRAM產業本身而言，由於期初廠房投資所需的金額非常高，能否藉由大量的銷貨以達成規模經濟，是產業內各公司能否獲利的關鍵因素。除此之外，產業內各公司也致力於提昇產品良率以及先進製程的研發。 本研究以華邦電、南科、力晶、茂德等四家公司為樣本，依其2001年至2004年之財務報表作為預估個案公司未來成長率及獲利率的依據，利用現金流量折現法採銷售導向及盈餘導向二種模式，依最樂觀、最可能發生與最悲觀等三種情境，估算其價格區間，並與個股目前之實際股價相比較，以推論目前股價的合理性及目前股價可能隱含的銷售成長率及盈餘成長率，另以敏感性分析將各個評價因子繪製成龍捲風圖來觀察個別關鍵評價因子對股價的影響程度。 實證結果顯示，華邦電、南科、力晶、茂德之股價合理區間分別為2.6元-22.41元、17.61元-45.09元、13.44元-32.70元、6.46元-19.07元。另在敏感度分析上，發現所有公司受銷售額成長率的影響最大。最後根據研究結果，再針對投資人、上市櫃公司以及後續研究者提出建議。

This thesis explores memory performance for smartphone workloads. We design a Video Conference Workload (VCW) to model typical smartphone usage. We describe a trace-based methodology which uses a software implementation to mimic the behaviour of specialised hardware accelerators. Our methodology stores dataflow information from the original application to maintain the relationships between requests. We first study seven address mapping schemes with our VCW, using a first-ready, first-come-first-served (FR-FCFS) memory scheduler. Our results show the best performing scheme is up to 82% faster than the worst. The VCW is memory intensive, with up to 86.8% bandwidth utilisation using the best performing scheme. We also test a Web Browsing and a set of computer vision workloads. Most are not memory intensive, with utilisation under 15%. Finally, we compare four schedulers and find that the FR-FCFS scheduler using the Write Drain mode [8] performed the best, outperforming the worst scheduler by 6.3%.

This thesis explores memory performance for smartphone workloads. We design a Video Conference Workload (VCW) to model typical smartphone usage. We describe a trace-based methodology which uses a software implementation to mimic the behaviour of specialised hardware accelerators. Our methodology stores dataflow information from the original application to maintain the relationships between requests. We first study seven address mapping schemes with our VCW, using a first-ready, first-come-first-served (FR-FCFS) memory scheduler. Our results show the best performing scheme is up to 82% faster than the worst. The VCW is memory intensive, with up to 86.8% bandwidth utilisation using the best performing scheme. We also test a Web Browsing and a set of computer vision workloads. Most are not memory intensive, with utilisation under 15%. Finally, we compare four schedulers and find that the FR-FCFS scheduler using the Write Drain mode [8] performed the best, outperforming the worst scheduler by 6.3%.

In order to resolve the Al void formation originated from the severe stress issues in dynamic random access memory (DRAM), double-deposited-aluminum (DDA) layer process was proposed. This novel metallization process can be effectively and simply performed with the native oxide such as Al 2 O 3 between upper and lower Al metal layer by ex-situ deposition technique. We could effectively control the Al void by adapting the DDA layers with different grain structure. From this novel metallization process, we have confirmed the optimal thickness of Al barrier metal to 100Å to be free from Al voids, which makes it possible to improve the static refresh characteristics of DRAM by 17%.