Made available in DSpace on 2014-12-17T14:00:17Z (GMT). No. of bitstreams: 1 FelipeHMO_DISSERT.pdf: 3354962 bytes, checksum: a758acb9f2bb7a31cde2e3bc40a8bacb (MD5) Previous issue date: 2013-03-04 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior / The dissertation intends to develop an investigation on the artistic existence in human beings with different bodies in society at different historical moments. In this regard and based on this scenario, the study develops a description of the stigmas production and how they are established, spread and interfere with the sociability among human beings regarded as normal and those with different bodies. Regarding the scenic arts, the text describes about the participation of artists with different bodies in the scene, specifically the freak show and postdramatic theater. The text also investigates aspects of the biography and the work of mexican artist Frida Kahlo, which underpin methodological proceedings and produce contribution to the creative process of performance Kahlo em mim Eu e(m) Kahlo , which is to investigate the practice of the scene in this dissertation / A disserta??o tem como objetivo realizar uma averigua??o sobre o fazer art?stico na exist?ncia dos seres humanos com corpos diferenciados na sociedade, em diferentes momentos hist?ricos. Neste sentido e com base neste panorama, o estudo elabora uma descri??o sobre a produ??o de estigmas e a forma como eles se instauram, se propagam e interferem na sociabilidade entre os seres humanos considerados normais e os com corpos diferenciados. No que tange as artes c?nicas, o texto faz uma descri??o acerca da participa??o dos artistas com corpos diferenciados na cena, especificamente do freak show e no teatro p?s-dram?tico. O texto tamb?m investiga aspectos da biografia e da obra da artista pl?stica mexicana Frida Kahlo, os quais fundamentam os procedimentos metodol?gicos e produzem aportes para o processo criativo da performance Kahlo em mim Eu e(m) Kahlo , que consiste na investiga??o da pr?tica da cena na disserta??o

[EN] SRAM technology has traditionally been used to implement processor caches since it is the fastest existing RAM technology.However,one of the major drawbacks of this technology is its high energy consumption.To reduce this energy consumption modern processors mainly use two complementary techniques: i)low-power operating modes and ii)low-power memory technologies.The first technique allows the processor working at low clock frequencies and supply voltages.The main limitation of this technique is that manufacturing defects can significantly affect the reliability of SRAM cells when working these modes.The second technique brings alternative technologies such as eDRAM, which provides minimum area and power consumption.The main drawback of this memory technology is that reads are destructive and eDRAM cells work slower than SRAM ones. This thesis presents three main contributions regarding low-power caches and heterogeneous technologies: i)an study that identifies the optimal capacitance of eDRAM cells, ii)a novel cache design that tolerates the faults produced by SRAM cells in low-power modes, iii)a methodology that allows obtain the optimal operating frequency/voltage level when working with low-power modes. Regarding the first contribution,in this work SRAM and eDRAM technologies are combined to achieve a low-power fast cache that requires smaller area than conventional designs and that tolerates SRAM failures.First,this dissertation focuses on one of the main critical aspects of the design of heterogeneous caches:eDRAM cell capacitance.In this dissertation the optimal capacitance for an heterogeneous L1 data cache is identified by analyzing the compromise between performance and energy consumption.Experimental results show that an heterogeneous cache implemented with 10fF capacitors offers similar performance as a conventional SRAM cache while providing 55% energy savings and reducing by 29% the cache area. Regarding the second contribution,this thesis proposes a novel organization for a fault-tolerant heterogeneous cache.Currently,reducing the supply voltage is a mechanism widely used to reduce consumption and applies when the system workload activity decreases.However,SRAM cells cause different types of failures when the supply voltage is reduced and thus they limit the minimum operating voltage of the microprocessor. In the proposal,memory cells implemented with eDRAM technology serve as backup in case of failure of SRAM cells, because the correct operation of eDRAM cells is not affected by reduced voltages. The proposed architecture has two working modes: high-performance mode for supply voltages that do not induce SRAM cell failures, and low-power mode for those voltages that cause SRAM cell failures. In high-performance mode, the cache provides full capacity, which enables the processor to achieve its maximum performance. In low-power mode, the effective capacity of the cache is reduced because some of the eDRAM cells are dedicated to recover from SRAM failures. Experimental results show that the performance is scarcely reduced (e.g. less than 2.7% across all the studied benchmarks) with respect to an ideal SRAM cache without failures. Finally,this thesis proposes a methodology to find the optimal frequency/voltage level regarding energy consumption for the designed heterogeneous cache. For this purpose, first SRAM failure types and their probabilities are characterized.Then,the energy consumption of different frequency/voltage levels is evaluated when the system works in low-power mode.The study shows that, mainly due to the impact of SRAM failures on performance,the optimal combination of voltage and frequency from the energy point of view does not always correspond to the minimum voltage. / [ES] La tecnología SRAM se ha utilizado tradicionalmente para implementar las memorias cache debido a que es la tecnología de memoria RAM más rápida existente.Por contra,uno de los principales inconvenientes de esta tecnología es su elevado consumo energético.Para reducirlo los procesadores modernos suelen emplear dos técnicas complementarias:i) modos de funcionamiento de bajo consumo y ii)tecnologías de bajo consumo.La primeras técnica consiste en utilizar bajas frecuencias y voltajes de funcionamiento.La principal limitación de esta técnica es que los defectos de fabricación pueden afectar notablemente a la fiabilidad de las celdas SRAM en estos modos.La segunda técnica agrupa tecnologías alternativas como la eDRAM,que ofrece área y consumo mínimos.El inconveniente de esta tecnología es que las lecturas son destructivas y es más lenta que la SRAM. Esta tesis presenta tres contribuciones principales centradas en caches de bajo consumo y tecnologías heterogéneas: i)estudio de la capacitancia óptima de las celdas eDRAM, ii)diseño de una cache tolerante a fallos producidos en las celdas SRAM en modos de bajo consumo, iii)metodología para obtener la relación óptima entre voltaje y frecuencia en procesadores con modos de bajo consumo. Respecto a la primera contribución,en este trabajo se combinan las tecnologías SRAM y eDRAM para conseguir una memoria cache rápida, de bajo consumo, área reducida, y tolerante a los fallos inherentes a la tecnología SRAM.En primer lugar,esta disertación se centra en uno de los aspectos críticos de diseño de caches heterogéneas SRAM/eDRAM: la capacitancia de los condensadores implementados con tecnología eDRAM.En esta tesis se identifica la capacitancia óptima de una cache de datos L1 heterogénea mediante el estudio del compromiso entre prestaciones y consumo energético.Los resultados experimentales muestran que condensadores de 10fF ofrecen prestaciones similares a las de una cache SRAM convencional ahorrando un 55% de consumo y reduciendo un 29% el área ocupada por la cache. Respecto a la segunda contribución,esta tesis propone una organización de cache heterogénea tolerante a fallos.Actualmente,reducir el voltaje de alimentación es un mecanismo muy utilizado para reducir el consumo en condiciones de baja carga.Sin embargo,las celdas SRAM producen distintos tipos de fallos cuando se reduce el voltaje de alimentación y por tanto limitan el voltaje mínimo de funcionamiento del microprocesador. En la cache heterogénea propuesta,las celdas de memoria implementadas con tecnología eDRAM sirven de copia de seguridad en caso de fallo de las celdas SRAM, ya que el correcto funcionamiento de las celdas eDRAM no se ve afectado por tensiones reducidas.La arquitectura propuesta consta de dos modos de funcionamiento: high-performance mode para voltajes de alimentación que no inducen fallos en celdas implementadas en tecnología SRAM, y low-power mode para aquellos que sí lo hacen. En el modo high-performance mode,el procesador dispone de toda la capacidad de la cache.En el modo low-power mode se reduce la capacidad efectiva de la cache puesto que algunas de las celdas eDRAM se dedican a la recuperación de fallos de celdas SRAM.El estudio de prestaciones realizado muestra que éstas bajan hasta un máximo de 2.7% con respecto a una cache perfecta sin fallos. Finalmente, en esta tesis se propone una metodología para encontrar la relación óptima de voltaje/frecuencia con respecto al consumo energético sobre la cache heterogénea previamente diseñada. Para ello,primero se caracterizan los tipos de fallos SRAM y las probabilidades de fallo de los mismos.Después,se evalúa el consumo energético de diferentes combinaciones de voltaje/frecuencia cuando el sistema se encuentra en un modo de bajo consumo.El estudio muestra que la combinación óptima de voltaje y frecuencia desde el punto de vista energético no siempre corresponde al mínimo voltaje debido al imp / [CAT] La tecnologia SRAM s'ha utilitzat tradicionalment per a implementar les memòries cau degut a que és la tecnologia de memòria RAM més ràpida existent.Per contra, un dels principals inconvenients d'aquesta tecnologia és el seu elevat consum energètic.Per a reduir el consum els processadors moderns solen emprar dues tècniques complementàries: i)modes de funcionament de baix consum i ii)tecnologies de baix consum.La primera tècnica consisteix en utilitzar baixes freqüències i voltatges de funcionament.La principal limitació d'aquesta tècnica és que els defectes de fabricació poden afectar notablement a la fiabilitat de les cel·les SRAM en aquests modes.La segona tècnica agrupa tecnologies alternatives com la eDRAM, que ofereix àrea i consum mínims.L'inconvenient d'aquesta tecnologia és que les lectures són destructives i és més lenta que la SRAM. Aquesta tesi presenta tres contribucions principals centrades en caus de baix consum i tecnologies heterogènies: i)estudi de la capacitancia òptima de les cel·les eDRAM, ii)disseny d'una cau tolerant a fallades produïdes en les cel·les SRAM en modes de baix consum, iii)metodologia per a obtenir la relació òptima entre voltatge i freqüència en processadors amb modes de baix consum. Respecte a la primera contribució, en aquest treball es combinen les tecnologies SRAM i eDRAM per a aconseguir una memòria cau ràpida, de baix consum, àrea reduïda, i tolerant a les fallades inherents a la tecnologia SRAM.En primer lloc, aquesta dissertació se centra en un dels aspectes crítics de disseny de caus heterogènies: la capacitancia dels condensadors implementats amb tecnologia eDRAM.En aquesta dissertació s'identifica la capacitancia òptima d'una cache de dades L1 heterogènia mitjançant l'estudi del compromís entre prestacions i consum energètic.Els resultats experimentals mostren que condensadors de 10fF ofereixen prestacions similars a les d'una cau SRAM convencional estalviant un 55% de consum i reduint un 29% l'àrea ocupada per la cau. Respecte a la segona contribució, aquesta tesi proposa una organització de cau heterogènia tolerant a fallades.Actualment,reduir el voltatge d'alimentació és un mecanisme molt utilitzat per a reduir el consum en condicions de baixa càrrega.Per contra, les cel·les SRAM produeixen diferents tipus de fallades quan es redueix el voltatge d'alimentació i per tant limiten el voltatge mínim de funcionament del microprocessador. En la cau heterogènia proposta, les cel·les de memòria implementades amb tecnologia eDRAM serveixen de còpia de seguretat en cas de fallada de les cel·les SRAM, ja que el correcte funcionament de les cel·les eDRAM no es veu afectat per tensions reduïdes.L'arquitectura proposada consta de dues maneres de funcionament: high-performance mode per a voltatges d'alimentació que no indueixen fallades en cel·les implementades en tecnologia SRAM,i low-power mode per a aquells que sí ho fan.En el mode high-performance,el processador disposa de tota la capacitat de la cau.En el mode low-power es redueix la capacitat efectiva de la cau posat que algunes de les cel·les eDRAM es dediquen a la recuperació de fallades de cel·les SRAM.L'estudi de prestacions realitzat mostra que aquestes baixen fins a un màxim de 2.7% pel que fa a una cache perfecta sense fallades. Finalment,en aquesta tesi es proposa una metodologia per a trobar la relació òptima de voltatge/freqüència pel que fa al consum energètic sobre la cau heterogènia prèviament dissenyada.Per a açò,primer es caracteritzen els tipus de fallades SRAM i les probabilitats de fallada de les mateixes.Després,s'avalua el consum energètic de diferents combinacions de voltatge/freqüència quan el sistema es troba en un mode de baix consum.L'estudi mostra que la combinació òptima de voltatge i freqüència des del punt de vista energètic no sempre correspon al mínim voltatge degut a l'impacte de les fallades de SRAM en les pres / Lorente Garcés, VJ. (2015). Cache architectures based on heterogeneous technologies to deal with manufacturing errors [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/58428 / TESIS

A significant portion of the memory in servers today is often unused. Our large-scale study of HPC systems finds that more than half of the total memory in active nodes running user jobs are unused for 88% of the time. Google and Azure Cloud studies also report unused memory accounts for 40% of the total memory in their servers, on average. Leaving so much memory unused is wasteful. To address this problem, we note that in the context of CPUs, Turbo Boost can turn off the unused cores to boost the performance of in-use cores. However, there is no equivalent technology in the context of memory; no matter how much memory is unused, the performance of in-use memory remains the same. This dissertation explores architectural techniques to utilize the unused memory to boost the performance of in-use memory and refer to them collectively as Memory Turbo Boost. This dissertation explores how to turbo boost memory performance through memory replication; specifically, it explores how to efficiently store the replicas in the unused memory and explores multiple architectural techniques to utilize the replicas to enhance memory system performance. Performance simulations show that Memory Turbo Boost can improve node-level performance by 18%, on average across a wide spectrum of workloads. Our system-wide simulations show applying Memory Turbo Boost to an HPC system provides 1.4x average speedup on job turnaround time. / Doctor of Philosophy / Today's servers often have a significant portion of their memory unused. Our large-scale study of HPC systems finds that more than half of the total memory of an HPC server is unused for most of the time; Google and Azure Cloud studies find that 40% of the total memory in their servers is often unused. Today's servers usually have 100s of GBs to TB memory; 40% unused memory means 10s-100s of GBs unused memory on the servers. Leaving so much memory unused is wasteful. To address this problem, I note that there are techniques to leverage unused hardware resources to improve the performance of in-use resources in other types of hardware. For example, CPU Turbo Boost can turn off the unused cores to boost the performance of in-use cores; modern SSDs can use the unused space to switch the Multi-Level Cell blocks to Single-Level Cell blocks to boost performance. However, there is no equivalent technology in the context of memory; no matter how much memory is unused, the performance of in-use memory remains the same. This dissertation explores techniques to utilize the unused memory to boost the performance of in-use memory and refer to them collectively as Memory Turbo Boost. Performance evaluations show that Memory Turbo Boost can provide up to 18% average performance improvement.

二十一世紀初的經濟不景氣橫掃了全球的DRAM製造產業，讓全世界的DRAM製造產商大賠了120億美金，國內廠商受傷尤其嚴重，甚至發生公司債之債務不履行事件，國內廠商岌岌可危。本論文主要係以案例探討之方式，研究國內DRAM製造廠商之經營模式、產業特性與風險管理問題，尤其在面對國際間產業劇烈之競爭下，國內之DRAM製造商的經營條件比國際大廠更為艱困，例如：金融環境、政府支援程度、生產規模、技術自主問題等與國外廠商皆有一段差距，因此在經營上所面對之風險與其他國家製造商相較，其實更為險峻。 / 本文以案例公司發生公司債之債務不履行事件為切入點，深入地了解一家在本國企業中屬於中大型企業之DRAM製造公司，為何會有債務不履行之情況發生？其近因似為案例公司在財務上過度倚賴公司債為籌資工具，且公司債之到期或轉換公司債之履約期間過於密集，以致產生流動性問題，然而其遠因乃在於DRAM產品價格快速的滑落，廠商缺乏適當的風險管理工具及機制以應付DRAM之價格風險。DRAM產品為成本競爭導向之標準產品，成本競爭來自於生產良率、製程微縮與新建更大尺寸廠房，當每家廠商都競逐於經濟規模以降低成本時產業會變得不穩定而暴起暴落，在產品價格處於高點時，所有廠商將產能利用率(稼動率)推到最高，此時因產能稼動率高，因此平均每單位晶片之生產成本較低，所以廠商獲利頗豐，並可輕易自資本市場取得資金擴充產能；等到市場供過於求，產品價格下跌處於低點時，廠商只好減產以降低損失，在其他條件不變下，此時因產能稼動率低，因此平均每單位晶片之生產成本反而較產品價格好時還要高，產品價格下跌所帶來的巨額損失，對廠商的虧損有乘數效果，此時廠商在資本市場或銀行等間接金融市場都不容易籌措到資金，本文以案例公司所面對之風險管理問題，提供幾個避險之建議，其中包括金融業、政府等應該能夠扮演更積極的角色，創造共贏共榮的局面，並避免類似之事件再發生，此為本文最大之貢獻。

記憶體產業是最10年隨著電腦及通訊產業的發展而快速崛起的產業，但也由於國際及國內各大廠前仆後繼的投資擴產，最近幾年面臨產能過剩及供過於求現象，而2008年遇全球不景氣，消費性電子產品需求疲弱不振，即使減產也難挽頹勢；而在記憶體產業如此惡劣環境下，本研究之個案公司-創見資訊，仍能維持一相對高而穩定之獲利，本研究係透過對其所處產業—記憶體模組/通路商之產業分析、及其歷史性財務報表分析加上相關預測資料，據以作為評價的基礎，評估出創見資訊之真實價值，得到以下研究結論： 一、記憶體應用之產品，因低價電腦 (Netbook) 及固態硬碟 (SSD) 相繼問市，產業前景仍十分樂觀，但其同時存在有同業間彼此產品差異性不大，未來競爭更趨激烈。 二、創見資訊已具備如充沛的營運資金、具一定經濟規模及領先之市占率、高品牌知名度、實質緊密的供應商關係、產品組合差異化、分散的代理商客戶、遍及全球的運籌網路及快速的新產品的開發速度等記憶體模組/通路商應有之關鍵成功因素。 三、創見資訊MVA 與EVA 相關性分析中得知的相關性高達0.80326，由此得知EVA變化對MVA 變化有很大的解釋能力，顯示該公司較無資訊不對稱問題。 四、銷售利潤率的變化造成創見資訊 ROIC下降主因，其主要係受到上游關鍵性原材料供過於求導致價格急速下跌，進而影響終端產品售價下滑幅度；雖然創見資訊過去五的移動平均ROIC 雖超過30%，但移動平均ROS 則逐漸下滑，甚至低於10%，加上移動平均資本週轉率走高，推論近年來逐漸傾向於Commodity Business。 五、創見資訊除因2006年預期Vista效應將帶來業績成長而積極備貨，造成2006 年存貨指標略有惡化外；而毛利指標雖均大於0，係由於近年來無論是上游關鍵原材料IC (約占製造成本80%以上)及產品售價亦大幅下跌之影響，若與同業較，其銷貨毛利指標已明顯優於其他同業；其他二個指標均在0左右，顯示其應收帳款、管銷費用並無不當膨脹，整體盈餘品質尚佳。 六、在經營績效方面，無論是現金週轉天數、營運現金流量與稅後淨利相比方面，創見資訊均呈逐年改善趨勢，而威剛科技則有逐漸惡化現象。 七、本研究發現，即使價格波動幅度劇烈，無論是毛利率或是ROIC表現，創見資訊均明顯優於威剛科技，且在因應關鍵性材料價格波動之能力亦優於威剛科技。 八、在評價分析方面，由銷售導向DCF 法評價出來的每股股東價值區間在64.86元~102.10元之間而盈餘導向DCF 法評價出來的可能股東價值區間為85.40元~115.50元，若與最近12個月平均市價89.95元相較，則兩個方法評價結果，仍具參考價值。 九、根據企業評價分析，在敏感性分析後，本研究發現要提升公司價值之各個價值因子的重要性依序為邊際利潤率＞銷售成長率＞盈餘成長率＞資金成本＞總投資/銷售率，此研究結果可提供公司經營者在排列策略優先順序時的重要參考。

本研究主要是探討台灣半導體產業中晶圓代工與動態隨機記憶體製造廠商競爭優勢有哪些？並且由價值鍵模型、市場-技術生命週期論著、策略矩陣模型、策略性資源模型及鑽石模型來探討。前面是以一般產業模型探討產業具有競爭優勢。 　　從產業現象中推理，歸納哪些具有競爭優勢條件，再經過模型加以應用、推導、驗證，更能使理論與實務相結合。 　　本研究運用Porter鑽石模型探討，找出每一構面因素的相關競爭優勢內涵。第一因素是生產要素，第二因素是需求條件，第三因素是企業策略、企業結構和競爭程度，第四因素是相關及支援性產業，第五因素是機會，第六因素是政府角色。之後依序探討各因素實際上在產業中成功因素內涵加以分析。並配合個案研究與個案深入訪談專家，依序分析國內最具代表性廠商所具有競爭優勢形成的因果關係，使得探討產業競爭優勢更趨完整。 本研究結果使得下列相關命題更具實質的意義。 1. （價值鍵模型）中探討產業競爭優勢、產業分工與群聚的效果。 2. （策略矩陣模型中）分析得知競爭優勢之基礎與條件。 3. （策略性資源模型）得知廠商組織能力培養與產品創新及有形資產之土地、廠房、設備購置時間之重要性。 4. （後進、先進地區市場-技術生命週期論著）：探討產業發展策略中進入成熟期時台灣晶圓代工與DRAM廠商在進入21世紀深次微米技術時，採取何種方式及步驟，保持競爭優勢。 5. （生產因素）資本資源探討，Venture Capital 投入，不僅止於資金挹注且提供經營資訊，銀行融資及推介策略性合夥人。 6. （企業策略、企業結構和競爭程度）國內該產業廠商之策略、管理型態及組織結構如：未來經營策略有合併、策略聯盟與競爭又合作方向，良好事業策略制定與執行影響廠商生存利基與競爭條件。 7. （機會）產業之機會，如國際IDM大廠製造轉移至台灣晶圓Foundry與DRAM廠商。3C商品整合趨勢，提高DRAM需求與掌握國際市場開拓能力，增加市場通路機會。 第一章 緒論……………………………………………………………… 1 1-1 研究背景與問題………………………………………………… 1 1-2 研究的目的……………………………………………………… 1 1-3 研究對象與範圍………………………………………………… 2 第二章 相關文獻探討…………………………………………………… 4 2-1 競爭優勢觀念之探討…………………………………………… 4 2-2 經營策略觀念之探討…………………………………………… 9 2-3 價值鍵探討……………………………………………………… 15 2-4 產業分析觀念之探討…………………………………………… 16 2-5 其他研究架構因素探討………………………………………… 22 2-6 相關理論架構模式之比較……………………………………… 23 第三章 研究設計………………………………………………………… 26 3-1 研究架構………………………………………………………… 26 3-2 研究流程………………………………………………………… 28 3-3 資料蒐集與分析………………………………………………… 29 3-4 研究方法………………………………………………………… 29 第四章 台灣半導體產業之晶圓代工與動態隨機存取記憶體競爭優勢探討…… 31 4-1 前言……………………………………………………………… 31 4-2 全球半導體產業發展現況與展望……………………………… 32 4-3 影響晶圓代工及DRAM需求因 ………………………………… 48 4-4 台灣DRAM製程技術及研發探討 -市場∼技術生命週期論…………………… 49 4-5 具競爭優勢生產成本與價格-價值鍵模型……………………… 54 4-6 專業服務導向與多樣化產品之競爭優勢-策略矩陣模型………… 56 4-7 專業晶圓代工與動態隨機記憶體製造-策略性資源模型………… 60 4-8 彈性經營管理強度與國際競爭能力…………………………… 70 4-9 整體績效改善與達成…………………………………………… 71 4-10 生產力與獲利能力之優勢……………………………………… 72 第五章 晶圓代工與動態隨機記憶體產業競爭力分析………………… 75 5-1 鑽石理論模型構面因素………………………………………… 75 5-2 生產要素………………………………………………………… 77 5-3 需求條件………………………………………………………… 95 5-4 公司實力、策略與競爭…………………………………………100 5-5 相關與支援產業…………………………………………………104 5-6 機會角色…………………………………………………………116 5-7 政府角色…………………………………………………………119 第六章 公司個案討論……………………………………………………126 6-1 個案介紹-聯華電子股份有限公司 ……………………………126 6-2 聯華電子公司策略性資源模型（一）…………………………130 6-3 聯華電子公司策略性資源模型（二）…………………………133 6-4 聯華電子公司「晶圓專工」策略-價值鍵模型………………136 6-5 個案介紹-台灣茂矽電子股份有限公司………………………138 6-6 台灣茂矽電子公司總體策略-產業價值鍵模型………………141 6-7 台灣茂矽電子公司策略性資源模型……………………………142 第七章 台灣半導體產業競爭優勢-Foundry & DRAM研究探討……145 第八章 結論與建議………………………………………………………161 參考文獻……………………………………………………………………164 附錄一訪談問卷…………………………………………………………169

人類經濟活動重心之變革推動著產業競爭的樣貌，於二十一世紀的今日，知識已成為經濟活動中最主要之價值驅力，與之相應的，產業中智慧財產層面的競爭也逐漸受到重視，發展至今，智慧財產已深入產業鏈且細化為各種以智慧財產運用為中心以創造獲利之企業。 半導體產業於台灣經濟發展之推進中佔有關鍵性之地位，隨著台灣廠商在全球產業鏈中扮演的角色重要性與日俱增，難以避免必須因應半導體產業中由智慧財產所造就的新興商業模式，其中，智慧財產研發公司拋棄舊有以生產製造為主之商業模式，開創以知識為本的競爭場域，並挾其智慧財產進行全球化的授權以及訴訟，扮演著遊戲規則的創造者，尤其記憶體產業之兩大智慧財產研發公司Rambus Inc.以及Tessera Technology Inc.，自2000年起不斷於全球提起專利訴訟，對整體產業乃至於台灣廠商帶來無法忽視之影響。 本研究試圖建立分析智慧財產研發公司之架構，亦即由該等公司之策略演進出發，宏觀的了解其於變動的競爭環境中如何發揮企業優勢；其次，以公司策略定位為基礎，進一步推動資源投入之分配，並形塑商業模式的產生；最後，本研究萃取智慧財產研發公司商業模式中較具特色且影響廣泛之訴訟階段，藉由記憶體產業中之個案分析比較之方式進行深入之實證研究，以管窺該等公司之專利運用模式，期能透過提升對於智慧財產研發公司策略定位、商業模式以及訴訟模式之了解，活化企業智慧財產之管理，並提供台灣廠商面對專利授權與訴訟時因應之基礎。 / The revolution of economic activities of human beings has been the force behind the changing format of competition among industries. In the contemporary 21st century, knowledge has become one of the most valuable forces in economic activities; correspondently, the competition strategy of intellectual property also seized much attention. As of today, intellectual property has already been integrated in each and every industry chains and developed into various enterprises which earn profits by operating it. Semi-conductor industry played an important role in the process of Taiwan’s economic development. As Taiwanese companies claim more crucial roles in the global industry chain, they are inevitably forced to deal with the new business model established by the creation of intellectual properties. Among them, intellectual property development companies have withdrawn from old business model of production and manufacturing and create a new competition field on the basis of intellectually properties. Intellectual property development companies engage in global wide license and litigation, acting as the rule-maker within the new frame of competition. Rambus Inc. and Tessera Technology Inc. are the two leading intellectual property development companies which brought lawsuits internationally since 2000, creating serious impacts on both the entire industry and Taiwanese companies. This research aims to establish an analytical framework to observe intellectually property development companies, starting from the progress of strategy, try to understand how to exercise their advantages in the ever-changing competitive business world; furthermore, based on business strategies, this research look further into the distribution of resources and the creation of business models; lastly, this research closely examines the litigation phase of the business model of intellectual property development companies by comparative case studies, in order to conclude the operation pattern of patents of such companies. With further exploration on the strategic positioning, business model and litigation pattern of intellectual property development companies, this research provides not only a deeper understanding on the management of IPRs but also a framework for Taiwanese companies to cope with patent licenses and litigations.

<div>The Internet-of-Things (IoT) is one of the fastest-growing technologies in computing, revolutionizing several application domains such as wearable computing, home automation, industrial manufacturing, <i>etc</i>. This rapid proliferation, however, has given rise to a plethora of new security and privacy concerns. For example, IoT devices frequently access sensitive and confidential information (<i>e.g.,</i> physiological signals), which has made them attractive targets for various security attacks. Moreover, with the hardware components in these systems sourced from manufacturers across the globe, instances of counterfeiting and piracy have increased steadily. Security mechanisms such as device authentication and key exchange are attractive options for alleviating these challenges.</div><div><br></div><div>In this dissertation, we address the challenge of enabling low-cost and low-overhead device authentication and key exchange in off-the-shelf embedded systems. The first part of the dissertation focuses on a hardware-intrinsic mechanism and proposes the design of two Physically Unclonable Functions (PUFs), which leverage the memory (DRAM, SRAM) in the system, thus, requiring minimal (or no) additional hardware for operation. Two lightweight authentication and error-correction techniques, which ensure robust operation under wide environmental and temporal variations, are also presented. Experimental results obtained from prototype implementations demonstrate the effectiveness of the design. The second part of the dissertation focuses on the application of these techniques in real-world systems through a new end-to-end authentication and key-exchange protocol in the context of an Implantable Medical Device (IMD) ecosystem. Prototype implementations exhibit an energy-efficient design that guards against security and privacy attacks, thereby making it suitable for resource-constrained devices such as IMDs.</div><div><br></div>

This paper describes various approaches to hardware testing semiconductor memory. We describe the priciple of basic memory types, the way which each of them stores information and their comunication protocol. Following part deals with common failures which may occur in the memory.  The section also describes the implementation of memory model and tester designed in VHDL language. It is possible to inject some errors into memory, which are later detected by the tester. The final section shows the response of tester to various error types according to used error detection method. The paper is especially focused on failure detection by variants of march test.

隨著全球經濟大海嘯浪潮湧來，先進國家普遍的購買力衰退，全球的資訊高科技行業正面臨著產品競爭的嚴峻挑戰。目前國內大多數IT行業在瞭解和滿足顧客需求、制定產品開發策略，組織成長策略以及用不同產品適應市場競爭的變化等方面，普遍存在問題。企業最高主管的一個重要任務是獲取、形成和配置組織資源。而科技是很多公司極其重要的一種資源，管理好這個資源贏得競爭優勢，需要把它與公司策略結合起來；企業最高主管第二個重要任務是形成和開發公司創新能力。這要求企業最高主管能夠評估公司擁有的創新能力，並且知道如何運用和改善它。 因此本研究的目的就是探討基於策略管理的企業成長理念、實用技能和有效方法，使我國電子產業能隨著環境的變遷有良性的發展軌道。經由對個案公司的研究與深入訪談，一方面更加了解個案公司所處的競爭環境、策略選擇與組織配置。另一方面，亦可從中歸納一些結論與建議，以期提供個案公司、其他業者、國內相關方面，長期生存與發展的另一思考方向，以及相關考慮議題。 本研究首先分析了個案公司策略制定的背景，繼而定義了個案公司的策略方向，包括：採取焦點市場的差異化、以接觸為基礎的策略、簡單策略、以及建立策略本領。以下分別陳述如下： 個案公司經策略分析，其發展的最好途徑是一採取策略導向、整合作業流程以及發揮策略資訊科技應用，來培養人才、開拓市場、防範風險、開發新產品和服務；另一方面是瞭解和掌握未來經濟發展趨勢、業界發展趨勢、確實掌握顧客通路，加快創新力度，爭取後來居上；此外，個案公司需要強化與策略、業務的契合。 在網路經濟和資訊經濟中，憑著資訊科技和網路技術，在各行業有許多默默無名的中小企業，都能後來居上，超過前者。可見資訊化以成為企業轉型與成長的關鍵成功因素之一。電子業是高度資本與科技導向的行業。透過企業發揮通路優勢和科技創新優勢，個案公司的績效才可望大幅度上升。 最後，對個案公司思考方向的建議如下： 1.在企業競爭激烈的環境下，並非僅有複製領先企業的做法即可成功，複製領先企業的做法不甚困難，困難的為此等做法背後所有涉及之策略、流程及人員。是以採行某一企業行動之前後，必須有一套完整的配套措施協助人員訓練與流程改造，方能達成企業經營運行之預期效益。 2.不一味追求新科技，忽略策略與管理之契合。策略之採用適當與否，端看是否能滿足顧客之需要與提供完善服務，以及是否能為企業帶來經營上之效益，而不是以追求最新科技為最主要目標，而是應該瞭解目前各種市場區隔科技使用情形，並針對需求變動隨時更新，以契合企業與顧客兩者之需求。