This dissertation focuses on design and implementation of a highly linear and low flicker-noise receiver front-end based on the direct conversion architecture for multiband applications in a CMOS technology. The dissertation consists of two parts: One, implementation of a highly linear RF receiver front-end and, two, implementation of a low flicker-noise RF receiver front-end based for direct conversion architecture. For multiband applications, key active components, highly linear LNAs and mixers, in the RF front-end receiver have been implemented in a 0.18um CMOS process. Theoretical approaches are analyzed from the perspective of implementation issues for highly linear receiver system and are also compared with measured results. Highly linear LNAs and mixers have been analyzed in terms of noise, linearity and power consumption, etc. For a low flicker-noise receiver front-end based on direct conversion architecture, the design of differential LNA and various low flicker-noise mixers are investigated in a standard 0.18um CMOS process. A differential LNA which shows high linearity was fabricated with a low flicker-noise mixer. Three low flicker-noise mixers were designed, measured and compared to the-state-of-the-arts published by other research institutes and companies.

<p>The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator.</p><p>A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal.</p><p>The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.</p>

As trends in broadband wireless communications applications demand faster development cycles, smaller sizes, lower costs, and ever increasing data rates, engineers continually seek new ways to harness evolving technology. The zero intermediate frequency receiver architecture has now become popular as it has both economic and size advantages over the traditional superheterodyne architecture.<p> Orthogonal Frequency Division Multiplexing (OFDM) is a popular multi-carrier modulation technique with the ability to provide high data rates over echo ladened channels. It has excellent robustness to impairments caused by multipath, which includes frequency selective fading. Unfortunately, OFDM is very sensitive to the carrier frequency offset (CFO) that is introduced by the downconversion process. The objective of this thesis is to develop and to analyze an algorithm for blind CFO recovery suitable for use with a practical zero-Intermediate Frequency (zero-IF) OFDM telecommunications system.<p> A blind CFO recovery algorithm based upon characteristics of the received signal's power spectrum is proposed. The algorithm's error performance is mathematically analyzed, and the theoretical results are verified with simulations. Simulation shows that the performance of the proposed algorithm agrees with the mathematical analysis.<p> A number of other CFO recovery techniques are compared to the proposed algorithm. The proposed algorithm performs well in comparison and does not suffer from many of the disadvantages of existing blind CFO recovery techniques. Most notably, its performance is not significantly degraded by noisy, frequency selective channels.

In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end. The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated. The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.

As trends in broadband wireless communications applications demand faster development cycles, smaller sizes, lower costs, and ever increasing data rates, engineers continually seek new ways to harness evolving technology. The zero intermediate frequency receiver architecture has now become popular as it has both economic and size advantages over the traditional superheterodyne architecture.<p> Orthogonal Frequency Division Multiplexing (OFDM) is a popular multi-carrier modulation technique with the ability to provide high data rates over echo ladened channels. It has excellent robustness to impairments caused by multipath, which includes frequency selective fading. Unfortunately, OFDM is very sensitive to the carrier frequency offset (CFO) that is introduced by the downconversion process. The objective of this thesis is to develop and to analyze an algorithm for blind CFO recovery suitable for use with a practical zero-Intermediate Frequency (zero-IF) OFDM telecommunications system.<p> A blind CFO recovery algorithm based upon characteristics of the received signal's power spectrum is proposed. The algorithm's error performance is mathematically analyzed, and the theoretical results are verified with simulations. Simulation shows that the performance of the proposed algorithm agrees with the mathematical analysis.<p> A number of other CFO recovery techniques are compared to the proposed algorithm. The proposed algorithm performs well in comparison and does not suffer from many of the disadvantages of existing blind CFO recovery techniques. Most notably, its performance is not significantly degraded by noisy, frequency selective channels.

<p>In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. </p><p>Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from several drawbacks such as extreme sensitivity to DC offsets, 1/f noise, local oscillator (LO) leakage/radiation, front-end nonlinearity and I/Q mismatch. This implies very high demands on the DCR front-end. </p><p>The front-end comprises a low-noise amplifier (LNA) and a mixer. Different LNA and mixer architectures has been studied and from the mentioned inherited problems with direct conversion, one proposal for a solution is a differential source degenerated LNA and a differential harmonic mixer, which has been designed and simulated. </p><p>The LNA has a gain of 12dB, a noise figure of 3.6dB and provides a return loss better than -15dB. The overall noise figure of the signal path is 8dB and the overall IIP3 and IIP2 is -12dBm and 31dBm, respectively.</p>

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The current consumption of the IQ modulator is a significant part of the totalcurrent consumption of a mobile transmitter platform and reducing it is of greatinterest. Also, as the WCDMA/LTE standards specifies full duplex transmissionsand Tx and Rx are most often using the same antenna, it is crucial to have asolution with low noise generation. Two new proposals have been studied with theaim to reduce the current consumption and noise contribution of the IQ modulator. A current mode envelope tracking IQM is the first of the studied designs. Thisimplementation lowers the bias currents in the circuit in relation to the amplitudeof the baseband input signals, meaning that a low input amplitude results in alowering of the current consumption. It proves to be very efficient for basebandsignals with a high peak-to-average ratio. Simulations and calculations have shownthat an average current reduction of 56 % can be achieved for an arbitrary LTEbaseband signal. The second is an entirely new passive mixer design where the baseband voltagesare sequentially copied to the RF node, removing the need for V-to-I conversion inthe mixer which reduces current consumption and noise. Results from simulationshas proven that this design is fully capable of improving both current consumptionas well as the noise levels. With an output power of 4.0 dBm, the power consumptionwas 43.3 mW, including clock generating circuits. This, combined with thefact that the design is small and simple, means that there is definitely a possibilityto replace the present IQM design with a passive mixer.

<p>Master thesis work at ITN (Department of Science and Technology) in the areas of A/D-construction and RF-circuit design. Major goal of project were to research suitable possibilities for implementations of direct conversion in transceivers operating in the 160MHz band, theoretic study followed by development of components in the construction environment Cadence. Suitable A/D- converter and other important parts were selected at the end of the theoretic study. Subsampling technique was applied to make A/D sample requirements more realistic to achieve. Besides lowering requirements on A/D-converter it allows a more simple construction, which saves more components than subsampling adds. Subsampling add extra noise, because of that an A/D-converter based on the RSD algorithm was chosen to improve error rate. To achieve high bit-processing rate compared to the used number of transistors, pipeline structure were selected as conversion method. The receiver was that part which gained largest attention because it’s the part which is most interesting to optimise. A/D-conversion is more difficult to construct than D/A conversion, besides there’s more to gain from eliminating mixers in the receiver than in the transmitter.</p>

The Decimator, an SED Systems Ltd. product, is a PCI slot card that performs both time and frequency domain measurements of given input signals. It is essentially a more economical version of a bench spectrum analyzer or oscilloscope, with a PC interface. Several issues limit the speed and accuracy of the results of the Decimator, and the study of these issues is the focus of this thesis. These issues, including but not limited to, are as follows: 1) Imbalances between the received In-phase and Quadrature-phase channels; 2) The FFT and Windowing functions are performed by a microcontroller, but it is desired that they be migrated to an FPGA. While solutions to improve the first issue is being implemented and verified, the second issue is not one of simply reducing a source of error. The second issue requires a cost-benefit analysis on the migration of these signal processing algorithms from an ARM microcontroller to a Xilinx FPGA.