The aim of this thesis is introduce readers to the basics of digital frequency synthesis and design of direct digital synthesizer with circuit AD9951 by Analog Devices. The device will be controlled from a PC via USB. The device works with internal oscillator, with the ability to connect an external frequency standard of 10 MHz. On input is frequency doubler with transistor. Outpu signal is filtered by low-pass filter and amplified by monolitic amplifier ERA-3+.

Implantable biomedical wireless sensors provide monitoring of vital health signs such as oxygen, temperature and intraocular pressure and may help to analyse and detect diseases in humans and animals. However, one of the design challenges of implantable devices is providing a safe and reliable energy source. Replaceable batteries are one of the most common methods for powering up implantable devices and have been used in e.g.cardiac pacemakers for decades. However, the need for a regular battery replacement may require surgical incisions. Multiple studies have been done on energy harvesting from ambient energy sources to provide the required power for the operation of the implantable sensor and thus reducing the need for battery replacement. In this work, a circuit-level radio frequency (RF) energy harvesting system has been designed and simulated in 65 nm CMOS process technology. The system consists of an AC-DC converter, a DC-DC converter, a Ring oscillator, a Buffer, and a Voltage sensor with comparators, dividers and a reference generator. The rectifier operates at a frequency of 900 MHz and offers a power conversion efficiency (PCE) of 71%. The doubler works at 50 MHz with a voltage conversion efficiency (VCE) of 98%. Additionally, the Voltage sensor monitors the voltage level of the energy-storing unit, that in this project is intended to be an mm-size rechargeable battery. If the voltage level is equal to or higher than a threshold value, Vref, the harvesting system will be in discharging mode. Similarly, if the voltage level is below Vref, then the system will be in charging mode.

Power converters used in high reliability radiation hardened space applications trail their commercial counterparts in terms of power density and efficiency. This is due to the additional challenges that arise in the design of space rated power converters from the harsh environment they need to operate in, to the limited availability of space qualified components and field demonstrated power converter topologies. New radiation hardened Gallium Nitride (GaN) Field Effect Transistors (FETs) with their inherent radiation tolerance and superior performance over Silicon Power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are a promising alternative to improve power density and performance in space power converters. This thesis presents the considerations and design of a practical implementation of the Phase Shifted Full Bridge DC-DC Isolated converter with synchronous rectification for space applications. Recently released radiation hardened GaN FETs were used in the Full Bridge and synchronous rectifier power stages. A survey outlining the benefits of new radiation hardened GaN FETs for space power applications compared to current radiation hardened power MOSFETs is included. In addition, this work presents the overall design process followed to design the DC-DC converter power stage, as well as a comprehensive power loss analysis. Furthermore, this work includes details to implement a conventional hard-switched Full Bridge DC-DC converter for this application. An efficiency and component stress comparison was performed between the hard-switched Full Bridge design and the Phase Shifted Full Bridge DC-DC converter design. This comparison highlights the benefits of phase shift modulation (PSM) and zero voltage switching (ZVS) for GaN FET applications. Furthermore, different magnetic designs were characterized and compared for efficiency in both converters. The DC-DC converters implemented in this work regulate the output to a nominal 20 V, delivering 500 W from a nominal 100 V DC Bus input. Complete fault analysis and protection circuitry required for a space-qualified implementation is not addressed by this work. / MS / Recently released radiation-hardened Gallium Nitride (GaN) Field Effect Transistors (FETs) offer the opportunity to increase efficiency and power density of space DC-DC power converters. The current state of the art for space DC-DC power conversion trails their commercial counterparts in terms of power density and efficiency. This is mainly due to two factors. The first factor is related to the additional challenges that arise in the design of space rated power converters from the harsh environment they need to operate in, to the limited availability of space qualified components and field demonstrated converter topologies. The second factor lies in producing reliable radiation hardened power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). GaN FETs not only have better electrical performance than power MOSFETs, they have also demonstrated inherent tolerance to radiation. This results in less structural device changes needed to make GaN FETs operate reliably under high radiation compared to their MOSFETs counterparts. This work outlines the design implications of using newly released radiation hardened GaN FETs to implement a fixed frequency isolated Phase Shifted Full Bridge DC-DC converter while strictly abiding to the design constraints found in space-power converter applications. In addition, a one-to-one performance comparison was made between the soft-switched Phase Shift modulated Full Bridge and the conventional hard-switched Full Bridge DC-DC converter. Finally, different magnetic designs were evaluated in the laboratory to assess their impact on converter efficiency.

The telecommunications market is one of the large rapidly growing fields in today’s power supply industry due to the increasing demand for telecom distributed power supply (DPS) systems. The half-bridge LLC (Inductor-Inductor-Capacitor) resonant converter is currently the most attractive topology for the design and implementation of 24V/48V DC telecom power converters. The current doubler rectifier (CDR) converter topology was invented and described in the early 1950s which can offer the unique characteristic of halving the output voltage while doubling the output current compared to a standard rectifier. In this thesis, the current doubler converter topology with its unique characteristic is evaluated as a complementary solution to improve the LLC resonant converter performance, especially for the low output voltage and high output current telecommunication applications. A novel half-bridge LLC resonant current doubler converter (LLC-CDR) is proposed in this thesis which can offer several performance benefits compared to conventional LLC-standard rectifier design . The unique characteristics of the LLC-CDR topology can offer significant improvements by transformation of a 48V converter into a 24V converter with the same power density. This thesis introduces a new SPICE-based simulation model to analyse the operation of this novel LLC-CDR converter circuit design. This model can be used to define the critical component parameters for the LLC -CDR circuit output inductor values. It can also be used to predict the circuit overall performance under different load conditions. Both time-domain based transient simulation analysis and frequency-domain based AC analysis provided by this simulation model showed favourable results in comparison to bench measurement results on a prototype. The model provides a valuable insight to reveal some of the unique characteristics of this LLC -CDR topology. It demonstrates a proof of concept that the conventional LLC resonant converter can be easily redesigned for low voltage, high current applications by using the LLC-CDR topology without requiring a new design for the LLC resonant stage components and the power transformer. A new magnetic integration solution was proposed to significantly improve the overall performance in the LLC-CDR topology that had not been published before. The LLC-CDR converter hardware prototypes with two output inductors coupled and uncoupled configurations were extensively modelled, constructed and bench tested.Test results demonstrated the suitability of an integrated coupled inductors design for the novel LLC-CDR converter application. The integrated coupled inductors design can significantly improve the LLC-CDR converter frequency-domain based AC simulation analysis results. In addition, these results also illustrate the potential benefit of how the magnetic integration design in general could reduce the magnetic component size, cost, and weight compared to the uncoupled inductors design. Finally, a hardware prototype circuit was constructed based on a commercial 1800 W single phase telecom power converter to verify the operation of this novel half bridge LLC-CDR topology. The converter prototype successfully operated at both no load and full load conditions with the nominal output voltage halved from 48VDC to 24VDC, and doubled the output current to match the same output power density. It also demonstrates that the efficiency of this novel half bridge LLC –CDR is 92% compares to 90% of EATON’s commercial 24VDC LLC resonant converter, which can fulfill the research goals.

<p>Designing an application specific integrated circuit (ASIC) must be starting with careful preparations, otherwise the chip will not be as good as possible. The theoretical studies must cover everything from the chip circuits to the application structure. In mobile applications there is extremely important that the current consumption becomes minimized because the battery power is limited. The power reductions studies must include the most power costing circuits on the chip. When the whole circuit or segments of the circuit is not in use, they must switch fast and simple into another mode that consume nearly none power. This mode is called sleep-mode. If the sleep-mode has very low leakage currents, the lifetime of the application will dramatically increase. </p><p>This report studies the most power costing circuits in smartcard application ASIC. The chip should be used to control a LCD display on the smartcard. The circuits that have been investigated are level shifters, charge pumps and LCD drivers, also sleep-mode configuration possibilities have been investigated. Other small preparing work is also included in the thesis.</p>

Designing an application specific integrated circuit (ASIC) must be starting with careful preparations, otherwise the chip will not be as good as possible. The theoretical studies must cover everything from the chip circuits to the application structure. In mobile applications there is extremely important that the current consumption becomes minimized because the battery power is limited. The power reductions studies must include the most power costing circuits on the chip. When the whole circuit or segments of the circuit is not in use, they must switch fast and simple into another mode that consume nearly none power. This mode is called sleep-mode. If the sleep-mode has very low leakage currents, the lifetime of the application will dramatically increase. This report studies the most power costing circuits in smartcard application ASIC. The chip should be used to control a LCD display on the smartcard. The circuits that have been investigated are level shifters, charge pumps and LCD drivers, also sleep-mode configuration possibilities have been investigated. Other small preparing work is also included in the thesis.

With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.

On-chip impedance tuning is used to overcome IC perturbations caused by packaging stress. Tuning is more important for matching networks of radio frequency (RF) systems. Possible package resonance and fabrication process variations may cause instability, which is a major problem in RF systems. Thus, precautions need to be taken in order to maintain the overall stability of components and the final system itself. Electrically erasable programmable read-only memory switches (EEPROMs) occupy less die area compared to e-fuses and microelectromechanical system (MEMS) switches, thus EEPROMs are proposed to be used as tuning switches in millimetre-wave (mm-wave) applications. It is anticipated that EEPROM switches will also enable multi-time programming because of the smaller area and the fact that more switches can be used for fine-tuning. The problem addressed in this research is how suitable EEPROMs are for switching applications in the mm-wave region. The main focus of this dissertation is to characterise the suitability of EEPROM switches qualitatively for tuning with systems operating in the mm-wave spectrum. 130 nm SiGe BiCMOS IBM 8HP process technology was used for simulation and the fabricated prototypes. The Dickson charge pump (CP), two voltage doubler CPs and four floating gate (FG) devices were investigated. Literature and theoretical verification was done using computer aided design (CAD) Cadence software through circuit analysis and the layouts were also designed for integrated circuit (IC) prototype fabrication. The qualitative evaluation of the hypothesis was based on investigating reliability issues, switching characteristics, CP output drive capability and mm-wave characterisation. The maximum measured drain current for FGs was 1.4 mA, 2.7 mA and 3 mA for devices 2, 3 and 4, respectively. The ratio between ON state switching current (after tunnelling) and OFF state switching current (after injection) was 1.5, 1.35 and 6 for devices 2, 3 and 4, respectively. The ratios correlated with the expected results in terms of FG transistor area: a high area results in a higher ratio. Despite the correlation, devices 2 and 3 may be unsuitable because the ratio is less than 2: a smaller ratio between the ON and OFF states could also result in higher losses. The Dickson CP achieved an output voltage of 2.96 V from an input of 1.2 V compared to 3.08 V as computed from the theoretical analysis and 4.5 V from the simulation results. The prototypes of the voltage doubler CP did not perform as expected: a maximum of 1 V was achieved compared to 4.1 – 5 V as in the simulation results. The suitability of FG devices for switching applications depends on the ratio of the ON and OFF states (associated to insertion and isolation losses): the larger the FG transistor area, the higher the ratio. The reliability issues are dominated by the oxide thickness of the transistor, which contributes to charge leakages and charge trapping: smaller transistor length causes more uncertainties. Charge trapping in the oxide increases the probability of leakages and substrate conduction, thus introduces more losses. Based on the findings of this research work, the FG devices promise to be suitable for mm-wave switching applications and there is a need for further research investigation to characterise the devices in the mm-wave region fully. AFRIKAANS : Impedansie-instelling op skyf word gebruik om steurings in geïntegreerde stroombane wat deur verpakkingstres veroorsaak word, te oorkom. Instelling is meer belangrik om netwerke van radiofrekwensiesisteme te paar. Moontlike verpakkingresonansie en variasies in die vervaardigingsproses kan onstabiliteit veroorsaak, wat ‟n groot probleem is in radiofrekwensiesisteme. Voorsorg moet dus getref word om die oorhoofse stabiliteit van komponente en die finale sisteem self te handhaaf. Elektries uitveebare programmeerbare slegs-lees-geheueskakelaars (EEPROMs) neem minder matrysarea op as e-sekerings en die sekerings van mikro-elektromeganiese sisteme en word dus voorgestel vir gebruik as instellingskakelaars in millimetergolfaanwendings. Daar word verwag dat EEPROM-skakelaars ook multi-tydprogrammering sal moontlik maak as gevolg van die kleiner area en die feit dat meer skakelaars gebruik kan word vir fyn instellings. Die probleem wat in hierdie navorsing aandag geniet, is die geskiktheid van EEPROMS vir skakelaanwendings in die millimetergolfstreek. The hooffokus van die verhandeling is om die geskiktheid van EEPROM-skakelaars kwalitatief te karakteriseer vir instelling met sisteme wat in die millimetergolfspektrum funksioneer. Department of Electrical, Electronic and Computer Engineering v University of Pretoria 130 nm SiGe BiCMOS IBM 8HP-prosestegnologie is gebruik vir simulasie en die vervaardigde prototipes. Die Dickson-laaipomp is gebruik vir simulasie en die vervaardigde prototipes. Die Dickson-laaipomp, twee spanningverdubbelinglaaipompe en vier swewendehektoestelle is ondersoek. Literatuur- en teoretiese verifikasie is gedoen met behulp van rekenaarondersteunde-ontwerp (CAD) Cadence-sagteware deur stroombaananalise en die uitleg is ook ontwerp vir die vervaardiging van geïntegreerdestroombaanprototipes. Die kwalitatiewe evaluasie van die hipotese is gebaseer op die ondersoek van betroubaarheidkwessies, skakelingeienskappe, laaipompuitsetdryfvermoë en millimetergolfkarakterisering. Die maksimum gemete dreineerstroom vir swewende hekke was 1.4 mA, 2.7 mA en 3 mA vir onderskeidelik toestelle 2, 3 en 4. Die verhouding tussen die AAN-toestand van die skakelstroom (na tonnelling) en die AF-toestand van die skakelstroom (na inspuiting) was 1.5, 1.35 en 6 vir toestelle 2, 3 en 4, onderskeidelik. Die verhoudings het ooreengestem met die verwagte resultate rakende die swewendehek-transistorareas: ‟n groot area het ‟n hoër verhouding tot gevolg. Nieteenstaande die ooreenstemming, mag toestelle 2 en 3 moontlik nie geskik wees nie, omdat die verhouding kleiner as 2 is: ‟n kleiner verhouding tussen die AAN- en AF-toestande mag ook hoër verliese tot gevolg hê. Die Dickson-laaipomp het ‟n uitsetspanning van 2.96 V vanaf ‟n inset van 1.2 V vergeleke met 3.08 V soos bereken volgens die teoretiese analise en 4.5 V volgens die simulasieresultate. Die prototipes van die spanningverdubbelinglaaipomp het nie gefunksioneer soos verwag is nie: ‟n maksimum van 1 V is bereik vergeleke met 4.1 – 5 V soos in die simulasieresultate. Die geskiktheid van swewendehektoestelle vir skakelingtoepassings hang af van die verhouding van die AAN- en AF-toestande (wat met invoer-en isolasieverlies geassosieer word): hoe groter die swewendehektransistorarea, hoe hoër die verhouding. Die betroubaarheidkwessies word oorheers deur die oksieddikte van die transistor, wat bydra tot ladinglekkasies en ladingvasvangs: korter transistorlengte veroorsaak meer onsekerheid. Ladingvasvangs in die oksied verhoog die moontlikheid van lekkasies en substraatgeleiding en veroorsaak dus groter verlies. Die bevindings van hierdie navorsing toon dat swewendehektoestelle waarskynlik geskik is vir millimetergolfaanwendings en verdere navorsing is nodig om die toestelle volledig in die millimetergolfstreek te karakteriseer. Copyright / Dissertation (MEng)--University of Pretoria, 2013. / Electrical, Electronic and Computer Engineering / unrestricted

The main aim of the thesis is to develop a solution of a frequency synthesizer for a microwave communication systems. Specifically, it suggests a design for frequency synthesizer with phase-locked loop. At beginning of the thesis the principle and basic properties of this method of signal generation are explained. Then it is followed by a brief discussion of the parameters of synthesizers and their influence on design. Another part of the work is the analysis of circuit the frequency synthesizer with the phase-locked loop MAX2871, which is followed by a proposal for the design of the frequency synthesizer module hardware. The last part of the work deals with practical implementation, verification of function and measurement of achieved parameters and their evaluation.