Master of Science / Department of Electrical Engineering / William Kuhn / When enough charges accumulate on two objects, the air dielectric between them breaks down to create a phenomenon known as electrostatic discharge (ESD). ESD is of great concern in the integrated circuit industry because of the damage it can cause to ICs. The problem will only become worse as process components become smaller. The three main types of ESD experienced by an IC are the human body model (HBM), the charged device model (CDM), and the machine model (MM). HBM ESD has the highest voltage while CDM ESD has the highest bandwidth and current of the three ESD types. Integrated circuits generally include ESD protection circuitry connected to their pads. Pads are the connection between the IC and the outside world, making them the required location for circuitry designed to route ESD events away from the IC's internal circuitry. The most basic protection pads use diodes connected from I/O to VDD and I/O to ground. A voltage clamp between VDD and ground is also necessary to protect against CDM and MM event types where the device may not yet have a low impedance supply path connected. The purpose of this research is to investigate the performance of ESD circuits and to develop a method for detecting the occurrence of an ESD event in an integrated circuit by utilizing IC fuses. The combination of IC fuses and detection circuitry designed to sense a broken fuse allows the IC to perform a built-in self-test (BIST) for ESD to identify compromised ICs, preventing manufacturers from shipping damaged circuits. Simulations are used to design an optimized protection circuit to complement the proposed ESD detection circuit. Optimization of an ESD pad circuit increases the turn-on speed of its voltage clamps and decreases the series resistance of its protection diodes. These improvements minimize the stress voltage placed on internal circuitry due to an ESD event. An ESD measurement setup is established and used to verify voltage clamp operation. This research also proposes an ESD detection circuit based on IC fuses, which fail during an ESD event. A variety of IC fuses are tested using the ESD measurement setup as well as a TLP setup in order to determine the time and current needed for them to break. Suitable IC fuses have a resistance less than 5 Ω and consistently break during the first trial.

Until approximately 50 years ago, wireless electronics was confined to military purposes. With the advancement of technology, consumer electronics found widespread applications in almost every aspect of our lives and numerous devices were developed using electromagnetic waves to transfer different types of data. In light of such advancements, the electromagnetic compatibility (EMC) evolved from a military concept to regulate the radio frequency requirements of the battlefield equipment to a mature and essential part in manufacturing and employing electronic devices. Medical devices were no exception and largely benefited from the ease of connectivity and mobility provided by usage of wireless electronics. Due to the sensitive nature of medical devices and extreme consequences of their malfunction, EMC grew to a centric issue in design and production of such devices. This work examines the electromagnetic compatibility of a wearable biomedical measurement system used for the assessment of mental stress of combatants in real time. This system was developed as a part of the ARTEC project and supported by the Spanish Ministry of Defense through the Future Combatant program [1]. We focus on the EMC of the electrocardiogram of the system and aim to identify its EMC requirements of this system while assessing it against various standards and protocols. Throughout this study, we elucidate the fundamentals of electromagnetic compatibility with specific attention to medical devices. Furthermore, we present our results after conducting several EMC tests to measure the compatibility of the electrocardiogram device using the Intertek guidelines. The emission test was performed while essential counter measures such as appropriate shielding and anti-interference filters had been applied.

Diplomová práce pojednává o překážkách voného pohybu pracovníků v judikatuře ESD. Nejprve se teoreticky věnuje právní úpravě této problematiky a přináší určitou typologii překážek volného pohybu pracovníků. Zvláštní pozornost je věnována překážkám vyplývajícím ze vzájemného uznávání diplomů a kvalifikací. Ve druhé části jsou uvedeny a okomentovány vybrané rozsudky Evropského soudního dvora dotýkající se dané tematiky.

In Australia, Integrated Coastal Zone Management (ICM) is the policy framework adopted by government to manage the coastal zone. Amongst other principles, ICM contains an explicit mandate to include local communities in the management of the coastal zone. In Australia, the Coastcare program emerged in response to international acceptance of the need to involve local communities in the management of the coastal zone. This dissertation is a critical cultural investigation of the Coastcare program to discover how the program and the coastal zone generally, is understood and negotiated by three volunteer groups in SE Queensland. There is a paucity of data surrounding the actual experiences of Coastcare volunteers. This dissertation begins to fill this gap in our knowledge of local community involvement in coastal management. My dissertation considers the culture of Coastcare and broadly, community participation initiatives. Coastcare participants, government policymakers, environmental scientists, etc bring to their encounter a specific ‘way of seeing’ the coast – a cultural framework – which guides their actions, ideas and priorities for the coastal zone. These cultural frameworks are established and maintained in the context of unequal relations of power and knowledge. The discourses of environmental science and economics – as evidenced in the chief ICM policy objective, Ecologically Sustainable Development (ESD) – are powerful knowledges in the realm of community participation policy. This arrangement has serious consequences for what governments and experts can expect to achieve via community participation programs. In short, the quest for ‘power-sharing’ with communities and ‘meaningful participation’ is impeded by dominant scientific and economic cultures which act to marginalise and discredit the cultures of communities (and volunteers). Ironically enough, the lack of consideration of these deeper relations of power and knowledge means that the very groups (such as policymakers, environmental scientists, etc) who actively seek the participation of local communities, contribute disproportionately to the relative failure of community participation programs. At the very least, as those in a position of power, policymakers and associated experts do little to enhance communication with local communities. To this situation add confusion wrought by changes in the delivery of the Coastcare program and a lack of human and financial resources. From this perspective, the warm and fuzzy sentiment of Coastcare can be understood as the ‘Coastcare of neglect’. However, the emergence of community participation as ‘legitimate’ in environmental policymaking indicates a fissure in the traditional power relations between communities and experts. Indeed the entry of ‘community participation policy’ is relatively new territory for the environmental sciences. It is this fissure which I seek to explore and encourage via the application of a cultural studies framework which offers another ‘way of seeing’ community participation in coastal and marine management and thereby, offers avenues to improve relations between communities and experts. My fieldwork reveals a fundamental mismatch between the cultural frameworks which communities bring to the coast and those frameworks embodied and implemented by the Coastcare program. Upon closer examination, it is apparent that the Coastcare program (and community participation programs generally) are designed to introduce local ‘lay’ communities to environmental science knowledge. Local coastal cultures are relegated to the personal and private realm. An excellent example of this is the scientifically oriented ‘eligible areas for funding’ of the Coastcare program. The volunteers consulted for this project emphasized their motivation in terms of ‘maintaining the natural beauty of the coast’ and ‘protecting a little bit of coast from the rampant development of the coastal zone’. Their motivations were largely the antithesis of ESD. They understood their actions as thwarting the negative impacts of coastal development – this occurred within a policy framework which accepted development as fait d’accompli. Australia’s nation of coastal dwellers may not know a lot about ‘coastal ecologies’ but they do know the coast in other ways. Community knowledge of the coast can be largely accounted for in the phrase, ‘Australian beach culture’. Serious consideration of Australian beach culture in environmental policy is absent. The lack of attention to this central tenet of the Australian way of life is because, as a concept and in practice, beach culture lacks the ‘seriousness’ and objectivity of environmental science knowledge – it is about play, hedonism, holidays, spirituality, emotion and fun. The stories (including Indigenous cultural heritage) which emerge when Australians are asked about their ‘beach cultural knowledge’ – historical and contemporary experiences of the Australian coast – await meaningful consideration by those interested in communicating with Australian communities living on the coast. This ‘cultural geography’ is an avenue for policymakers to better communicate and engage with Australian communities in their quest to increase participation in, or motivate interest in community coastal management programs.

While commitments made at the Rio+20 conference paved the road for the building of a green and fair economy, the ability of economics to provide a satisfactory intellectual framework to support this process has been increasingly questioned, particularly since the 2008 global financial crisis. In order to make economics more responsive to present and future challenges, this study argues that education in economics must be centred on the pursuit of sustainable development with what has been termed Education for Sustainable Development (ESD). To qualify as ESD, this paper contends that economics education must embrace pluralism on four levels (theoretical, methodological, disciplinary and pedagogical). This fourfold pluralism will improve economists’ capacity to deal with societal challenges and allow for the long-term building of resilient green-er and fair-er economies. The University of Versailles Saint-Quentin (France) Bachelor of Economics and Management is chosen as a case study to identify the current institutional factors hindering the opening of economics education to pluralism. The thesis draws on relevant literature in the field, and also utilises interviews undertaken with five economic professors teaching in the Bachelor. Following analysis of the case study, five main barriers to a plural economics education were found; these barriers are professionalisation, recruitment, evaluation, laziness and performance.

In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, product reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are scaling down, while ESD energy remains the same, VLSIs are becoming more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. Hence, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Furthermore with scaling, the integration of analog blocks such as ADC, PLL’s, DLL’s, oscillator etc. on digital chips has provided cheap system on chip (SOC) solutions. However, when analog and digital chip are combined into single mixed-signal chip, on-chip noise coupling from the digital to the analog circuitry through ESD protection circuits becomes a big concern. Thus, increasing supply noise isolation while ensuring the ESD protection robustness is also a big challenge. In this thesis, several ESD protection circuits and devices have been proposed to address the critical issues like increased leakage current, slower turn-on time of devices, increased susceptibility to power supply isolation etc. The proposed ESD protection circuits/devices have been classified into two categories: Pad based ESD protection in which the ESD protection circuits are placed in the I/O pads, and Rail based ESD in which ESD protection circuit is placed between power supplies. In our research, both these aspects have been investigated. The Silicon Controlled Rectifier (SCR) based devices have been used for Pad ESD protection as they have highest ESD protection level per unit area. Two novel devices Darlington based SCR (DSCR) and NMOS Darlington based SCR (NMOS-DSCR) having faster turn-on time, lower first breakdown voltage and low capacitance have been proposed. The transient clamps have been investigated and optimized for Rail based ESD protection. In this research, we have addressed the issue of leakage current in transient clamps. A methodology has been purposed to reduce the leakage current by more than 200,000 times without having major impact on the ESD performance. Also, the issue of noise coupling from digital supply to analog supply through the ESD protection circuits has been addressed. A new transient clamp has been proposed to increase the power supply noise isolation. Finally, a new methodology of placement of analog circuit with respect to transient clamp has been proposed to further increase the power supply noise isolation.

In spite of significant progress during last couple of decades, ESD still affects production yields, manufacturing costs, product quality, product reliability and profitability. The objective of an ESD protection circuit is to create a harmless shunting path for the static electricity before it damages the sensitive electronic circuits. As the devices are scaling down, while ESD energy remains the same, VLSIs are becoming more vulnerable to ESD stress. This higher susceptibility to ESD damage is due to thinner gate oxides and shallower junctions. Furthermore, higher operating frequency of the scaled technologies enforces lower parasitic capacitance of the ESD protection circuits. Hence, increasing the robustness of the ESD protection circuits with minimum additional parasitic capacitance is the main challenge in state of the art CMOS processes. Furthermore with scaling, the integration of analog blocks such as ADC, PLL’s, DLL’s, oscillator etc. on digital chips has provided cheap system on chip (SOC) solutions. However, when analog and digital chip are combined into single mixed-signal chip, on-chip noise coupling from the digital to the analog circuitry through ESD protection circuits becomes a big concern. Thus, increasing supply noise isolation while ensuring the ESD protection robustness is also a big challenge. In this thesis, several ESD protection circuits and devices have been proposed to address the critical issues like increased leakage current, slower turn-on time of devices, increased susceptibility to power supply isolation etc. The proposed ESD protection circuits/devices have been classified into two categories: Pad based ESD protection in which the ESD protection circuits are placed in the I/O pads, and Rail based ESD in which ESD protection circuit is placed between power supplies. In our research, both these aspects have been investigated. The Silicon Controlled Rectifier (SCR) based devices have been used for Pad ESD protection as they have highest ESD protection level per unit area. Two novel devices Darlington based SCR (DSCR) and NMOS Darlington based SCR (NMOS-DSCR) having faster turn-on time, lower first breakdown voltage and low capacitance have been proposed. The transient clamps have been investigated and optimized for Rail based ESD protection. In this research, we have addressed the issue of leakage current in transient clamps. A methodology has been purposed to reduce the leakage current by more than 200,000 times without having major impact on the ESD performance. Also, the issue of noise coupling from digital supply to analog supply through the ESD protection circuits has been addressed. A new transient clamp has been proposed to increase the power supply noise isolation. Finally, a new methodology of placement of analog circuit with respect to transient clamp has been proposed to further increase the power supply noise isolation.

Grön Flagg är en utmärkelse som i Sverige finns på cirka 2000 förskolor/skolor, där syftet är att utveckla och synliggöra arbetet för Hållbar utveckling. I tidigare examensarbeten har det undersökts om förskollärares upplevelser och uppfattningar av vad Grön Flagg är och bör vara i verksamheten. Vi har istället undersökt Grön Flagg-verksamheten utifrån tio barns upplevelser och beskrivningar. Sammanfattningsvis visar resultatet att barnen främst associerar Grön Flagg till sopor och källsortering och de anser att detta är viktigt för att djur och natur inte ska ta skada. De flesta av barnen uttryckte att det är roligt att arbeta utifrån Grön Flagg, och de gav många konkreta exempel på förskolans aktiviteter samt sina egna handlingar i vardagen. Studien visar att barnen överlag diskuterar inom fyra olika teman; kompostering, källsortering, naturruta och omsorg till djur. Undersökningen har även visat att barnens erfarenheter av Grön Flagg kan delas in i känslomässiga upplevelser och moraliska ståndpunkter, då de ofta ger exempel på regler på vad som är och inte är tillåtet att göra i naturen.

In modern integrated circuits, electrostatic discharge (ESD) is a major problem that influences the reliability of operation, yield and cost of fabrication. ESD discharge events can generate static voltages beyond a few kilo volts. If these voltages are dissipated in the chip, high electric field and high current are generated and will destroy the gate oxide material or melt the metal interconnects. In order to protect the chip from these unexpected ESD events, special protection devices are designed and connect to each pin of the IC for this purpose. With the scaling of nano-metric processing technologies, the ESD design window has become more critical. That leaves little room for designers to maneuver. A good ESD protection device must have superior current sinking ability and also does not affect the normal operation of the IC. The two main categories of ESD devices are snapback and non-snapback ones. Non-snapback designs usually consist of forward biased diode strings with properties, such as low heat and power, high current carrying ability. Snapback devices use MOSFET and silicon controlled rectifier (SCR). They exploit avalanche breakdown to conduct current. In order to investigate the properties of various devices, they need to be modeled in device simulators. That process begins with realizing a technology specific NMOS and PMOS in the device simulators. The MOSFET process parameters are exported to build ESD structures. Then, by inserting ESD devices into different simulation test-benches, such as human-body model or charged-device model, their performance is evaluated through a series of figures of merit, which include peak current, voltage overshoot, capacitance, latch-up immunity and current dissipation time. A successful design can sink a large amount of current within an extremely short duration, while it should demonstrate a low voltage overshoot and capacitance. In this research work, an inter-weaving diode and SCR hybrid device demonstrated its effectiveness against tight ESD test standards is shown.

No description available.