First, one of the purposes of this thesis is to estimate the complete crosstalk effects including the package and the pads on the surface acoustic wave (SAW) substrate. A new approach based on finite-difference time-domain (FDTD) with equivalent current source method is applied. Two kinds of patterns of one-port SAW resonators with the same package structure and inter-digital transducer (IDT) design are studied. Verification with the measurement results shows that our method is able to obtain good agreement and be used to observe the influence from the SAW pattern. Second, the equivalent current source method is extended to model the excitation of human-body¡¦s electrostatic discharge (ESD) situations. The efficiencies of sacrificial electrodes are also discussed. Finally, a novel sacrificial electrode with fractal to protect SAW devices from ESD break is proposed. Comparing with traditional electrode, the simulation results show that fractal can improve the protective efficiency greatly. Finally, a novel analysis model that can be used to analyze and optimize the impedance of an RFID transponder integrated circuit (IC) which uses backscatter encoding based on simultaneously maintaining the BER of the reader and maximizing the received power of the transponder IC is proposed. The analysis method utilizes mapping from signal constellation of the backscattered signal to the Smith chart to relate the two parameters. Given the system specification and characteristics of the reader and transponder antennas, the optimum impedances of transponder IC for binary communication system can be easily designed by using this model.

abstract: Electrostatic Discharge (ESD) is a unique issue in the electronics industry that can cause failures of electrical components and complete electronic systems. There is an entire industry that is focused on developing ESD compliant tooling using traditional manufacturing methods. This research work evaluates the feasibility to fabricate a PEEK-Carbon Nanotube composite filament for Fused Filament Fabrication (FFF) Additive Manufacturing that is ESD compliant. In addition, it demonstrates that the FFF process can be used to print tools with the required accuracy, ESD compliance and mechanical properties necessary for the electronics industry at a low rate production level. Current Additive Manufacturing technology can print high temperature polymers, such as PEEK, with the required mechanical properties but they are not ESD compliant and require post processing to create a product that is. There has been some research conducted using mixed multi-wall and single wall carbon nanotubes in a PEEK polymers, which improves mechanical properties while reducing bulk resistance to the levels required to be ESD compliant. This previous research has been used to develop a PEEK-CNT polymer matrix for the Fused Filament Fabrication additive manufacturing process / Dissertation/Thesis / Masters Thesis Engineering 2020

The thesis is divided into two parts, theoretical and empirical. In the first, the author explains the important terms for processing the empirical part. He deals with the theory of fire and summary of the general rules. He also deals with finding out the causes of fire and the computer program "Statistical monitoring of events", all the data were taken here. The chapter provides a general overview of el. devices, classification, history and possible danger. A very important of this part is the division of el. initiators explain. the terms such as el. short circuit, impedance, el. spark, el. arc, overcurrent, car-el. and its application in vehicles. Separately the author deals with atmospheric and ESD. The first objective was to analyze the causes of fires from el. devices in the South Bohemian Region (SBR). The second objective was the proposal of arrangements to improve the situation. The author determined two hypotheses: 1. The most common cause of fires of el. devices in the SBR is the el. short circuit. 2. The most frequent fires of el. devices in the SBR are the fires of vehicles. At the end of the first part, the author outlined the methodology. For processing the empirical part , he chose a quantitative research. The research was carried out by using the one-dimensional statistical analysis of data. The author created the list of literary sources based on literature gained from research libraries, the Fire Rescue Service (FRS) of the SBR, territorial department Strakonice and el. sources available on the internet. All the data the author gained SME of the FRS of the SBR. Within empirical part, the author first carried out the overall statistics of fires from el. initiators. The results show that in the period of 2009 - 2013 there was an increase in number of fires from el. initiators from 7,14 % to 14,97 %, it means more than double compared to a total amount of all fires, which have a decreasing tendency. Then he deals with proportions among particular initiators of fire. These data indicate that the most abundant initiator is car-el. and its application in vehicles. Other significant initiators are el. short circuit and impedance. Other initiators carry a much smaller proportion of the total number of fires. Then follow damages and salvage values caused. Salvage values in each of the monitored years are far greater than the damages, about 80 %. The author continues with the amount of people killed and injured, there is a big difference. Throughout the given period there were 5 people killed in fires from el. initiators, 51 people injured. For the total fires are numbers logically higher, in years 2009 - 2013 were 363 people injured and 51 killed. Then follows a part in which the author deals with individual initiators represented by el. short circuit, impedance, el. spark, el. arc, overcurrent, car-el. and its application in vehicles, atmospheric discharge and ESD. In the empirical part, there are also included initiators, which cannot be further specified. After processing the gained statistical data it comes to the discussion, in which the author analyzes particular tables and graphs, problems, which occurred with their solution and expresses to previously established hypotheses. The first hypothesis was refuted, the second confirmed. The author proposed measures to improve the situation, as there was detected a lack of security measures. The results of the thesis will be a contribution to the FRS of the Czech Republic, especially to the Prevention Department, pedagogical purposes or the general public in the context of preventive educational activities. After implementation of any of my proposals, using the same research it is possible to determine whether the implementation of the proposal has a positive impact on the number of fires, injured and killed people or on an amount of damages in the coming years.

Avec la nouvelle génération d'avions composites, une attention est portée sur les systèmes de carburant vis-à-vis de la prévention des décharges électrostatiques (ESD) durant les phases de remplissage des réservoirs. La plupart des travaux réalisés en aéronautique a été menée sur des réservoirs métalliques. Toutefois, l'introduction des matériaux composites a soulevé de nouvelles interrogations, puisque ces matériaux peuvent avoir un comportement différent des métaux vis-à-vis de l'électrisation par écoulement, qui justifient pleinement de nouvelles analyses. Afin de définir correctement les structures des réservoirs et leur protection contre les risques ESD, il est crucial de comprendre comment un empilement complexe de matériaux se comporte en termes de création de charge lorsque ces matières sont en contact avec un carburant d'avion. La structure de ces matériaux et leurs propriétés électriques contrôlent le potentiel électrique atteint dans le réservoir à travers un équilibre entre la production, l'accumulation et la fuite des charges électriques. Ce potentiel peut dépasser le point d'éclair du mélange air/vapeurs de carburant et provoquer une inflammation. Diverses mesures de protection peuvent être adoptées pour contrôler ce phénomène, comme utiliser des additifs antistatiques dans les carburants, des réservoirs métalliques à la masse ou encore des réservoirs faits de matériaux non métalliques mais ne favorisant pas l'accumulation de charges. C'est principalement en réponse à cette dernière solution que ce travail est orienté afin de guider vers le choix optimaux des matériaux et une meilleure définition des structures du réservoir. / With the new generation of composite aircrafts an attention is carried out on fuel systems with respect to prevention of electrostatic discharges (ESD) during the filling phases of the tanks. Most of the work realized in aeronautics (during the 60's) was conducted on metallic fuel tanks. However, the introduction of composite materials has raised new questions, since those materials can have a different behavior than metallic ones with respect to flow electrification, which fully justify new analyses. In order to properly define the tank structures and their protection against ESD hazards, it is crucial to understand how a complex stack of materials (conductive or not, multilayered or homogeneous, painted or not) constituting a fuel tank behaves with respect to the mechanisms of charge creation by flow electrification when these materials are in contact with aviation fuel. The structure of these materials and their electrical properties control the electric potential reached in the tank through a balance between the production, accumulation and leakage of the electrical charge. This potential may exceed the flash point of the fuel vapors/air mixture and induce ignition. Various protective measures can be adopted to control this phenomenon such as using antistatic additives in the fuels, lowering the rates ofthe fuel injection inside the tank, using only bonded metallic tanks or tanks made of non-metallic materials which do not favor charge accumulation or local charge trapping. It is majorly in response to the latter solution that this work is oriented in order to guide optimum choices of materials and a better definition of the tank structures.

Electrostatic Discharge (ESD), an event of a sudden transfer of electrons between two bodies at different potentials, happens commonly throughout nature. When such even occurs on integrated circuits (ICs), ICs will be damaged and failures result. As the evolution of semiconductor technologies, increasing usage of automated equipments and the emerging of more and more complex circuit applications, ICs are more sensitive to ESD strikes. Main ESD events occurring in semiconductor industry have been standardized as human body model (HBM), machine model (MM), charged device model (CDM) and international electrotechnical commission model (IEC) for control, monitor and test. In additional to the environmental control of ESD events during manufacturing, shipping and assembly, incorporating on-chip ESD protection circuits inside ICs is another effective solution to reduce the ESD-induced damage. This dissertation presents design, characterization, integration and compact modeling of novel silicon controlled rectifier (SCR)-based devices for on-chip ESD protection. The SCR-based device with a snapback characteristic has long been used to form a VSS-based protection scheme for on-chip ESD protection over a broad rang of technologies because of its low on-resistance, high failure current and the best area efficiency. The ESD design window of the snapback device is defined by the maximum power supply voltage as the low edge and the minimum internal circuitry breakdown voltage as the high edge. The downscaling of semiconductor technology keeps on squeezing the design window of on-chip ESD protection. For the submicron process and below, the turn-on voltage and sustain voltage of ESD protection cell should be lower than 10 V and higher than 5 V, respectively, to avoid core circuit damages and latch-up issue. This presents a big challenge to device/circuit engineers. Meanwhile, the high voltage technologies push the design window to another tough range whose sustain voltage, 45 V for instance, is hard for most snapback ESD devices to reach. Based on the in-depth elaborating on the principle of SCR-based devices, this dissertation first presents a novel unassisted, low trigger- and high holding-voltage SCR (uSCR) which can fit into the aforesaid ESD design window without involving any extra assistant circuitry to realize an area-efficient on-chip ESD protection for low voltage applications. The on-chip integration case is studied to verify the protection effectiveness of the design. Subsequently, this dissertation illustrate the development of a new high holding current SCR (HHC-SCR) device for high voltage ESD protection with increasing the sustain current, not the sustain voltage, of the SCR device to the latchup-immune level to avoid sacrificing the ESD protection robustness of the device. The ESD protection cells have been designed either by using technology computer aided design (TCAD) tools or through trial-and-error iterations, which is cost- or time-consuming or both. Also, the interaction of ESD protection cells and core circuits need to be identified and minimized at pre-silicon stage. It is highly desired to design and evaluate the ESD protection cell using simulation program with integrated circuit emphasis (SPICE)-like circuit simulation by employing compact models in circuit simulators. And the compact model also need to predict the response of ESD protection cells to very fast transient ESD events such as CDM event since it is a major ESD failure mode. The compact model for SCR-based device is not widely available. This dissertation develops a macromodeling approach to build a comprehensive SCR compact model for CDM ESD simulation of complete I/O circuit. This modeling approach offers simplicity, wide availability and compatibility with most commercial simulators by taking advantage of using the advanced BJT model, Vertical Bipolar Inter-Company (VBIC) model. SPICE Gummel-Poon (SGP) model has served the ICs industry well for over 20 years while it is not sufficiently accurate when using SGP model to build a compact model for ESD protection SCR. This dissertation seeks to compare the difference of SCR compact model built by using VBIC and conventional SGP in order to point out the important features of VBIC model for building an accurate and easy-CAD implement SCR model and explain why from device physics and model theory perspectives.

Overcrowding during indoor events can be risky, in-case of any kind of a hazard such as fire.This solution address this by providing real-time crowd detection solution using Force-SensingResistor (FSR) sensors, referred sensor (IR) and microcontrollers. The solution needs to offer accurate data in real-time to the event managers including number of people and entrancerate to help when and if the event areas will be overcrowded, thereby enhancing event safetyand decision-making. This thesis indicate that the system offers essential real-time data forevent safety with an accuracy of 87.25%. These data will assists event managers in makinginformed decisions to avoid the risks of overcrowding. This thesis evaluates the effectivenessof our system in comparison to other systems, discussing what we’ve learned, suggest possibleimprovements, and talk about whether our system could be useful in real-world indoor events.

Silicon-on-Insulator (SOI) CMOS technology constitutes a good candidate for mixed signal RF CMOS applications. Due to its low junction capacitance and reduced leakage current, SOI provides reduced static and dynamic power consumption of the digital logic combined with increased cut-off frequencies. Moreover, in terms of passive device integration the major benefit of SOI when compared to the conventional bulk is the possibility to use a high resistivity substrate which allows a drastic reduction of substrate losses allowing a high quality factor of the passive devices. Another issue is the harsh environment applications. Electronics capable of operating at high temperatures are required in several industrial applications, including the automobile industry, the aerospace industry, the electrical and nuclear power industries, and the well-logging industry. The capability of SOI circuits to expand the operating temperature range of integrated circuits up to 300°C has been demonstrated. SOI devices and circuits present advantages in this field over bulk counterparts such as the absence of thermally-activated latch up and reduced leakage current. In this context, various topologies of integrated transmission lines and spiral inductors implemented on standard and high substrate resistivities have been analyzed over a large temperature range. The temperature behavior of the SOI transistors is presented. The main figures-of-merit of the SOI MOSFETs are analyzed and the extraction of the extrinsic and intrinsic parameters of the small signal equivalent circuit is performed. Also, an example of RF circuit applications of the SOI technology, based on a fully integrated Low-Noise Amplifier for low-power and narrow-band applications, is investigated and characterized at high temperature. The main figures-of-merit of the designed circuit are extracted and discussed. The good results show that the SOI technology is now emerging as a good candidate for the realization of analog integrated circuits for low-power and high-temperature applications.

The technology evolution and complexity of new circuit applications involve emerging reliability problems and even more sensitivity of integrated circuits (ICs) to electrostatic discharge (ESD)-induced damage. Regardless of the aggressive evolution in downscaling and subsequent improvement in applications' performance, ICs still should comply with minimum standards of ESD robustness in order to be commercially viable. Although the topic of ESD has received attention industry-wide, the design of robust protection structures and circuits remains challenging because ESD failure mechanisms continue to become more acute and design windows less flexible. The sensitivity of smaller devices, along with a limited understanding of the ESD phenomena and the resulting empirical approach to solving the problem have yielded time consuming, costly and unpredictable design procedures. As turnaround design cycles in new technologies continue to decrease, the traditional trial-and-error design strategy is no longer acceptable, and better analysis capabilities and a systematic design approach are essential to accomplish the increasingly difficult task of adequate ESD protection-circuit design. This dissertation presents a comprehensive design methodology for implementing custom on-chip ESD protection structures in different commercial technologies. First, the ESD topic in the semiconductor industry is revised, as well as ESD standards and commonly used schemes to provide ESD protection in ICs. The general ESD protection approaches are illustrated and discussed using different types of protection components and the concept of the ESD design window. The problem of implementing and assessing ESD protection structures is addressed next, starting from the general discussion of two design methods. The first ESD design method follows an experimental approach, in which design requirements are obtained via fabrication, testing and failure analysis. The second method consists of the technology computer aided design (TCAD)-assisted ESD protection design. This method incorporates numerical simulations in different stages of the ESD design process, and thus results in a more predictable and systematic ESD development strategy. Physical models considered in the device simulation are discussed and subsequently utilized in different ESD designs along this study. The implementation of new custom ESD protection devices and a further integration strategy based on the concept of the high-holding, low-voltage-trigger, silicon controlled rectifier (SCR) (HH-LVTSCR) is demonstrated for implementing ESD solutions in commercial low-voltage digital and mixed-signal applications developed using complementary metal oxide semiconductor (CMOS) and bipolar CMOS (BiCMOS) technologies. This ESD protection concept proposed in this study is also successfully incorporated for implementing a tailored ESD protection solution for an emerging CMOS-based embedded MicroElectroMechanical (MEMS) sensor system-on-a-chip (SoC) technology. Circuit applications that are required to operate at relatively large input/output (I/O) voltage, above/below the VDD/VSS core circuit power supply, introduce further complications in the development and integration of ESD protection solutions. In these applications, the I/O operating voltage can extend over one order of magnitude larger than the safe operating voltage established in advanced technologies, while the IC is also required to comply with stringent ESD robustness requirements. A practical TCAD methodology based on a process- and device- simulation is demonstrated for assessment of the device physics, and subsequent design and implementation of custom P1N1-P2N2 and coupled P1N1-P2N2//N2P3-N3P1 silicon controlled rectifier (SCR)-type devices for ESD protection in different circuit applications, including those applications operating at I/O voltage considerably above/below the VDD/VSS. Results from the TCAD simulations are compared with measurements and used for developing technology- and circuit-adapted protection structures, capable of blocking large voltages and providing versatile dual-polarity symmetric/asymmetric S-type current-voltage characteristics for high ESD protection. The design guidelines introduced in this dissertation are used to optimize and extend the ESD protection capability in existing CMOS/BiCMOS technologies, by implementing smaller and more robust single- or dual-polarity ESD protection structures within the flexibility provided in the specific fabrication process. The ESD design methodologies and characteristics of the developed protection devices are demonstrated via ESD measurements obtained from fabricated stand-alone devices and on-chip ESD protections. The superior ESD protection performance of the devices developed in this study is also successfully verified in IC applications where the standard ESD protection approaches are not suitable to meet the stringent area constraint and performance requirement.

Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices’ operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs iv subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diodetriggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the end

Les circuits intégrés (CI) devenant de plus en plus complexes et vulnérables face aux décharges électrostatiques (ESD pour ElectroStatic Discharge), la capacité à vérifier de manière fiable la présence de défauts de conception ESD sur des puces comptant plusieurs milliards de transistors avant tout envoi en fabrication est devenu un enjeu majeur dans l’industrie des semi-conducteurs. Des outils commerciaux automatisés de dessin électronique (EDA pour Electronic Design Automation) et leur flot de vérification associé permettent d’effectuer différents types de contrôles qui se sont révélés être efficaces pour des circuits avec une architecture classique. Cependant, ils souffrent de limitations lorsqu’ils sont confrontés à des architectures inhabituelles, dites custom. De plus, ces méthodes de vérification sont généralement effectuées tard dans le flot de conception, rendant toute rectification de dessin coûteuse en termes d’efforts correctifs et de temps. Cette thèse de doctorat propose une méthodologie de vérification ESD systématique et multi-échelle introduite dans un outil appelé ESD IP Explorer qui a été spécifiquement implémenté pour couvrir le flot de conception dans sa globalité et pour adresser des circuits dits custom. Il est composé d’un module de reconnaissance et d’un module de vérification. Le module de reconnaissance identifie tout d’abord et de manière automatisée les structures de protection ESD, embarquées sur silicium dans le circuit intégré pour améliorer leur robustesse ESD, selon un mécanisme de reconnaissance topologique. Le module de vérification convertit ensuite le réseau de protection ESD, formé des structures de protection ESD, en un graphe dirigé. Finalement, une analyse ESD quasi-statique reposant sur des algorithmes génériques issus de la théorie des graphes est effectuée sur la globalité du circuit à vérifier. Des algorithmes d’apprentissage automatique ont été employés pour prédire les comportements quasi-statiques des protections ESD à partir des paramètres d’instance de leurs composants élémentaires sous la forme d’une liste d’interconnexions. L’avantage ici est qu’aucune simulation électrique n’est requise pendant toute la durée d’exécution d’ESD IP Explorer, ce qui simplifie l’architecture de l’outil et accélère l’analyse. Les efforts d’implémentation ont été concentrés sur la compatibilité d’ESD IP Explorer avec le nœud technologique 28nm FD-SOI (pour Fully Depleted Silicon On Insulator). L’outil de vérification développé a été utilisé avec succès pour l’analyse d’un circuit incorporant des parties numériques et à signaux mixtes et comprenant plus de 1,5 milliard de transistors en seulement quelques heures. Des circuits custom qui n’ont pas pu être vérifiés au moyen d’outils de vérification traditionnels du fait de problèmes d’incompatibilité ont également pu être soumis à analyse grâce à ESD IP Explorer. / As Integrated Circuits (ICs) become more complex and susceptible to ElectroStatic Discharges (ESD), the ability to reliably verify the presence of ESD design weaknesses over a multi-billion transistor chip prior to the tape-out is a major topic in the semiconductor industry. Commercial tools dedicated to Electronic Design Automation (EDA) and related verification flows are in charge of providing checks that have been proven to be efficient for circuits with a mainstream architecture. However, they suffer limitations when confronted with custom designs. Moreover, these verification methods are often run late in the design flow, making any design re-spin costly in terms of corrective efforts and time. This Ph. D. thesis proposes a systematic and scalable ESD verification methodology embodied in a tool called ESD IP Explorer that has been specifically implemented to cover the entire design flow and to comply with custom circuit architectures. It is composed of a recognition module and a verification module. The recognition module first automatically identifies ESD protection structures, embedded in integrated circuits to enhance their ESD hardness, according to a topology-aware recognition mechanism. The verification module then converts the ESD protection network that is formed by ESD protection structures into a directed graph. There, technology-independent and graph-based verification mechanisms perform a chip-scale quasistatic ESD analysis. Machine learning algorithms have been used in order to infer the quasistatic behavior of ESD IPs from the netlist instance parameters of their primary devices. This approach has the advantage that no simulation is required during the execution of ESD IP Explorer, which makes the tool architecture simpler and improves execution times. Implementation efforts pertained to the compliance of ESD IP Explorer with the 28nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The developed verification tool has been used to successfully analyze a digital and mixed-signal circuit prototype counting more than 1.5 billion transistors in several hours, as well as custom designs that could not be analyzed by means of traditional verification tools due to incompatibility issues.