Dual gate MOSFET structures such as FinFETs are widely regarded as the most promising option for continued scaling of silicon based transistors after 2010. This work examines key process modules that enable reduction of both device area and fin width beyond requirements for the 16nm node. Because aggressively scaled FinFET structures suffer significantly degraded device performance due to large source/drain series resistance (RS/D), several methods to mitigate RS/D such as maximizing contact area, silicide engineering, and epitaxially raised S/D have been evaluated.

abstract: Recent years have seen fin field effect transistors (finFETs) dominate modern complementary metal oxide semiconductor (CMOS) processes, [1][2], e.g., at the sub 20 nm technology nodes, as they alleviate short channel effects, provide lower leakage, and enable some continued VDD scaling. However, a realistic finFET based predictive process design kit (PDK) that supports investigation into both circuit and physical design, encompassing all aspects of digital design, for academic use has been unavailable. While the finFET based FreePDK15 was supplemented with a standard cell library, it lacked full physical verification (LVS) and parasitic extraction at the time [3][4]. Consequently, the only available sub 45 nm educational PDKs are the planar CMOS based Synopsys 32/28 nm and FreePDK45 (45 nm PDK) [5][6]. The cell libraries available for those processes are not realistic since they use large cell heights, in contrast to recent industry trends. Additionally, the SRAM rules and cells provided by these PDKs are not realistic. Because finFETs have a 3D structure, which affects transistor density, using planar libraries scaled to sub 22 nm dimensions for research is likely to give poor accuracy. Commercial libraries and PDKs, especially for advanced nodes, are often difficult to obtain for academic use, and access to the actual physical layouts is even more restricted. Furthermore, the necessary non disclosure agreements (NDAs) are un manageable for large university classes and the plethora of design rules can distract from the key points. NDAs also make it difficult for the publication of physical design as these may disclose proprietary design rules and structures. This work focuses on the development of realistic PDKs for academic use that overcome these limitations. These PDKs, developed for the N7 and N5 nodes, even before 7 nm and 5 nm processes were available in industry, are thus predictive. The predictions have been based on publications of the continually improving lithography, as well as estimates of what would be available at N7 and N5. For the most part, these assumptions have been accurate with regards to N7, except for the expectation that extreme ultraviolet (EUV) lithography would be widely available, which has turned out to be optimistic. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2019

Indiana University-Purdue University Indianapolis (IUPUI) / In this thesis, we investigated the 7 nm FinFET technology for its delay-power product performance. In our study, we explored the ASAP7 library from Arizona State University, developed in collaboration with ARM Holdings. The FinFET technology was chosen since it has a subthreshold slope of 60mV/decade that enables cells to function at 0.7V supply voltage at the nominal corner. An emphasis was focused on characterizing the Non-Ideal effects, delay variation, and power for the FinFET device. An exhaustive analysis of the INVx1 delay variation for different operating conditions was also included, to assess the robustness. The 7nm FinFET device was then employed into 6T SRAM cells and 16 function ALU. The SRAM cells were approached with advanced multi-corner stability evaluation. The system-level architecture of the ALU has demonstrated an ultra-low power system operating at 1 GHz clock frequency.

As we move under the aegis of the Moore's law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node.

L'intégration de composés semi-conducteurs III-V sur silicium devrait conduire au développement de nouveaux dispositifs micro- et optoélectroniques performants. Le composé InGaAs de haute mobilité électronique est un candidat prometteur pour le transistor métal-oxyde-semiconducteur à effet de champ à canal n au-delà du noeud technologique 10 nm. En outre les semi-conducteurs III-V sont aussi des matériaux appropriés pour la fabrication de composants optiques (lasers, diodes) et de dispositifs analogiques ultra-haute fréquence et leur intégration sur une plateforme Si ajoutera de nouvelles fonctionnalités pour le réseau de communications optiques. Cependant la miniaturisation des dispositifs et leur intégration dans les architectures 3D nécessitent le développement de méthodes de caractérisation avancées pour fournir des informations sur leur composition physico-chimique avec une résolution à l'échelle nanométrique.Dans cette thèse, les études physico-chimiques des hétérostructures III-V directement élaborées sur plaquettes de Si 300 mm par épitaxie en phase vapeur sont adressées. Les techniques de spectrométrie de masse d'ions secondaires sont utilisées et développées dans le but d'étudier la raideur des interfaces, la composition chimique et le dopage de couches III-V minces dans des architectures 2D et 3D avec une bonne résolution en profondeur. L'analyse quantitative précise sur un puits quantique InGaAs (PQ) pour des architectures 2D et 3D a été réalisée en utilisant les techniques SIMS magnétique et Auger. Pour obtenir le profil chimique des structures III-V étroites et répétitives, une méthode de moyenne des profils a été développée pour ces deux techniques. Egalement, la reconstruction 3D et le profil en profondeur de tranchées individuelles (moins de cent nanomètres de largeur) contenant un PQ d’InGaAs mince obtenu par croissance sélective dans des cavités de dioxyde de silicium en utilisant la méthode de piégeage des défauts par rapport d’aspect ont été obtenus avec succès en utilisant le SIMS à temps de vol ainsi que la sonde atomique tomographique. Enfin, les résultats ont été corrélés avec des mesures de photoluminescence. / The integration of III-V semiconductor compounds on silicon should lead to the development of new highly efficient micro- and opto-electronic devices. High mobility InGaAs material is a promising candidate for n-channel metal-oxide semiconductor field-effect transistor beyond the 10 nm technology node. Moreover III-V semiconductors are also suitable materials for fabrication of optical (lasers, diodes) and ultra-high frequency analog devices and their integration on a Si platform will add new functionalities for optical network and communication. However the miniaturization of devices and their integration into 3D architectures require the development of advanced characterization methods to provide information on their physico-chemical composition with nanometer scale resolution.In this thesis, the physico-chemical studies of III-As heterostructures directly grown on 300 mm Si wafers by metalorganic vapor phase epitaxy are addressed. Secondary ion mass spectrometry techniques are used and developed in order to study interfaces abruptness, chemical composition and doping of III-V thin layers in 2D and 3D architectures with high depth resolution. The accurate quantitative analysis on InGaAs quantum wells (QWs) in 2D and 3D architectures was performed using magnetic SIMS and Auger techniques. To obtain the chemical profiling of narrow and repetitive III-V structures the averaging profiling method was developed for both techniques. Additionally, 3D reconstruction and depth profiling of individual trenches (less than hundred nanometer in width) containing thin InGaAs QWs selectively grown in silicon dioxide cavities using the aspect ratio trapping method were successfully obtained using Time-of-flight SIMS and atom probe tomography. Finally, the results were correlated with photoluminescence measurements.

Este trabalho apresenta o estudo de transistores de tunelamento controlados por efeito de campo, denominados TFETs. Foram realizadas análises com base em explicação teórica, simulação numérica e medidas experimentais para demonstrar a viabilidade do uso desta tecnologia como alternativa para permitir o contínuo escalamento de dispositivos. A motivação para o uso de transistores com corrente principal resultante do tunelamento de banda para banda consiste na proposta de superar o limite físico de inclinação de sublimiar da tecnologia CMOS convencional de 60 mV/década sob temperatura ambiente. Afinal, esta limitação impede a redução na tensão de alimentação de circuitos e, consequentemente, apresenta crescentes problemas quanto à dissipação de potência. Com este objetivo, foram realizadas simulações numéricas de diversas geometrias alternativas visando atenuar as características indesejáveis dos TFETs, como a corrente ambipolar e a relativamente baixa relação ION/IOFF. Inicialmente são definidos os modelos necessários para representar adequadamente os fenômenos relevantes sob variação de temperatura e é definida uma estrutura capaz de minimizar os efeitos da ambipolaridade. Posteriormente, medidas experimentais foram utilizadas para calibrar as simulações e estudar o efeito da temperatura e do dimensionamento no funcionamento de dispositivos desta tecnologia. Comparando resultados práticos e simulados, nota-se como uma redução no comprimento de porta, com a consequente inserção de uma subposição (underlap) em relação à junção canal/dreno, e uma diminuição na temperatura permitem a obtenção de valores promissores de inclinação de sublimiar e de relação ION/IOFF, compatível com a proposta de futuras aplicações digitais e analógicas. / This works presents the study of tunneling field effect transistors, namely TFETs. Analyses were performed based on theoretical explanations, numerical simulations and experimental data in order to show this technology suitability as an alternative for the continuous devices scaling. The basic idea of making use of band-to-band tunneling as the main current component comes from the possibility of reaching sub-60 mV/decade subthreshold slopes at room temperature, differently from conventional CMOS devices. After all, this physical limitation causes relevant power dissipation issues, since it requires relatively high power supply voltages. Bearing this objective, numerical simulations of several alternative geometries were performed in order to tackle TFETs disadvantages, as the undesirable ambipolar currents and the low ION/IOFF ratio. At first, it was necessary to choose the most appropriate models to take into consideration the relevant phenomena under temperature variation and to define the physical structure in order to minimize ambipolar effects. After these analyses, experimental data were used to calibrate simulation parameters and to study how temperature and physical dimensions affect the performance of devices based on this technology. Comparing experimental and simulated results, it was possible to notice that when the structure is designed with gate underlap related to channel/drain junction and the temperature decreases, the obtained values for subthreshold slope and ION/IOFF ratio may be used as an important reference of this technology as a promising alternative for both digital and analog applications.

Este trabalho apresenta o estudo de transistores de tunelamento controlados por efeito de campo, denominados TFETs. Foram realizadas análises com base em explicação teórica, simulação numérica e medidas experimentais para demonstrar a viabilidade do uso desta tecnologia como alternativa para permitir o contínuo escalamento de dispositivos. A motivação para o uso de transistores com corrente principal resultante do tunelamento de banda para banda consiste na proposta de superar o limite físico de inclinação de sublimiar da tecnologia CMOS convencional de 60 mV/década sob temperatura ambiente. Afinal, esta limitação impede a redução na tensão de alimentação de circuitos e, consequentemente, apresenta crescentes problemas quanto à dissipação de potência. Com este objetivo, foram realizadas simulações numéricas de diversas geometrias alternativas visando atenuar as características indesejáveis dos TFETs, como a corrente ambipolar e a relativamente baixa relação ION/IOFF. Inicialmente são definidos os modelos necessários para representar adequadamente os fenômenos relevantes sob variação de temperatura e é definida uma estrutura capaz de minimizar os efeitos da ambipolaridade. Posteriormente, medidas experimentais foram utilizadas para calibrar as simulações e estudar o efeito da temperatura e do dimensionamento no funcionamento de dispositivos desta tecnologia. Comparando resultados práticos e simulados, nota-se como uma redução no comprimento de porta, com a consequente inserção de uma subposição (underlap) em relação à junção canal/dreno, e uma diminuição na temperatura permitem a obtenção de valores promissores de inclinação de sublimiar e de relação ION/IOFF, compatível com a proposta de futuras aplicações digitais e analógicas. / This works presents the study of tunneling field effect transistors, namely TFETs. Analyses were performed based on theoretical explanations, numerical simulations and experimental data in order to show this technology suitability as an alternative for the continuous devices scaling. The basic idea of making use of band-to-band tunneling as the main current component comes from the possibility of reaching sub-60 mV/decade subthreshold slopes at room temperature, differently from conventional CMOS devices. After all, this physical limitation causes relevant power dissipation issues, since it requires relatively high power supply voltages. Bearing this objective, numerical simulations of several alternative geometries were performed in order to tackle TFETs disadvantages, as the undesirable ambipolar currents and the low ION/IOFF ratio. At first, it was necessary to choose the most appropriate models to take into consideration the relevant phenomena under temperature variation and to define the physical structure in order to minimize ambipolar effects. After these analyses, experimental data were used to calibrate simulation parameters and to study how temperature and physical dimensions affect the performance of devices based on this technology. Comparing experimental and simulated results, it was possible to notice that when the structure is designed with gate underlap related to channel/drain junction and the temperature decreases, the obtained values for subthreshold slope and ION/IOFF ratio may be used as an important reference of this technology as a promising alternative for both digital and analog applications.

Neste trabalho, é apresentada uma análise da operação analógica de transistores de múltiplas portas, avaliando a tensão Early, o ganho de tensão em malha aberta, a razão da transcondutância pela corrente de dreno (gm/IDS), a condutância de dreno e, em especial, a distorção harmônica, exibida por estes dispositivos. Ao longo deste trabalho, foram estudados FinFETs, dispositivos de porta circundante (Gate-All-Around GAA) com estrutura de canal gradual (Graded-Channel GC) e transistores MOS sem junções (Junctionless - JL). Inicialmente, foi efetuada a análise da distorção harmônica apresentada por FinFETs com e sem a presença de tensão mecânica biaxial, com diversas larguras de fin (Wfin) e comprimentos de canal (L), quando estes operavam em saturação, como amplificadores de um único transistor. Nesta análise, as não-linearidades foram avaliadas através da extração das distorções harmônicas de segunda e terceira ordens (HD2 e HD3, respectivamente), mostrando que a presença de tensão mecânica tem pouca influência em HD2, mas altera levemente a HD3. Quando os ganhos de tensão em malha aberta dos dispositivos são levados em conta, transistores sem tensão, também chamados de convencionais, mais estreitos apresentam grande vantagem em termos de HD2 em relação aos tensionados. Ainda nesta análise, percebeu-se que HD2 e HD3 de transistores tensionados pioram com a redução da temperatura, especialmente em inversão mais forte. Na seqüência, foi efetuada uma análise de HD3 em FinFETs com e sem tensão mecânica de vários comprimentos e larguras de canal, operando em região triodo e aplicados a estruturas balanceadas 2-MOS, mostrando que presença de tensão mecânica traz pouca influência em HD3, mas reduz a resistência do canal dos dispositivos (RON), o que não é bom em estruturas resistivas, como as avaliadas. Nesta análise, ainda, pode-se perceber uma melhora em HD3 superior a 30 dB ao se incrementar VGT de zero a 1,0 V, em cuja tensão dispositivos mais estreitos apresentam curvas mais lineares que os mais largos. Então, foi estudada a distorção apresentada por transistores GAA e GC GAA operando em regime triodo, aplicados a estruturas 2-MOS, onde se pôde perceber que GC GAAs com maiores comprimentos da região fracamente dopada apresentam vantagem em HD3 em relação aos demais, para valores de VGT superiores a 2 V. Na avaliação destas estruturas em função da temperatura, percebeu-se que, para VGT superiores a 1,1 V, HD3 depende fortemente da temperatura e piora conforme a temperatura diminui. O estudo envolvendo transistores sem junções foi mais focado em seus parâmetros analógicos, comparando-os aos apresentados por dispositivos de porta tripla ou FinFETs. Em inversões moderada e forte, transistores sem junção apresentaram menores valores para gm/IDS em relação a dispositivos de FinFETs polarizados em um mesmo nível de corrente, entretanto, a dependência de gm/IDS com a temperatura em transistores sem junção também foi menor que a apresentada por FinFETs. JL e FinFETs apresentaram comportamentos distintos para a tensão Early e o ganho de tensão em malha aberta em função da temperatura. Estes parâmetros sempre melhoram com o aumento da temperatura em dispositivos JL, enquanto que exibem seu máximo valor em temperatura ambiente em FinFETs. Nas proximidades da tensão de limiar, transistores sem junção com largura de fin de 30 nm exibiram tensão Early e ganho superiores a 80 V a 57 dB, respectivamente, enquanto que FinFETs mostraram Tensão Early de 35 V e ganho de 50 dB. Em todos os estudos efetuados ao longo do trabalho, procurou-se apontar as causas das não-linearidades apresentadas pelos dispositivos, a partir de modelos analíticos que pudessem relacionar a física de funcionamento dos transistores com os resultados experimentalmente obtidos. / In this work it is presented an analysis of the analog operation of multiple gate transistors, evaluating the Early Voltage, the open-loop voltage gain, the transconductance over the drain current ratio (gm/IDS), the drain conductance and, especially, the harmonic distortion exhibited by these devices. Along the work, FinFETs, Gate-All-Around (GAA) devices with the Graded-Channel (GC) structure and MOS transistors without junctions (Junctionless - JL) were studied. Initially, an analysis of the harmonic distortion presented by conventional and biaxially strained FinFETs with several fin widths (Wfin) and channel lengths (L) was performed, when these devices were operating in saturation as single transistor amplifiers. In this analysis, the non-linearities were evaluated through the extraction of the second and the third order harmonic distortions (HD2 and HD3, respectively), and it was shown that the presence of strain has negligible influence in HD2, but slightly changes HD3. When the open loop voltage gain of the devices is taken into consideration, narrower conventional transistors present a huge advantage with respect to the strained ones in terms of HD2. Also, it was perceived that both HD2 and HD3 of strained FinFETs worsen with the temperature decrease, especially in stronger inversion. In the sequence, an analysis of the HD3 presented by conventional and strained FinFETs of several fin widths and channel lengths operating in the triode regime was performed. These devices were applied to 2-MOS balanced structures, showing that the presence of the strain does not influence significantly the HD3, but reduces the resistance in the channel of the transistors (RON), which is not good for resistive structures as the ones evaluated. In this analysis, it can also be observed an HD3 improvement of 30 dB when VGT is increased from zero up to 1,0 V, where narrower devices present transfer characteristics more linear than the wider ones. Then, it was studied the distortion presented by GAA and GC GAA devices operating in the triode regime, applied to 2-MOS structures. In this case, it could be perceived that GC GAAs with longer lightly doped regions present better HD3 in comparison to the other devices for VGT higher than 2.0 V. In the evaluation of these structures as a function of the temperature, it could be seen that for VGT higher than 1.1 V, HD3 strongly depends on the temperature and worsens as the temperature decreases. The study involving JL transistors was focused on their analog parameters, comparing them to the ones presented by triple gate devices or FinFETs. In moderate and strong inversions, Junctionless showed lower values for gm/IDS with respect to triple gate devices biased at a similar current level. However, the dependence of gm/IDS from Junctionless with the temperature was also smaller than the one presented by FinFETs. Junctionless and FinFETs exhibited distinct behaviors for the Early voltage and the open-loop voltage gain as a function of the temperature. These parameters always improve with the temperature raise in JL devices whereas they exhibit their maximum values around room temperatures for FinFETs. In the proximity of the threshold voltage, Junctionless with fin width of 30 nm presented Early voltage and intrinsic gain larger than 80 V and 57 dB, respectively, whereas FinFETs exhibited Early voltage of 35 V and gain of 50 dB. For all the studies performed in this work, the probable causes of the non-linearities were pointed out, from analytic models that could correlate the physical work of the devices with the experimental results.

Die kontinuierliche Skalierung der planaren MOSFETs war in den vergangenen 40 Jahren der Schlüssel, um die Bauelemente immer kleiner und leistungsfähiger zu gestalten. Hinzu kamen Techniken zur mechanischen Verspannung, Verfahren zur Kurzzeitausheilung, die in-situ-dotierte Epitaxie und neue Materialien, wie das High-k-Gateoxid in Verbindung mit Titannitrid als Gatemetall. Jedoch erschwerten Kurzkanaleffekte und eine zunehmende Streuung der elektrischen Eigenschaften die Verkleinerung der planaren Transistoren erheblich. Somit gelangten die planaren MOSFETs mit der aktuellen 28 nm-Technologie teilweise an die Grenzen ihrer Funktionalität. Diese Arbeit beschäftigt sich daher mit der Integration von Multi-Gate-Transistoren auf Basis einer 22 nm-Technologie, welche eine bessere Steuerfähigkeit des Gatekontaktes aufweisen und somit die Fortführung der Skalierung ermöglichen. Zudem standen die Anforderungen eines stabilen und kostengünstigen Herstellungsprozesses als Grundvoraussetzung zur Übernahme in die Volumenproduktion stets mit im Vordergrund. Die Simulationen der Tri-Gate-Transistoren stellten dabei den ersten Schritt hin zu einer Multi-Gate-Technologie dar. Ihre Prozessabfolge unterscheidet sich von den planaren Transistoren nur durch die Formierung der Finnen und bietet damit die Möglichkeit eines hybriden 22 nm-Prozesses. Am Beispiel der Tri-Gate-Transistoren wurden zudem die Auswirkungen der Kristallorientierung, der mechanischen Verspannung und der Überlagerungseffekte es elektrischen Feldes auf die Leistungsfähigkeit von Multi-Gate-Strukturen analysiert. Im nächsten Schritt wurden Transistoren mit vollständig verarmten Kanalgebieten untersucht. Sie weisen aufgrund einer niedrigen Kanaldotierung eine Volumeninversion, eine höhere Ladungsträgerbeweglichkeit und eine geringere Anfälligkeit gegenüber der zufälligen Dotierungsfluktuation auf, welche für leistungsfähige Multi-Gate-Transistoren entscheidende Kriterien sind. Zu den betrachteten Varianten zählen die planaren ultradünnen SOI-MOSFETs, die klassischen FinFETs mit schmalen hohen Finnen und die vertikalen Nanowire-Transistoren. Anschließend wurden die Vor- und Nachteile der verschiedenen Transistorstrukturen für eine mittel- bis langfristige industrielle Nutzung betrachtet. Dazu erfolgte eine Analyse der statistischen Schwankungen und eine Skalierung hin zur 14 nm-Technologie. Eine Zusammenfassung aller Ergebnisse und ein Ausblick auf die mögliche Übernahme der Konzepte in die Volumenproduktion schließen die Arbeit ab. / Within the past 40 years the continuous scaling of planar MOSFETs was key to shrink the devices and to improve their performance. Techniques like mechanical stressing, rapid thermal annealing and in-situ doped epitaxial growing as well as novel materials, such as high-k-gate-oxide in combination with titanium nitride as metal-gate, has been introduced. However, short-channel-effects and increased scattering of electrical proper-ties significantly complicate the scaling of planar transistors. Thus, the planar MOSFETs gradually reached their limits of functionality with the current 28 nm technology node. For that reason, this work focuses on integration of multi-gate transistors based on a 22 nm technology, which show an improved gate control and allow a continuous scaling. Furthermore, the requirements of a stable and cost-efficient process as decisive condition for mass fabrication were always taken into account. The simulations of the tri-gate transistors present the first step toward a multi-gate technology. The process sequence differs from the planar one solely by a fin formation and offers the possibility of a hybrid 22 nm process. Also, the impact of crystal orientation, mechanical stress and superposition of electrical fields on the efficiency of multi-gate structures were analyzed for the tri-gate transistors. In a second step transistors with fully depleted channel regions were studied. Due to low channel doping they are showing a volume inversion, a higher carrier mobility and a lower sensitivity to random doping fluctuations, which are essential criteria for powerful multi-gate transistors. Reviewed structure variants include planar ultra-thin-body-SOI-MOSFETs, classic FinFETs with a tall, narrow fins and vertical nanowire transistors. Then advantages and disadvantages of the considered transistor structures have been observed for a medium to long term industrial use. For this purpose, an analysis of statistical fluctuations and the scaling-down to 14 nm technology was carried out. A summary of all results and an outlook to the transfer of concepts into mass fabrication complete this work.

L’augmentation des performances des dispositifs de la microélectronique repose encore pour une dizaine d’années sur une miniaturisation des circuits intégrés. Cette miniaturisation s’accompagne inévitablement d’une complexification des architectures et des empilements de matériaux utilisés. Au début de cette thèse, une des voies envisagées pour poursuivre la miniaturisation était de remplacer, dans une architecture finFET, le canal en silicium par un semi-conducteur à plus forte mobilité électronique, tel que l’In0,53Ga0,47As pour les transistors nMOS. Une étape essentielle à maitriser dans la fabrication des transistors finFET à base d’InGaAs est celle de la gravure plasma qui permet d’élaborer l’architecture du canal. En effet, pour assurer un fonctionnement optimal du transitor, il est primordial que les procédés de gravure ne génèrent pas de défauts sur les flancs du canal tels que la création de rugosité ou une perte de stœchiométrie. L’objectif principal de cette thèse est ainsi de réaliser la structuration du canal 3D d’InGaAs par gravure plasma en générant un minimum de défaut sur les flancs. Pour cela, nous avons évalué trois stratégies de gravure. Des premières études ont visé le développement de procédés de gravure en plasmas halogénés à température ambiante (55°C). De tels procédés conduisent à des profils pentus et rugueux du fait de redépôts InClx peu volatils sur les flancs des motifs. Dans un second temps, des procédés de gravure en plasma Cl2/CH4 à haute température (200°C) ont été étudiés et développés. Des motifs anisotropes et moins rugueux ont pu être obtenus, grâce à la volatilité des produits InClx et à la présence d’une passivation des flancs de type SiOx. Enfin, un concept de gravure par couche atomique, qui consiste à alterner deux étapes de procédé au caractère autolimité, a été étudié. Une première étape d’implantation en plasma He/O2 qui permet une modification de l’InGaAs sur une épaisseur définie suivie d’une étape de retrait humide en HF. Pour ces trois stratégies de gravure, une méthodologie permettant de caractériser de manière systématique les défauts engendrés sur les flancs a été mise en place. La spectroscopie Auger a permis d’accéder à la stœchiométrie des flancs tandis que la rugosité a été mesurée par AFM. Les résultats issus de la caractérisation des flancs des motifs gravés ont alors montré la nécessité de mettre en œuvre des procédés de restauration de surface. Un procédé combinant une étape d’oxydation par plasma de la surface d’InGaAs suivi d’un retrait par voie humide de la couche oxydée a ainsi été proposé. Ce traitement permet effectivement de diminuer la rugosité des flancs des motifs mais a accentué un enrichissement en arsenic déjà présent après les procédés de gravure. / Increasing the performance of transistors for the next decade still relies on transistor downscaling which is inevitably accompanied by an increasing complexity of the architectures and materials involved. At the beginning of this thesis, one strategy to pursue the downscaling was to replace, in a finFET architecture, the silicon channel with high-mobility semiconductor, such as In0,53Ga0,47As for the nMOS transistors. The patterning of the channel architecture by plasma etching is an essential step to overcome in the fabrication of InGaAs-based finFET transistors. Indeed, to ensure optimal performances of the device, it is crucial that the plasma etching process do not generate defects on the channel sidewalls such as a loss of stoichiometry and roughness formation. Thus, the major aim of this thesis is to pattern the 3D InGaAs channel by plasma etching with minimal sidewalls damage. For this, we investigated three plasma etching strategies. First, this work focused on the development of plasma etches process with halogen chemistries at ambient temperature (60°C). Such process leads to sloped and rough patterns due to the redeposit of low volatile InClx etch by products. Secondly, Cl2/CH4 plasma etching processes at high temperature (200°C) have been studied and developed. Anisotropic and relatively smooth patterns can be obtained using such plasma process thanks to enhanced volatility of InClx products and a SiOx sidewall passivation formation. Finally, an atomic layer etching concept has been investigated to pattern InGaAs with minimal damage. This concept consists in alternating two self-limited steps: first, an implantation step using He/O2 plasma modifies the InGaAs surface to a limited thickness. Then, the modified layer is removed by HF wet. For all these etching strategies, a methodology was implemented to perform a systematic characterization of the damage generated on the sidewalls. The Auger spectroscopy was used to determine the sidewall stoichiometry while the sidewall roughness is measured by AFM. The results from the sidewall characterizations revealed the necessity to implement a surface restoration process. It consists in oxidizing the InGaAs sidewalls with O2 plasma and to removed the oxidized layer with a HF step. This process was efficient to smooth the InGaAs pattern sidewalls but enhances an arsenic enrichment which was already present after the etching processes.