The steady and aggressive downscaling of the physical dimensions of the conventional metal-oxide-semiconductor field-effect-transistor (MOSFET) has been the main driving force for the IC industry and information technology over the past decades. As the device dimensions approach the fundamental limits, novel double/trigate device architecture such as FinFET is needed to guarantee the ultimate downscaling. Furthermore, Schottky barrier source/drain technology presents a promising solution to reducing the parasitic source/drain resistance in the FinFET. The ultimate goal of this thesis is to integrate Schottky barrier source/drain in FinFETs, with an emphasis on process development and integration towards competitive devices. First, a robust sidewall transfer lithography (STL) technology is developed for mass fabrication of Si-nanowires in a controllable manner. A scalable self-aligned silicide (SALICIDE) process for Pt-silicides is also developed. Directly accessible and uniform NWs of Ni- and Pt-silicides are routinely fabricated by combining STL and SALICIDE. The silicide NWs are characterized by resistivity values comparable to those of their thin–film counterparts. Second, a systematic experimental study is performed for dopant segregation (DS) at the PtSi/Si and NiSi/Si interfaces in order to modulate the effective SBHs needed for competitive FinFETs. Two complementary schemes SIDS (silicidation induced dopant segregation) and SADS (silicide as diffusion source) are compared, and both yield substantial SBH modifications for both polarities of Schottky diodes (i.e. φbn and φbp). Third, Schottky barrier source/drain MOSFETs are fabricated in UTB-SOI. With PtSi that is usually used as the Schottky barrier source/drain for p-channel SB-MOSFETs, DS with appropriate dopants leads to excellent performance for both types of SBMOSFETs. However, a large variation in position of the PtSi/Si interface with reference to the gate edge (i.e., underlap) along the gate width is evidenced by TEM. Finally, integration of PtSi NWs in FinFETs is carried out by combining the STL technology, the Pt-SALICIDE process and the DS technology, all developed during the course of this thesis work. The performance of the p-channel FinFETs is improved by DS with B, confirming the SB-FinFET concept despite device performance fluctuations mostly likely due to the presence of the PtSi-to-gate underlap. / QC 20100923

Une des principales solutions technologiques liées à la réduction d'échelle de la technologie CMOS est aujourd'hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les " design tools " permettant alors d'étudier et d'élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l'élaboration d'un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s'appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction.

Les propriétés électriques et physiques de structures à faible dimensionalité ont été étudiées pour des applications dans des domaines divers comme l'électronique, les capteurs. La mesure du bruit bruit à basse fréquence est un outil très utile pour obtenir des informations relatives à la dynamique des porteurs, au piègeage des charges ou aux mécanismes de collision. Dans cette thèse, le transport électronique et le bruit basse fréquence mesurés dans des structures à faible dimensionnalité comme les dispositifs multi-grilles (FinFET, JLT...), les nanofils 3D en Si/SiGe, les nanotubes de carbone ou à base de graphène sont présentés. Pour les approches " top-down " et " bottom-up ", l'impact du bruit est analysé en fonction de la dimensionalité, du type de conduction (volume vs surface), de la contrainte mécanique et de la présence de jonction metal-semiconducteur.

As scaling of CMOS technology continues, the control of parasitic source/drain (S/D) resistance (RSD) is becoming increasingly challenging. In order to control RSD, metallic source/drain MOSFETs have attracted significant attention, due to their low resistivity, abrupt junction and low temperature processing (≤700 °C). A key issue is reducing the contact resistance between metal and channel, since small Schottky barrier height (SBH) is needed to outperform doped S/D devices. A promising method to decrease the effective barrier height is dopant segregation (DS). In this work several relevant aspects of Schottky barrier (SB) contacts are investigated, both by simulation and experiment, with the goal of improving performance and understanding of SB-MOSFET technology:First, measurements of low contact resistivity are challenging, since systematic error correction is needed for extraction. In this thesis, a method is presented to determine the accuracy of extracted contact resistivity due to propagation of random measurement error.Second, using Schottky diodes, the effect of dopant segregation of beryllium (Be), bismuth (Bi), and tellurium (Te) on the SBH of NiSi is demonstrated. Further study of Be is used to analyze the mechanism of Schottky barrier lowering.Third, in order to fabricate short gate length MOSFETs, the sidewall transfer lithography process was optimized for achieving low sidewall roughness lines down to 15 nm. Ultra-thin-body (UTB) and tri-gate SB-MOSFET using PtSi S/D and As DS were demonstrated. A simulation study was conducted showing DS can be modeled by a combination of barrier lowering and doped Si extension.Finally, a new Schottky contact model was implemented in a multi-subband Monte Carlo simulator for the first time, and was used to compare doped-S/D to SB-S/D for a 17 nm gate length double gate MOSFET. The results show that a barrier of ≤ 0.15 eV is needed to comply with the specifications given by the International Technology Roadmap for Semiconductors (ITRS). / QC 20111206

Modern cities are undergoing rapid expansion. The number of connected devices in the networks in and around these cities is increasing every day and will exponentially increase in the next few years. At home, the number of connected devices is also increasing with the introduction of home automation appliances and applications. Many of these appliances are becoming smart devices which can track our daily routines. It is imperative that all these devices should be secure. When cryptographic keys used for encryption and decryption are stored on memory present on these devices, they can be retrieved by attackers or adversaries to gain control of the system. For this purpose, Physical Unclonable Functions (PUFs) were proposed to generate the keys required for encryption and decryption of the data or the communication channel, as required by the application. PUF modules take advantage of the manufacturing variations that are introduced in the Integrated Circuits (ICs) during the fabrication process. These are used to generate the cryptographic keys which reduces the use of a separate memory module to store the encryption and decryption keys. A PUF module can also be recon gurable such that the number of input output pairs or Challenge Response Pairs (CRPs) generated can be increased exponentially. This dissertation proposes three designs of PUFs, two of which are recon gurable to increase the robustness of the system.

No description available.

Cette thèse est consacrée à la caractérisation et la modélisation du transport électronique dans des matériaux et dispositifs SOI avancés pour la microélectronique. Tous les matériaux innovants étudiés(ex: SOI fortement dopé, plaques obtenues par collage etc.) et les dispositifs SOI sont des solutions possibles aux défis technologiques liés à la réduction de taille et à l'intégration. Dans ce contexte,l'extraction des paramètres électriques clés, comme la mobilité, la tension de seuil et les courants de fuite est importante. Tout d'abord, la caractérisation classique pseudo-MOSFET a été étendue aux plaques SOI fortement dopées et un modèle adapté pour l'extraction de paramètres a été proposé. Nous avons également développé une méthode électrique pour estimer la qualité de l'interface de collage pour des plaquettes métalliques. Nous avons montré l'effet bipolaire parasite dans des MOSFET SOI totalement désertés. Il est induit par l’effet tunnel bande-à-bande et peut être entièrement supprimé par une polarisation arrière. Sur cette base, une nouvelle méthode a été développée pour extraire le gain bipolaire. Enfin, nous avons étudié l'effet de couplage dans le FinFET SOI double grille, en mode d’inversion. Un modèle analytique a été proposé et a été ensuite adapté aux FinFETs sans jonction(junctionless). Nous avons mis au point un modèle compact pour le profil des porteurs et des techniques d’extraction de paramètres. / This thesis is dedicated to the electrical characterization and transport modeling in advanced SOImaterials and devices for ultimate micro-nano-electronics. SOI technology is an efficient solution tothe technical challenges facing further downscaling and integration. Our goal was to developappropriate characterization methods and determine the key parameters. Firstly, the conventionalpseudo-MOSFET characterization was extended to heavily-doped SOI wafers and an adapted modelfor parameters extraction was proposed. We developed a nondestructive electrical method to estimatethe quality of bonding interface in metal-bonded wafers for 3D integration. In ultra-thin fully-depletedSOI MOSFETs, we evidenced the parasitic bipolar effect induced by band-to-band tunneling, andproposed new methods to extract the bipolar gain. We investigated multiple-gate transistors byfocusing on the coupling effect in inversion-mode vertical double-gate SOI FinFETs. An analyticalmodel was proposed and subsequently adapted to the full depletion region of junctionless SOI FinFETs.We also proposed a compact model of carrier profile and adequate parameter extraction techniques forjunctionless nanowires.

The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the breakdown of the transistor caused by short channel effects. Alternative solution to this is the FinFET transistor technology where the gate of the transistor is a 3D fin which surrounds the transistor and prevents the breakdown caused by scaling and short channel effects. FinFET devices are reported to have excellent control over short channel effects, high On/Off Ratio, extremely low gate leakage current and relative immunization over gate edge line roughness. Sub 20 nm is perceived to the limit of scaling the CMOS transistors but FinFETs can be scaled down further due the above-mentioned reasons. Due to these advantages the VLSI industry have now shifted to FinFET in their designs. Although these transistors have not been completely opened to academia. Analyzing and observing the effects of these devices can be pivotal in gaining an in depth understanding of them. This thesis explores the application of FinFETs using a standard cell library developed using these transistors and are analyzed and compared with CMOS transistors. The FinFET package files used to develop these cell is a 15nm FinFET technology file developed by NCSU in collaboration with Cadence and Mentor Graphics. Post design the cells were characterized and then the results were compared to through various CMOS packages to understand and extrapolate conclusions on the FinFET devices.

Afin d'optimiser les performances des circuits intégrés, l’industrie de la micro et nanotechnologie mène d'intenses recherches sur la miniaturisation à l'échelle sub-22nm de leurs principaux constituants que sont les transistors MOS. La réduction de la taille de grille atteint néanmoins des limites qui rendent problématique le contrôle du canal. L'une des approches les plus prometteuses pour contourner ce dilemme et ainsi poursuivre la miniaturisation des futurs nœuds technologiques, consiste au développement des transistors d’architectures 3D (Trigate ou FinFET). La mise au point de telles structures requiert une caractérisation de plus en plus fine, surtout à une étape clé de leur élaboration, qui est celle du dopage par implantation ionique. Du fait des faibles profondeurs implantées, l'analyse par diffusion d'ions de moyenne énergie (MEIS) est tout à fait adaptée pour quantifier les implants et évaluer la conformité du dopage grâce à sa bonne résolution en profondeur (0.25 nm). Néanmoins, les dimensions de la sonde (0.5 × 1 mm2) étant très supérieures à celles des motifs, il nous a fallu développer un protocole d’analyse propre à de telles architectures. Les échantillons étudiés dans le cadre de cette thèse sont des systèmes modèles. Ils sont constitués de réseaux de lignes de silicium (Si) 3D, formées par gravure lithographique par faisceaux d’électrons (e-beam) sur des plaques 300 mm de types silicium sur isolant (SOI). Le dopage a été réalisé à une énergie de 3 keV par implantions conventionnelle (ou beam line) et immersion plasma (PIII).L’analyse des spectres MEIS des implants insérés dans chaque facette des motifs a été possible grâce aux simulations 3D types Monte-Carlo effectuées avec le logiciel PowerMEIS. Nous avons ainsi développé une nouvelle méthode adaptée à la caractérisation du dopage 3D. Les mesures ont montré que, contrairement à la méthode PIII, la dose implantée par la méthode conventionnelle correspond à celle visée. Cependant la distribution des dopants introduits au sein des nanostructures par les deux méthodes de dopage n’est pas uniforme. Dans les échantillons implantés par PIII, on a observé une importante concentration des dopants aux sommets des motifs et un faible dopage des flancs. Ceci étant moins marqué dans celui implanté par la méthode conventionnelle. En corrélant les techniques de Microscopie Electronique en Transmission (MET), d’analyses par rayons x synchrotron et MEIS, nous avons également pu déterminer les dimensions des zones implantées ainsi que celles des zones cristallines dans les réseaux de lignes gravées.L'exploitation de la technique MEIS en mode canalisation a permis une évaluation complète des couches non gravées. L’investigation des endommagements post – dopage dans les régions cristallines non implantées ont été menées toujours avec la même technique MEIS. Les résultats ont révélé une importante influence de la méthode d’implantation et la température sur les défauts et les déformations dans le cristal. L’origine des anomalies au sein des échantillons a ainsi été identifiée en corrélant les mesures MEIS et celles par spectrométrie de masse des ions secondaires en temps de vol (ToF-SIMS). / With the aim of optimizing the performances of integrated circuits (ICs), the nanotechnology industry is carrying out intense research activities on the miniaturization at the sub-22 nm scale of their main constituents: the MOS transistors. Nevertheless, the shrinking of the gate size has reached the limits that make the control of the channel problematic. One of the most promising approaches to circumvent this dilemma and thus further the miniaturization of the future technological nodes, is the development of transistors of 3D architecture (Trigate or FinFET). The elaboration of such nanostructures requires increasingly fine characterization tools precisely at a key stage of their fabrication, namely the ion implantation doping. Given the ultra-shallow implantation depths, the medium energy ion scattering (MEIS) analysis technique is suitable for quantifying the implants and evaluating the doping conformity thanks to its good depth resolution (0.25 nm). However, the dimensions of the beam (0.5×1 mm2) being by far larger than those of the patterns, we had to develop an analysis protocol dedicated to such architectures. The samples studied in the framework of this thesis are considered as model systems. They are constituted of 3D silicon (Si) Fin – shaped line gratings, etched on the 300 mm wafers of silicon on insulator (SOI) types by using the electron beam (e-beam) lithography. The doping has been carried out at an energy of 3 keV by using the conventional (or beam line) and plasma immersion ion implantation (PIII) methods.The analyses s of the MEIS spectra of the dopants implanted into each part of the patterns were possible thanks to the 3D Monte-Carlo simulations performed with the PowerMEIS software. We have thus developed a new method suitable for the characterization of the 3D doping. The measurements have shown that, contrarily to the PIII method, the dose implanted by the conventional method is as targeted. However, the distribution of the dopants inserted within the nanostructures by using the two doping methods is not uniform. In the PIII implanted samples, a large dopants' focusing at the tops of the patterns and low sidewalls' doping have been observed. This is less marked in the one implanted by the conventional method. By correlating the Transmission Electron Microscopy (TEM), synchrotron x – ray analyses and MEIS, we have also determined the dimensions of the implanted and crystal areas of the line gratings.The exploitation of the MEIS technique in channeling mode has permitted the full assessment of the impacts of the implantation in the non-etched layers. The investigations of the crystal qualities in the non-implanted areas were carried out with the same technique. The results show that the temperature conditions have a considerable influence on the defects and lattice deformations. The origin of the anomalies in the samples has thus been identified by correlating the MEIS and Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) measurements.

The processors and digital circuits designed today contain billions of transistors on a small piece of silicon. As devices are becoming smaller, slimmer, faster, and more efficient, the transistors also have to keep up with the demands and needs of the daily user. Unfortunately, the CMOS technology has reached its limit and cannot be used to scale down due to the transistor's breakdown caused by short channel effects. An alternative solution to this is the FinFET transistor technology, where the gate of the transistor is a three dimensional fin that surrounds the transistor and prevents the breakdown caused by scaling and short channel effects. FinFET devices are reported to have excellent control over short channel effects, high On/Off Ratio, extremely low gate leakage current and relative immunization over gate edge line roughness. Sub 20 nm node size is perceived to be the limit of scaling the CMOS transistors, but FinFETs can be scaled down further because of its unique design. Due to these advantages, the VLSI industry has now shifted to FinFET in implementation of their designs. However, these transistors have not been completely opened to academia. Analyzing and observing the effects of these devices can be pivotal in gaining an in-depth understanding of them. This thesis explores the implementation of FinFETs using a standard cell library designed using these transistors. The FinFET package file used to design these cells is a 15nm FinFET technology file developed by NCSU in collaboration with Cadence and Mentor Graphics. Post design, the cells were characterized, the results were analyzed and compared with cells designed using CMOS transistors at different node sizes to understand and extrapolate conclusions on FinFET devices.