Zugl.: Berlin, Humboldt-Univ., Diss., 2007

Thesis (doctoral)--Humboldt-Universität zu Berlin, 2007. / Includes bibliographical references (p. [187]-195).

Intermediate lipid structures such as inverted micelles and interlamellar attachment are thought to play a crucial role in different biological processes like viral infection. Lysophosphatidylcholine has been shown to inhibit membrane fusion at stabilizing concentrations (between 1 and 10% with respect to membrane lipids). Studies in this thesis looked at the effects of Lysophosphatidylcholine (LPC) properties on the inhibition of Sendai viral fusion. The effects of bilayer sidedness preference as well as flip-flop of Lysophosphatidylcholine (lyso PC) were examined. Octadecylrhodamine (R₁₈) lipid mixing assays were used to measure the fusion of Sendai virus with different biological, erythrocyte ghosts, and artificial systems consisting of different lipids and different viral receptor compositions. The data showed that external addition of LPC exhibits a dependency between the incubation time of the lysolipids and the inhibition of viral fusion. The results also demonstrate a relationship between the location of LPC in the bilayer and its ability to inhibit lipid mixing. LPC present only on the outer monolayer plays a role in the inhibition of viral fusion. Reorientation of LPC was also measured for the same incubation periods. A method using Bovine Serum Albumin (BSA) and radioactivity labelled LPC, was applied to measure the flip-flop. Significant transbilayer reorientation of Lyso PC in the bilayer was shown to take place. The rate of flip-flop was measured at 0.32 ± 0.08% LPC /min. Such reorientation can explain the time dependency observed earlier. The conclusions of this thesis lend support to stalk intermediate mechanism of viral membrane fusion. The ability of LPC to inhibit only when present on one side of the bilayer supports the idea of a negatively curved stalk intermediate. Moreover, it showed that the shape and curvature tendencies of the bilayer stabilizer determine its effects on viral fusion. / Thesis / Master of Science (MS)

One central question of neuroscience asks how a neural system can generate the diversity of complex behaviors needed to meet the range of possible demands placed on an organism by an ever changing environment. In many cases, it appears that animals assemble complex behaviors by recombining sets of simpler behaviors known as behavioral primitives. The crawling behavior of the nematode worm Caenorhabditis elegans represents a classic example of such an approach since worms use the simple behaviors of forward and reverse locomotion to assemble more complex behaviors such as search and escape. The relative simplicity and well-described anatomy of the worm nervous system combined with a high degree of genetic tractability make C. elegans an attractive organism with which to study the neural circuits responsible for assembling behavioral primitives into complex behaviors. Unfortunately, difficulty probing the physiological properties of central synapses in C. elegans has left this opportunity largely unfulfilled. In this dissertation we address this challenge by developing techniques that combine whole-cell patch clamp recordings with optical stimulation of neurons. We do this using transgenic worms that express the light-sensitive ion channel Channelrhodopsin-2 (ChR2) in putative pre-synaptic neurons and fluorescent protein reporters in the post-synaptic neurons to be targeted by electrodes. We first apply this new approach to probe C. elegans circuitry in chapter II where we test for connectivity between nociceptive neurons known as ASH required for sensing aversive stimuli, and premotor neurons required for generating backward locomotion, known as AVA. In chapter III we extend our analysis of the C. elegans locomotory circuit to the premotor neurons required for generating forward locomotion, known as AVB. We identify inhibitory synaptic connectivity between ASH and AVB and between the two types of premotor neurons, AVA and AVB. Finally, we use our observations to develop a biophysical model of the locomotory circuit in which switching emerges from the attractor dynamics of the network. Primitive selection in C. elegans may thus represent an accessible system to test kinetic theories of decision making. This dissertation includes previously published co-authored material.

Some techniques are presented to permit the implementation of asynchronous sequential circuits using standard flip-flops. An algorithm is presented for the RS flip-flop, and it is shown that any flow table may be realized using the algorithm (the flow table is assumed to be realizable using standard logic gates). The approach is shown to be directly applicable to synchronous circuits, and transition flip-flops (JK, D, and T) are analyzed using the ideas developed. Constraints are derived for the flow tables to meet to be realizable using transition flip-flops in asynchronous situations, and upper and lower bounds on the number of transition flip-flops required to implement a given flow table are stated.

The Successive Approximation Register (SAR) Analog to Digital Converter (ADC) is power efficient and operates at moderate resolution. However, the conversion speed is limited by settling time and control logic constraints. This report investigates a flip-flop bypass technique to reduce the required conversion time. A conventional design and flip-flop bypass design are simulated using a 0.18[micrometer] CMOS process. Background and design of the control logic, comparator, capacitive array, and switches for implementing the SAR ADCs is presented with the emphasis on optimizing for conversion speed. / text

Zugl.: Karlsruhe, Univ., Diss., 2007 / Hergestellt on demand

abstract: Radiation hardening by design (RHBD) has become a necessary practice when creating circuits to operate within radiated environments. While employing RHBD techniques has tradeoffs between size, speed and power, novel designs help to minimize these penalties. Space radiation is the primary source of radiation errors in circuits and two types of single event effects, single event upsets (SEU), and single event transients (SET) are increasingly becoming a concern. While numerous methods currently exist to nullify SEUs and SETs, special consideration to the techniques of temporal hardening and interlocking are explored in this thesis. Temporal hardening mitigates both SETs and SEUs by spacing critical nodes through the use of delay elements, thus allowing collected charge to be removed. Interlocking creates redundant nodes to rectify charge collection on one single node. This thesis presents an innovative, temporally hardened D flip-flop (TFF). The TFF physical design is laid out in the 130 nm TSMC process in the form of an interleaved multi-bit cell and the circuitry necessary for the flip-flop to be hardened against SETs and SEUs is analyzed with simulations verifying these claims. Comparisons are made to an unhardened D flip-flop through speed, size, and power consumption depicting how the RHBD technique used increases all three over an unhardened flip-flop. Finally, the blocks from both the hardened and the unhardened flip-flops being placed in Synthesis and auto-place and route (APR) design flows are compared through size and speed to show the effects of using the high density multi-bit layout. Finally, the TFF presented in this thesis is compared to two other flip-flops, the majority voter temporal/DICE flip-flop (MTDFF) and the C-element temporal/DICE flip-flop (CTDFF). These circuits are built on the same 130 nm TSMC process as the TFF and then analyzed by the same methods through speed, size, and power consumption and compared to the TFF and unhardened flip-flops. Simulations are completed on the MTDFF and CTDFF to show their strengths against D node SETs and SEUs as well as their weakness against CLK node SETs. Results show that the TFF is faster and harder than both the MTDFF and CTDFF. / Dissertation/Thesis / M.S. Electrical Engineering 2010

abstract: ABSTRACT The D flip flop acts as a sequencing element while designing any pipelined system. Radiation Hardening by Design (RHBD) allows hardened circuits to be fabricated on commercially available CMOS manufacturing process. Recently, single event transients (SET's) have become as important as single event upset (SEU) in radiation hardened high speed digital designs. A novel temporal pulse based RHBD flip-flop design is presented. Temporally delayed pulses produced by a radiation hardened pulse generator design samples the data in three redundant pulse latches. The proposed RHBD flip-flop has been statistically designed and fabricated on 90 nm TSMC LP process. Detailed simulations of the flip-flop operation in both normal and radiation environments are presented. Spatial separation of critical nodes for the physical design of the flip-flop is carried out for mitigating multi-node charge collection upsets. The proposed flip-flop is also used in commercial CAD flows for high performance chip designs. The proposed flip-flop is used in the design and auto-place-route (APR) of an advanced encryption system and the metrics analyzed. / Dissertation/Thesis / M.S. Electrical Engineering 2014

L’augmentation de la densité et la réduction de la tension d’alimentation des circuits intégrés rend la contribution des effets singuliers induits par les radiations majoritaire dans la diminution de la fiabilité des composants électroniques aussi bien dans l’environnement radiatif spatial que terrestre. Cette étude porte sur la modélisation des mécanismes physiques qui conduisent à ces aléas logiques (en anglais "Soft Errors"). Ces modèles sont utilisés dans une plateforme de simulation,appelée TIARA (Tool suIte for rAdiation Reliability Assessment), qui a été développée dans le cadre de cette thèse. Cet outil est capable de prédire la sensibilité de nombreuses architectures de circuits (SRAM,Flip-Flop, etc.) dans différents environnements radiatifs et sous différentes conditions de test (alimentation, altitude, etc.) Cette plateforme a été amplement validée grâce à la comparaison avec des mesures expérimentales effectuées sur différents circuits de test fabriqués par STMicroelectronics. La plateforme TIARA a ensuite été utilisée pour la conception de circuits durcis aux radiations et a permis de participer à la compréhension des mécanismes des aléas logiques jusqu’au noeud technologique 20nm. / Aggressive integrated circuit density increase and power supply scaling have propelled Single Event Effects to the forefront of reliability concerns in ground-based and space-bound electronic systems. This study focuses on modeling of Single Event physical phenomena. To enable performing reliability assessment, a complete simulation platform named Tool suIte for rAdiation Reliability Assessment (TIARA) has been developed that allows performing sensitivity prediction of different digital circuits (SRAM, Flip-Flops, etc.) in different radiation environments and at different operating conditions (power supply voltage,altitude, etc.) TIARA has been extensively validated with experimental data for space and terrestrial radiation environments using different test vehicles manufactured by STMicroelectronics. Finally, the platform has been used during rad-hard digital circuits design and to provide insights into radiation-induced upset mechanisms down to CMOS 20nm technological node.