I Sverige är 99.9 % av alla företag SME-företag. I dagens samhälle har förändrade förutsättningar och globala marknader ändrat kundkraven på exempelvis ledtid. Svenska tillverkande SME-företag kräver således ett sätt att anpassa sin produktion till dessa förändrade förutsättningar. VSM är en metod där current- och future-state mappas för att tydliggöra hur produktionen ser ut idag och hur det ska se ut imorgon. Det påvisas dock i tidigare studier att det finns hinder med VSM som motverkar framtagning av FSM. Det ska dock noteras att merparten av de studier som tidigare utförts har gjorts vid utländska företag eller företag större än SME. Dessa studier har dessutom genomförts i syfte att observera VSM i helhet och de fördelar som metoden har, eller undersöka vissa få hinder. Syftet med arbetet är därför att undersöka vilka hinder som kan försvåra för svenska SME-företag att designa future-state värdeflödeskartor som är lämpliga sett till deras verksamhet. Detta för att bättre möjliggöra för VSM implementation hos dessa företag. Detta har utförts genom att jämföra tidigare litteratur med en fallstudie på ett svenskttillverkande SME-företag inom metallindustrin och undersöka de mönster i hindren som observerats. Resultatet av arbetet var en modell av hinder som kan komma att försvåra försvenska SME-företag att designa future-state värdeflödeskartor som är lämpliga sett till deras verksamhet. Från denna modell tydliggörs ett stor överlapp mellan det empiriska resultatet och resultatet från tidigare studier. Ett hinder från tidigare litteratur motbevisas även och exkluderas från modellen. Detta medför att framtida utövare på svenska tillverkande SME-företag aktivt kan göra sig medvetna om de hinder som de kan tänkas stöta på samt vad dessa kan ha för påverkan på deras FSM, och genom detta förbereda sig för att möta dessa hinder. Framtida studier skulle kunna undersöka hinder vid användning av VSM-metoden på flera olika svenska tillverkande SME-företag och således skapa en bredare bild av hinder med VSM för framställning av en FSM / In Sweden, 99.9% of all companies are SMEs. In today's society, changing conditions and global markets have altered customer requirements, such as lead time. Therefore, Swedish manufacturing SMEs require a way to adapt their production to these changing conditions. Value Stream Mapping (VSM) is one such method that maps the current and future states to clarify how production looks today and how it should look tomorrow. However, previous studies have shown that there are obstacles with VSM that hinder the development of Future State Maps (FSMs). It should be noted that the majority of previous studies have been conducted in foreign or larger-than-SME companies. These studies have also been carried out to observe the entirety of VSM and its benefits or to investigate a few specific obstacles. The purpose of this study is to examine the obstacles that may hinder Swedish SMEs from designing future-state value stream maps suitable for their operations, in order to better enable VSM implementation in these companies. This has been accomplished by comparing previous literature with a case study conducted at a Swedish manufacturing SME in the metal industry and examining the patterns observed in the obstacles. The result of this work was a model of obstacles that may hinder Swedish SMEs from designing future-state value stream maps suitable for their operations. This table clearly shows a significant overlap between the empirical findings and the results from previous studies. Additionally, one obstacle from previous literature is contradicted. As a result, future practitioners in Swedish manufacturing SMEs can actively become aware ofthe obstacles they may encounter and understand their impact on their FSMs, thereby preparing to address these obstacles. Future studies could investigate obstacles in the use of the VSM method in several different Swedish manufacturing SMEs to create a broader understanding of obstacles with VSM for the development of an FSM.

Software size estimation/measurement has been the objective of a lot of research in the software engineering community due to the need of reliable size estimates. FSM Methods have become widely used in software project management to measure the functional size of software since its first publication, late 1970s. Although all FSM methods measure the functional size by quantifying the FURs, each method defined its own measurement process and metric. Therefore, a piece of software has several functional sizes when measured by different methods. In order to be able to compare functional sizes of software products measured by different methods, we need to convert them to each other. In this thesis study, the similarities and differences between four FSM methods, IFPUG FPA, Mark II FPA, COSMIC FFP and ARCHI DIM FSM are investigated and the common core concepts are presented. Accordingly a unification model of the measurement process of all four methods is proposed. The main objective of this model is to measure the functional size of a software system by applying all four methods simultaneously, using a single source of data. In order to have an infrastructure to validate the unification model by conducting empirical studies, a software tool is designed and implemented based on the unification model. Two empirical studies are conducted by utilizing the data of a real project to evaluate both the unification model proposed and the developed tool and the measurement results are discussed.

Context: Software cost and effort estimation are important activities for planning and estimation of software projects. One major player for cost and effort estimation is functional size of software which can be measured in variety of methods. Having several methods for measuring one entity, converting outputs of these methods becomes important. Objectives: In this study we investigate different techniques that have been proposed for conversion between different Functional Size Measurement (FSM) techniques. We addressed conceptual similarities and differences between methods, empirical approaches proposed for conversion, evaluation of the proposed approaches and improvement opportunities that are available for current approaches. Finally, we proposed a new conversion model based on accumulated data. Methods: We conducted a systematic literature review for investigating the similarities and differences between FSM methods and proposed approaches for conversion. We also identified some improvement opportunities for the current conversion approaches. Sources for articles were IEEE Xplore, Engineering Village, Science Direct, ISI, and Scopus. We also performed snowball sampling to decrease chance of missing any relevant papers. We also evaluated the existing models for conversion after merging the data from publicly available datasets. By bringing suggestions for improvement, we developed a new model and then validated it. Results: Conceptual similarities and differences between methods are presented along with all methods and models that exist for conversion between different FSM methods. We also came with three major contributions for existing empirical methods; for one existing method (piecewise linear regression) we used a systematic and rigorous way of finding discontinuity point. We also evaluated several existing models to test their reliability based on a merged dataset, and finally we accumulated all data from literature in order to find the nature of relation between IFPUG and COSMIC using LOESS regression technique. Conclusions: We concluded that many concepts used by different FSM methods are common which enable conversion. In addition statistical results show that the proposed approach to enhance piecewise linear regression model slightly increases model’s test results. Even this small improvement can affect projects’ cost largely. Results of evaluation of models show that it is not possible to say which method can predict unseen data better than others and it depends on the concerns of practitioner that which model should be used. And finally accumulated data confirms that empirical relation between IFPUG and COSMIC is not linear and can be presented by two separate lines better than other models. Also we noted that unlike COSMIC manual’s claim that discontinuity point should be around 200 FP, in merged dataset discontinuity point is around 300 to 400. Finally we proposed a new conversion approach using systematic approach and piecewise linear regression. By testing on new data, this model shows improvement in MMRE and Pred(25). / Javad Amiri: Nabshe Kooche 3, Bolvare shadi, Farhangian 2, Qom, Iran, phone: +989127476593 Vinod Kumar: s/o P.V.Kondala Rao, Main Road Khaji Street Rajahmundry. A.P. India pin: 533101 phone: +917396449336

This thesis work investigates how to represent protocols for asynchronous communication in the Scala programming language and the Akka actor framework, to be run on Java Virtual Machine (JVM). Further restrictions from the problem domain - the coexistence of multiple protocol instances sharing the same Java thread - imply that neither an asynchronous call waiting for response nor anything else can block the underlying Java threads. A common way to represent asynchronous communication protocols is to use state machines. This thesis seeks a way to shrink the size of and to reduce the complexity of the protocol implementations by representing sequences of asynchronous communication calls (i.e. sequences of sent and received messages) as a type of procedure. The idea is find a way to make the procedures that contain asynchronous calls look like synchronous communication procedures by hiding the asynchronous details. In other words, the resulting procedure code should show what to do and not so much focus on how to overcome the impediment of the asynchronous calls. With the help of an asynchronous communication protocol toy example, this report shows how such an protocol can be implemented with a combination of a state machine and a procedure representation in Scala and Akka. The procedure representation hides away the asynchronous details by using the Scala capability to use CPS-transformed delimited continuations. As a sub-problem, this thesis also shows how to safely schedule asynchronous communication timeouts with help of Scala and Akka within the restrictions of the thesis problem domain.

No description available.

Wireless sensor networks (WSN) play an important role in today’s monitoring and controlsystems like environmental monitoring, military surveillance, industrial sensing and control, smarthome systems and tracking systems. As the application of WSN grows by leaps and bounds, there is anincreasing demand in placing a larger number of sensors and controllers to meet the requirements. Theincreased number of sensors necessitates flexibility in the functioning of nodes. Nodes in wirelesssensor networks should be capable of being dynamically reconfigured to perform various tasks is theneed of the hour.In order to achieve flexibility in node functionality, it is common to adopt reconfigurablearchitecture for WSN nodes. FPGA-based architectures are popular reconfigurable architectures bywhich WSN nodes can be programmed to take up different roles across time. Area and power are themajor overheads in FPGA based architectures, where interconnect consumes more power and area thanlogic cells. The contemporary WSN standard requires longer battery life and micro size nodes for easyplacement and maintenance-free operation for years together.Three solutions have been studied and evaluated to approach this problem: 1) Homogenousembedded FPGA platform, 2) Power gated reconfigurable finite state machines and 3) Pass transistorlogic (PTL) based reconfigurable finite state machines. Embedded FPGA is a CMOS 65nm customdeveloped small homogenous FPGA which holds the functionality of the WSN nodes and it will bedynamically reconfigured from time to time to change the functionality of the node. In Power gatedreconfigurable FSM architecture, the functionality of the node is expressed in the form of finite statemachines, which will be implemented in a LUT based power gated design. In PTL based reconfigurablefinite state machine architecture, the finite state machines are completely realized using PTL basedcustom designed sets of library components. Low power configuration memory is used to dynamicallyreconfigure the design with various FSMs at different times.

O teste de software engloba diferentes técnicas, métodos e conceitos capazes de garantir a qualidade dos mais variados tipos de sistemas. Dentre tais técnicas, encontra-se o teste baseado em Máquinas de Estados Finitos (MEFs), que visa a garantir a conformidade entre a implementação e a especificação de um software. Com esse propósito, diversos métodos foram propostos para a geração de seqüências de verificação que garantam cobertura total das possíveis falhas existentes em uma implementação. A maioria dos métodos conhecidos são baseados na utilização de seqüências de distinção. Esse recurso, porem, não existe para toda MEF. Alguns métodos buscam a geração de seqüências de verificação baseados em recursos alternativos as seqüências de distinção, contudo, as seqüências geradas são exponencialmente longas. Este trabalho apresenta um método para geração de seqüências de verificação que visa a reduzir o tamanho das seqüências geradas para o domínio de MEFs que não dispõem de seqüência de distinção. Para isso, o método proposto baseia-se na utilização de conjuntos de distinção. Uma avaliação experimental foi realizada afim de mensurar a redução proporcionada pelo método proposto em relação aos principais métodos existentes na literatura. Com esse intuito, foram geradas MEFs aleatórias sob a perspectiva diferentes fatores. Em relação a variação do número de estados, os resultados indicaram reduções acima de 99; 5% em comparação com os métodos existentes, quando analisadas 75% das MEFs geradas / Software testing involves several techniques, methods, and concepts employed to guarantee a high level of quality in different application domains. Among such techniques, Finite State Machine (FSM) based testing aims to guarantee the conformance between the implementation and the specification of a system under test. In this context, several methods were proposed to generate checking sequences that cover all the possible faults existing in an implementation. Most of these methods are based on a special sequence, named distinguishing sequence, which does not exist for every minimal machine. Some methods were proposed to generate checking sequences based on alternative solutions in order to be applied on FSMs that do not have distinguishing sequences. However, these methods generate checking sequences exponentially long. This work proposes a method to generate checking sequences using identification sets. These sets exist for every minimal FSM and also lead to shorter checking sequences. We conducted an experimental study to compare the proposed method with the main existing methods. In the experiments, we used random FSMs that have different configurations of states, inputs, and outputs. Concerning the variation of number of states, the results show reductions higher than 99:5% in comparison with the existing methods for 75% of the experimented machines

A realização de atividades de teste é indispensável para a garantia da qualidade de um produto e para a identificação de defeitos, diminuindo custos de manutenção e evitando ao máximo o risco do cliente encontrar esses defeitos. Nessa linha, testes baseados em modelos têm se mostrado atrativos, pois o custo de geração de casos de testes e de correção de defeitos tende a ser menor. Devido à sua simplicidade conceitual e expressividade na descrição do comportamento de um sistema, um dos modelos mais usados e pesquisados na área de teste baseado em modelos são as Máquinas de Estados Finitos (MEFs). Por meio de MEFs e com apoio de ferramentas apropriadas, a geração de casos de testes para avaliar os comportamentos esperados de um sistema é automatizada, reduzindo tanto o custo da geração e da manutenção quanto as falhas humanas. Desta forma, a aplicabilidade de métodos de geração de casos de teste baseados em modelos no contexto de sistemas embarcados vem sendo investigada. O objetivo deste trabalho de mestrado consiste em investigar a aplicabilidade dos métodos de geração em cenários de teste reais, com foco em sistemas embarcados, identificando as difi- culdades e limitações do processo, bem como os requisitos essenciais para a adequação dos métodos de geração propostos na literatura e de ferramentas de apoio à atividade de teste. O foco principal do projeto é a implementação de mecanismos que atendam aos requisitos levantados, visando a usabilidade, segurança e portabilidade da ferramenta / Test activities are essential to ensure the quality of products and identify faults to reduce maintenance costs and avoid that the client finds these faults. In this sense, model-based tests have been proved useful, because the cost of generating test cases and fault correction tend to be smaller. Due to its conceptual simplicity and expressiveness in describing the behavior of a system, Finite State Machines (FSM) have been used and researched in the model-based testing area. FSMs, employed with the support of appropriate tools, enable the generation of test cases in an automated way to assess the expected behavior of a system, reducing both the generation and maintenance costs and human failures. Thus, the applicability of test cases generation methods based on models in the context of embedded systems should be investigated. Test cases generation methods based on FSM are designed to derive test cases from the model. In this context, this work aims to investigate the applicability of generation methods in real-world scenarios, focusing embedded systems. It should identify the difficulties and limitations of the process, as well as the essential requirements for the adequacy of generation methods proposed in the literature and tools to support the test activity. The main focus of the project is the implementation of mechanisms that meet the elicited requirements in order to provide usability, security and tool portability

MÉTODOS de geração de casos de teste visam a gerar um conjunto de casos de teste com uma boa relação custo/benefício. Critérios de cobertura de teste definem requisitos de teste, os quais um conjunto de teste adequado deve cobrir. Métodos e critérios visam a selecionar casos de teste baseados em especificações, que podem ser descritas por meio de modelos, tais como Máquinas de Estados Finitos (MEF). Existem diversos métodos de geração e critérios de cobertura, diferindo entre si em função das propriedades exigidas da MEF, do custo dos testes gerados e da eficácia na revelação de defeitos. Apesar de pesquisas intensas na definição desses métodos e critérios, são poucas as ferramentas de apoio disponíveis assim como são poucos os relatos de aplicação em termos de custo e eficácia para a definição de estratégias de teste efetivas. Dessa forma, é necessário obter dados reais das vantagens e desvantagens dos métodos e critérios para subsidiar a tomada de decisão no processo de desenvolvimento de software no que tange às atividades de teste e validação. Este trabalho apresenta resultados de experimentos para avaliar o custo e a eficácia de aplicação dos métodos e critérios mais relevantes para subsidiar a definição de estratégias de teste em diversos contextos, como por exemplo, no desenvolvimento de protocolos e de sistemas reativos. Utiliza-se um protótipo desenvolvido a partir de uma reengenharia da ferramenta Plavis/FSM para apoiar os experimentos / TEST case generation methods aim to generate a test suite that offers an acceptable trade-off between cost and avail. Test coverage criteria define testing requirements, which an adequate test suite must fulfill. Methods and criteria help to select test case from specifications, which can be describe as models, for example Finite State Machines (FSM). There are several generation methods and coverage criteria that differ depending on the required properties of the FSM, the cost of generated tests and the effectiveness in revealing faults. In spite of intense researches in the definition of those methods and criteria, there are few available tools to apply them as well as application reports about cost and effectiveness issues to define effective test strategies. Thus, it is necessary to obtain real data of the advantages and disadvantages of the methods and criteria to provide decision-making in the software development process as far in the validation and test activities. This work aimed to lead experiments to evaluate the cost and the effetiveness in applying the most relevant methods and criteria to subsidize test strategies definition in several contexts as the communication protocol development and the reactive systems development. A prototype was developed based on reengineering of the Plavis/FSM tool to support the experiments

Made available in DSpace on 2014-06-11T19:22:36Z (GMT). No. of bitstreams: 0 Previous issue date: 2002-09-19Bitstream added on 2014-06-13T19:28:11Z : No. of bitstreams: 1 tancredo_lo_me_ilha.pdf: 1818873 bytes, checksum: ed384d89dcc56a20c364164f7beef4f2 (MD5) / Este trabalho apresenta uma nova ferramenta de síntese para projetos de sistemas digitais denominada TAB2VHDL. A partir da descrição em diagrama de transição de estados de uma máquina finita, representada no modelo de Mealy, é gerada uma descrição otimizada do sistema na linguagem de VHDL. Elimina-se dessa forma a tarefa árdua com detalhes de projeto. A TAB2VHDL foi comparada com duas outras ferramentas disponíveis comercialmente. Foram projetados diversos chip-set de códigos de transmissão digital utilizados no setor de telecomunicações. Os resultados comprovaram o desempenho satisfatório com relação ao custo de implementação, ao tempo de execução e uso de memória. / This paper presents a new synthesis tool for digital system projects called TAB2VHDL. From the description in states transition diagram of a finite machine, represented in Mealy's model, an optimized system description in VHDL language is generated. Therefore, it is eliminated an arduous task with project details. The TAB2VHDL was compared with two other available commercial tools. It was projected a sort of chip-set digital transmission codes, used in telecommunication sector. The results proved the satisfactory performance related to the implementation cost, to the time of execution and memory use.