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Denna rapport är ett examensarbete för högskoleingenjör, teknisk design –Produktutveckling vid Luleå Tekniska Universitet. Den omfattar 10 arbetsveckorsarbete på 15 högskolepoäng utfört mellan 2016-10-10 och 2016-12-16. Uppdragsgivaren för detta projekt är företaget Zone Systems som tillverkar bådedigitala och analoga skyltar för in- och utomhusbruk. Målet med projektet är attskapa en produktserie för drive-in. I denna produktserie skall det ingå ramar tillprofilen Infinity som uppdragsgivaren redan tagit fram och som finns i olikastorlekar. Även en half-gate skall tas fram, vilket är det första som syns vid endrive-in och talar om för föraren vilken höjd fordonet max får ha. Dennaproduktserie skall gå att anpassa efter kundens önskemål, vara lättillverkad ochmöjliggöra att skylten går att snurra på. Materialval skall göras som klarar avutomhusmiljö samt ser till att produkterna är stabila. För att åstadkomma detta har relevant teori samlats in så som material,produktutveckling, färglära och kommunikation. En projektplan har också gjortssom har följts noga under hela projektet. Därefter påbörjades idéutvecklingen som bestod av olika idégenereringsmetodersom brainstorming, idéskiftmetoden, katalogmetoden, kategorisering och enworkshop bestående av sju personer. De idéer som genererats från dessa metodersamlades sedan ihop och en gallring av dem gjordes. Fyra koncept valdes ut vidgallringen- Det var koncepten Rör-ram, H-balk, Istappen och Ljuslådan. Ett koncept vidareutvecklades och konstruktionsförslag togs fram på detta. Ävenmock-ups och datormodelleringar togs fram för att sedan resultera i slutkonceptetBright. Därefter skissades en half-gate fram med designaspekt baserad påslutkonceptet. Denna modellerades även upp i CAD-programmet Siemens NX10.0 och verklighetstrogna bilder renderades på hela produktserien i LuxionKeyshot 5. Slutresultatet på produktserien låter kunden själv välja färg för att passa derasföretag. Skylten går även att snurra på och det material som användes är bockadstålplåt för att klara av utomhusmiljön och skapa en stabil grund. Även akrylplastanvänds för tätning och ljusutsläpp. Det är en moderniserad och nytänkandelösning för en produktserie till en drive-in samt tidlös tack vare dess smakfulladesign.

Este trabalho tem como objetivo investigar o comportamento de transistores SOI de porta tripla com óxido de porta de alta constante dielétrica e eletrodo de porta de metal. Inicialmente estudou-se a aplicação dos métodos de extração de parâmetros através de curvas da capacitância, previamente desenvolvidos para estruturas SOI planares, em dispositivos de porta tripla com óxido de porta de háfnio (HfO2) e porta de metal com nitreto de titânio (TiN). Foram utilizados dispositivos com grandes dimensões, onde a influência das portas laterais pode ser desprezada, apresentando desta forma, um comportamento similar aos dispositivos com geometria planar. Simulações numéricas tridimensionais seguidas de medidas experimentais validam a utilização desses métodos em estruturas de múltiplas portas com grande largura de canal. A capacitância também foi utilizada para se analisar a influência que o efeito de canto exerce sobre estas estruturas de múltiplas portas. Na seqüência, foi investigado o impacto que a variação da espessura da porta de metal TiN causa nas características elétricas dos transistores SOI de porta tripla com óxido de porta de silicato de óxido de háfnio (HfSiO). Parâmetros como tensão de limiar, função de trabalho, mobilidade, cargas de interface assim como as características analógicas foram analisadas. Os resultados indicaram que camadas de TiN mais finas são mais atrativas, apresentando menor tensão de limiar e armadilhas de interface, assim como um aumento na mobilidade e no ganho intrínseco do transistor. Contudo uma maior corrente de fuga pelo óxido de porta é vista nestes dispositivos. Juntamente com esta análise, o comportamento de transistores de porta tripla com dielétrico de porta de silicato de óxido de háfnio nitretado (HfSiON) também foi estudado, onde observou-se um maior impacto nas cargas de interface para o óxido de háfnio nitretado. Contudo, o mesmo é capaz de reduzir a difusão de impurezas até o óxido de silício (SiO2) interfacial com o canal de silício. Finalmente transistores de porta tripla com diferentes composições de estrutura de porta foram estudados experimentalmente, onde uma camada de óxido de disprósio (Dy2O3) foi depositada entre o silicato de óxido de háfnio (HfSiO) e a porta de metal TiN. Observou-se uma redução na tensão de limiar nos dispositivos com o óxido de disprósio assim como uma variação na tensão de faixa plana. Em resumo, quando a camada de óxido de disprósio foi depositada dentro da porta de metal TiN, uma melhor interface foi obtida, assim como uma maior espessura de óxido efetivo, indicando desta forma uma menor corrente de fuga. / The main goal of this work is to investigate the behavior of SOI triple gate transistors with high dielectric constant gate oxide and metal gate material. Initially it was studied the application of process parameters extraction methods through capacitance curves, developed previously for planar SOI structures, in the triple-gate devices with hafnium gate oxide (HfO2) and metal gate of titanium nitride (TiN). Devices with larger dimensions were used, where the lateral gate influence can be neglected, presenting a planar behavior. Three-dimensional numerical simulations followed by experimental measurements validated the methods used in multiple-gate structures with wide channel width. The capacitance was also used in order to analyze the corner effect influence under these structures. In sequence, it was investigated the impact that the metal gate TiN thickness variation cause on the electric characteristics on the SOI triple gate transistors with silicate of hafnium oxide (HfSiO) as gate oxide. Beyond threshold voltage, work function, mobility, interface trap density and analog characteristics were analyzed. The results showed that thinner TiN are highly attractive, showing a reduction on the threshold voltage and trap density, an improved mobility and of the intrinsic gain of the transistor. However, an increase on the leakage current is observed in these devices. Together with this analyzes the behavior of triple gate transistors with gate dielectric of silicate of hafnium oxide nitrated (HfSiON) was also studied, where for the HfSiON a higher interface trap density impact was observed. Nevertheless it is efficient on the reduction impurity diffusion to cross until the silicon oxide (SiO2) that interfaces with the silicon channel. Finally, triple gate transistors with different gate stacks were experimentally studied, where a dysprosium oxide layer (Dy2O3) was deposited between the silicate of hafnium oxide (HfSiO) and the TiN metal gate. We observed a reduction in the threshold voltage of theses devices with dysprosium oxide as well as a variation of flatband voltage. In summary, when the dysprosium oxide layer was deposited inside the TiN metal gate, a better interface was obtained, as well as a higher effective oxide thickness, resulting in a lower leakage current.

Este trabalho tem como objetivo investigar o comportamento de transistores SOI de porta tripla com óxido de porta de alta constante dielétrica e eletrodo de porta de metal. Inicialmente estudou-se a aplicação dos métodos de extração de parâmetros através de curvas da capacitância, previamente desenvolvidos para estruturas SOI planares, em dispositivos de porta tripla com óxido de porta de háfnio (HfO2) e porta de metal com nitreto de titânio (TiN). Foram utilizados dispositivos com grandes dimensões, onde a influência das portas laterais pode ser desprezada, apresentando desta forma, um comportamento similar aos dispositivos com geometria planar. Simulações numéricas tridimensionais seguidas de medidas experimentais validam a utilização desses métodos em estruturas de múltiplas portas com grande largura de canal. A capacitância também foi utilizada para se analisar a influência que o efeito de canto exerce sobre estas estruturas de múltiplas portas. Na seqüência, foi investigado o impacto que a variação da espessura da porta de metal TiN causa nas características elétricas dos transistores SOI de porta tripla com óxido de porta de silicato de óxido de háfnio (HfSiO). Parâmetros como tensão de limiar, função de trabalho, mobilidade, cargas de interface assim como as características analógicas foram analisadas. Os resultados indicaram que camadas de TiN mais finas são mais atrativas, apresentando menor tensão de limiar e armadilhas de interface, assim como um aumento na mobilidade e no ganho intrínseco do transistor. Contudo uma maior corrente de fuga pelo óxido de porta é vista nestes dispositivos. Juntamente com esta análise, o comportamento de transistores de porta tripla com dielétrico de porta de silicato de óxido de háfnio nitretado (HfSiON) também foi estudado, onde observou-se um maior impacto nas cargas de interface para o óxido de háfnio nitretado. Contudo, o mesmo é capaz de reduzir a difusão de impurezas até o óxido de silício (SiO2) interfacial com o canal de silício. Finalmente transistores de porta tripla com diferentes composições de estrutura de porta foram estudados experimentalmente, onde uma camada de óxido de disprósio (Dy2O3) foi depositada entre o silicato de óxido de háfnio (HfSiO) e a porta de metal TiN. Observou-se uma redução na tensão de limiar nos dispositivos com o óxido de disprósio assim como uma variação na tensão de faixa plana. Em resumo, quando a camada de óxido de disprósio foi depositada dentro da porta de metal TiN, uma melhor interface foi obtida, assim como uma maior espessura de óxido efetivo, indicando desta forma uma menor corrente de fuga. / The main goal of this work is to investigate the behavior of SOI triple gate transistors with high dielectric constant gate oxide and metal gate material. Initially it was studied the application of process parameters extraction methods through capacitance curves, developed previously for planar SOI structures, in the triple-gate devices with hafnium gate oxide (HfO2) and metal gate of titanium nitride (TiN). Devices with larger dimensions were used, where the lateral gate influence can be neglected, presenting a planar behavior. Three-dimensional numerical simulations followed by experimental measurements validated the methods used in multiple-gate structures with wide channel width. The capacitance was also used in order to analyze the corner effect influence under these structures. In sequence, it was investigated the impact that the metal gate TiN thickness variation cause on the electric characteristics on the SOI triple gate transistors with silicate of hafnium oxide (HfSiO) as gate oxide. Beyond threshold voltage, work function, mobility, interface trap density and analog characteristics were analyzed. The results showed that thinner TiN are highly attractive, showing a reduction on the threshold voltage and trap density, an improved mobility and of the intrinsic gain of the transistor. However, an increase on the leakage current is observed in these devices. Together with this analyzes the behavior of triple gate transistors with gate dielectric of silicate of hafnium oxide nitrated (HfSiON) was also studied, where for the HfSiON a higher interface trap density impact was observed. Nevertheless it is efficient on the reduction impurity diffusion to cross until the silicon oxide (SiO2) that interfaces with the silicon channel. Finally, triple gate transistors with different gate stacks were experimentally studied, where a dysprosium oxide layer (Dy2O3) was deposited between the silicate of hafnium oxide (HfSiO) and the TiN metal gate. We observed a reduction in the threshold voltage of theses devices with dysprosium oxide as well as a variation of flatband voltage. In summary, when the dysprosium oxide layer was deposited inside the TiN metal gate, a better interface was obtained, as well as a higher effective oxide thickness, resulting in a lower leakage current.

L'imagerie médicale remonte à la fin du XIXe siècle avec la découverte des rayons X par Röntgen. Depuis, de nombreuses modalités d'imagerie ont été développées, et sont aujourd'hui utilisées dans une large gamme d'indications cliniques. L'imagerie TEP (Tomographie par Émission de Positron) est une modalité fonctionnelle, quantitative et ayant une haute sensibilité, ce qui en fait une modalité de choix, notamment en cancérologie. Hélas, sa diffusion est freinée en comparaison avec le scanner ou l'imagerie par résonance magnétique, en raison de son coût notamment. C'est dans ce contexte que s'insère cette thèse, qui a pour objectif de montrer la faisabilité d'un imageur TEP ambulatoire dédié au suivi thérapeutique en cancérologie. À partir de développements instrumentaux originaux (localisation des gammas par division de lumière dans des barreaux scintillateurs, lecture à l'aide de Silicon PhotoMultiplier, géométrie compacte), ces travaux s'efforcent de baisser les coûts tout en restant compétitif en terme de performances. Dans un premier temps, une étude extensive de la division de lumière à travers toute une série de paramètres (longueur des barreaux scintillateurs, revêtement optique, matériau scintillateur, traitement des données) a été menée. Une résolution spatiale inférieure à 5 mm pour un barreau de 75 mm de LYSO emballé dans du teflon a notamment été obtenue. À partir de cette configuration, une première image a été reconstruite, à partir de deux modules en coïncidence, offrant une résolution spatiale de 5 mm pour un tel imageur. Enfin, toute une série de simulations a été menée, à partir des données expérimentales et avec une géométrie originale. En particulier, les performances ont été mesurées à partir du protocole NEMA, un standard permettant de comparer les performances à travers la littérature. Une résolution spatiale intrinsèque de l'ordre de 4 mm a été obtenue, soit meilleure que le marché actuel. La sensibilité de l'ordre de 2.5 cps/kBq est revanche relativement basse par rapport à l'existant, mais s'explique par un champ de vue axial restreint. Enfin, le potentiel en terme de quantification a été adressé, et est comparable au marché actuel. / Medical imaging first began at the end of the XIXth century with the discover of X-rays by Röntgen. Then, numerous imaging modalities have been developed and are used now for a wide range of cases. Positron Emission Tomography (PET) has a high sensitivity, is functional and quantitative, thus being of high interest in cancer monitoring. Nevertheless, PET is not as much spread in hospitals as magnetic resonance imaging and scanner. In this context, this work aims to prove the faisability of PET dedicated for cancer monitoring. Thanks to instrumental developments such as light sharing in scintillating crystals, use of Silicon Photomultipliers, and an original geometry, cost is expected to be reduced while having same performances as commercial devices. An extensive study of light sharing within scintillating barrels has been made, through many parameters (crystal length, coating, data analysis...). An intrinsic spatial resolution of 4 mm has been measured over a 75 mm long crystal of LYSO, coated with teflon. From such a configuration, a first image has been reconstructed using two modules in coincidence. A spatial resolution of 5 mm has been measured in the image. Finally, Monte Carlo simulations has been made with experimental data as input, in order to measure the performances of the final PET device. Thanks to NEMA standard protocol, performances has been measured and compared to other systems. A spatial resolution of 4 mm has been reached, for a sensitivity of 2.5 cps/kBq. Quantification problem has been assessed, providing results similar to existing devices.

In this thesis, the Cross-Gate SOI MOSFET that has double sources and double drains was successfully fabricated. The new SOI device structure has five unique features. First, it uses mesa isolation instead of using conventional LOCOS and trench isolation to avoid the bird¡¦s beak effect in LOCOS isolation and the complexity of digging trench in trench isolation¡F second, it has three surfaces of gate structures which can increase the effective channel width of the device to enhance the current drivability of the device without reducing the packing density of the circuit¡F third, it has four channels which can increase the current drivability of the device¡F fourth, it has narrowed source and drain that can reduce the leakage current¡F fifth, it has double sources and double drains that can design double or half current in the electric circuit by one device. According to the simulation results of the TSUPREM-4 and TMA TCAD, the saturation drain current of the multi-gate SOI devices are almost double larger than that of the conventional SOI device as VGS - Vth = 0.7 V. And the threshold voltage¡B Ion/Ioff and subthreshold factor of the Cross-Gate SOI device are almost the same with such of the Four Channels Multi-Gate SOI device. As far as the fabrication process is concerned, the new SOI device has simpler isolation processes than that of the conventional one. In addition, the nano-devices that Leff ¡× 71nm was successfully fabricated. As concerning the electrical behavior, under the same condition of Leff ¡× 71nm, Weff ¡× 440nm, tsi ¡× 120nm, the Cross-Gate SOI device has the lower subthreshold factor which is 93.153 and the higher Ion/Ioff which is 1.66¡Ñ10E5 than those of the Four Channels Multi-Gate SOI device, in addition, the Cross-Gate SOI device has no kink effect. So, it can be concluded that such the Cross-Gate SOI device presented is much more applicable to the development of low power and high speed ULSI in the nearest future.

This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.

La diminution de la taille des transistors actuellement utilisés en microélectronique ainsi que l’augmentation de leurs performances demeure encore au centre de toutes les attentions. Cette thèse propose d’étudier et de fabriquer des transistors à base de nanofils empilés. Cette architecture avec des grilles enrobantes est l’ultime solution pour concentrer toujours plus de courant électrique dans un encombrement minimal. Les simulations ont par ailleurs révélé le potentiel des nanofeuillets de silicium qui permettent à la fois d’optimiser l’espace occupé tout en proposant des performances supérieures aux dispositifs actuels. L’importance de l’ajout de certaines étapes de fabrication a également été soulignée. En ce sens, deux séries d’étapes de fabrication ont été proposées : la première option vise à minimiser le nombre de variations par rapport à ce qui est aujourd’hui en production tandis que la deuxième alternative offre potentiellement de meilleures performances au prix de développements plus importants. Les transistors ainsi fabriqués proposent des performances prometteuses supérieures à ce qui a pu être fabriqué dans le passé notamment grâce à l’introduction de contraintes mécaniques importantes favorables au transport du courant électrique. / The future of the transistors currently used in Microelectronics is still uncertain: shrinking these devices while increasing their performances always remains a challenge. In this thesis, stacked nanowire transistors are studied, fabricated and optimized. This architecture embeds gate all around which is the ultimate solution for concentrating always more current within a smaller device. Simulations have shown that silicon nanosheets provide an optimal utilization of the space with providing increased performances over the other technologies. Crucial process steps have also been identified. Subsequently, two process flows have been suggested for the fabrication of SNWFETs. The first approach consists in minimizing the number of variations from processes already in mass production. The second alternative has potentially better performances but its development is more challenging. Finally, the fabricated transistors have shown improved performances over state-of-the-art especially due to mechanical stress induced for improving electric transport.