Le mémoire de thèse est structuré en 3 chapitres. Le 1er chapitre présente le contexte de forte vitesse de commutation et de forte intégration en électronique de puissance, dans lequel s’inscrit cette thèse. Les fonctions et les enjeux de l’organe de commande rapprochée (« gate driver ») sont présentés. L’intégration du gate driver en technologie CMOS AMS 0.18 µm HV est présentée puis, plus particulièrement, l’intégration des fonctions optiques. Le 2e chapitre concerne l’étude de la transmission et de la modulation des charges à travers la barrière d’isolation optique. Un amplificateur en courant configurable a été dimensionné afin de pouvoir faire varier la résistance de grille. Une alimentation optique est intégrée en technologie AMS H18, comprenant une cellule PV et un convertisseur DC/DC à capacités commutées. Dans le 3e chapitre, 2 approches ont été développées pour la transmission du signal, la transmission dite en bande de base où les ordres de commande optiques sont l’image directe de la modulation en largeur d’impulsion (MLI), et la transmission dite numérique série où les changements d’état sont envoyés avec une trame haute fréquence. Un circuit de gestion logique et une horloge interne ont été conçus. La transmission numérique permet l’envoi d’information telle que la configuration de la résistance de grille. Le dimensionnement des circuits prend en compte une large plage de température de fonctionnement (-40°C à 140 °C), ainsi que les contraintes dues à l’alimentation optique (variation de la tension d’alimentation) et à l’alignement optique (variation du photo-courant généré). / The thesis dissertation is composed of 3 chapters. The 1st chapter introduces the thesis context of fast switching transients and highly integrated power electronics circuits. The functions and the issues of the close gate driver are presented. The gate driver is integrated in the AMS 0.18 µm technology with its optical functions. The second chapter deals with the transmission and modulation of the gate driver charge through the optical isolation barrier. A configurable buffer is designed in order to modulate the gate resistance value. An optical supply including a PV cell and a switched capacitors DC/DC converter is integrated. In the third chapter, two approaches are developed for the gate signal transfer. For the baseband analog transmission, the optical signal is a direct image of the pulse width modulation (PWM) signal whereas in the digital series transmission, only the commutation orders are transmitted in a high frequency frame. A logic circuit and an integrated clock are designed. The digital transmission allowed the transfer of information such as the gate resistance configuration. Large temperature range (-40°C to 140°C), optical supply constraints (supply voltage deviation) and optical alignment (photocurrent value deviation) are considered for the integrated circuits design.

La planification de traitement en radiothérapie nécessite un calcul précis de la dose délivrée au patient. La méthode la plus fiable pour y parvenir est la simulation du transport des particules par technique Monte Carlo. Cette thèse constitue la première étude concernant la validation de la plateforme de simulation Monte Carlo GATE (GEANT4 Application for Tomographic Emission), basée sur les librairies de GEANT4 (GEometry ANd Tracking), pour le calcul de la dose absorbée déposée par des faisceaux d’électrons. L’objectif de cette thèse est de montrer que GATE/GEANT4 est capable d’atteindre le niveau d’exigences requis pour le calcul de la dose absorbée lors d’une planification de traitement, dans des situations où les algorithmes analytiques, actuellement utilisés dans les services de radiothérapie, n’atteignent pas un niveau de précision satisfaisant. L’enjeu est de prouver que GATE/GEANT4 est adapté pour la planification de traitement utilisant des électrons et capable de rivaliser avec d’autres codes Monte Carlo reconnus. Cet enjeu a été démontré par la simulation avec GATE/GEANT4 de faisceaux et des sources d’électrons réalistes utilisées en radiothérapie externe ou en radiothérapie moléculaire et la production de distributions de dose absorbée en accord avec les mesures expérimentales et avec d’autres codes Monte Carlo de référence pour la physique médicale. Par ailleurs, des recommandations quant à l’utilisation des paramètres de simulation à fixer, assurant un calcul de la distribution de dose absorbée satisfaisant les spécifications en radiothérapie, sont proposées. / Radiation therapy treatment planning requires accurate determination of absorbed dose in the patient. Monte Carlo simulation is the most accurate method for solving the transport problem of particles in matter. This thesis is the first study dealing with the validation of the Monte Carlo simulation plateform GATE (GEANT4 Application for Tomographic Emission), based on GEANT4 (GEometry And Tracking) libraries, for the computation of absorbed dose deposited by electron beams. This thesis aims at demonstrating that GATE/GEANT4 calculations are able to reach treatment planning requirements in situations where analatycal algorithms are not satisfactory. The goal is to prove that GATE/GEANT4 is useful for treatment planning using electrons and competes with well validated Monte Carlo codes. This is demonstrated by the simulations with GATE/GEANT4 of realistic electron beams and electron sources used for external radiation therapy or targeted radiation therapy. The computed absorbed dose distributions are in agreement with experimental measurements and/or calculations from other Monte Carlo codes. Furthermore, guidelines are proposed to fix the physics parameters of the GATE/GEANT4 simulations in order to ensure the accuracy of absorbed dose calculations according to radiation therapy requirements.

The Square Kilometre Array (SKA) is known to be the most powerful radio telescope of its type. In support of its high observational power, it is estimated that thousands of antenna unit equipped with millions of LNA (low noise amplifier) will be deployed over a large area (radius>3000km). The stringent requirements for high performance and low cost LNA design bring about many challenges in terms of material growth, device fabrication and low noise circuit designs. For the past decade, the Manchester group has been wholeheartedly committed to the research and development of high performance, low cost Monolithic Microwave Integrated Circuit (MMIC) LNA with high breakdown (15V) and low noise characteristics (1.2dB to 1.5dB) for the SKA mid-frequency application (0.4GHz to 1.4GHz). The on-going optimisation of current design is hindered by the restriction of standard i-line 1µm gate lithography. The primary focus of this work is on the design and fabrication of new, submicron gate InGaAs/InAlAs/InP pHEMTs for high frequency applications and future SKA high frequency bands. The study starts with the design and fabrication of InGaAs-InAlAs pHEMT sub-100nm gate structure using E-Beam lithography. To address the problems of short channel effect and parasitic components, devices with 128nm T-gate structure, and with optimised device geometries and enhanced material growth, having fT of 162GHz and fmax of 183GHz are demonstrated, outlining the importance of device scaling for high speed operation. In addition, a gate-sinking technique using Pd/Ti/Au metallisation scheme was investigated to meet the requirement for single voltage supply in circuit design. Device with Pd-buried gate exhibits enhanced DC and RF characteristics and showed no degradation over 5 hours’ annealing at 230˚C. The implementation of this highly thermal stable Pd Schottky gate is key to improving the device’s long-term reliability at high-temperature operation. To solve the problem of low productivity in E-Beam lithography, a simple, low cost, technique termed soft reflow was introduced by utilising the principle of solvent vaporisation in a closed chamber. It provides a hybrid solution for the fabrication of submicron device using low cost i-line lithography. The integration of this new soft reflow process with the Pd-gate sinking technique has enabled the large-scale fabrication of 250nm T-gate pHEMTs, with excellent fT of 108GHz and a fmax of 119GHz and with device yields exceeding 80%. This novel soft reflow technique provides a high yield, fast throughput, solution for the fabrication of submicron gate pHEMT and other ultra-high frequency nanoscale devices.

Purpose: The research purpose is to, in a systematic way, build a method to develop suggestions regarding layout planning of gates in a marine terminal and additionally conduct a base for a simulation model. Approach: Firstly, a literature review has been conducted in the fields relevant to port security and gate configurations in marine terminals. Secondly, a case study has been executed in a Swedish marine terminal. The case study consisted of interviews and observations at the case company, who also provided this thesis with numerical raw data. Additionally, a benchmarking was conducted at a company in the same port area where interviews and observations was executed.   Findings: The findings in this thesis resulted in a methodology improvement, which contains important procedure steps that need to be considered while conducting a layout for a gate in a marine terminal. The procedure resulted in a conceptual model that was conducted as a result of the literature review and verified by being tested in the case study. Limitation: The thesis is limited to one case company. Even though it verified and validated the findings, additional case companies are recommended to fully validate the conceptual model which applies for further research. Further limitations to this thesis is that the financial- and technical factors will not be executed.   Theoretical implications: Companies who plans to increase the security in their marine terminal area or implement a new gate system can benefit from the findings. This thesis contributes to science by adding new theory.   Practical implications: This thesis conducted a conceptual model for a layout procedure which recommends to follow while planning a layout for a gate in a marine terminal. The model were verified with a case company and provided two layout suggestions that can be implemented at the specific company.

Placement is one of the most important steps in physical design for VLSI circuits. For field programmable gate arrays (FPGAs), the placement step determines the location of each logic block. I present novel timing and congestion driven placement algorithms for FPGAs with minimal runtime overhead. By predicting the post-routing timing-critical edges and estimating congestion accurately, this algorithm is able to simultaneously reduce the critical path delay and the minimum number of routing tracks. The core of the algorithm consists of a criticality-history record of connection edges and a congestion map. This approach is applied to the 20 largest Microelectronics Center of North Carolina (MCNC) benchmark circuits. Experimental results show that compared with the state-of-the-art FPGA place and route package, the Versatile Place and Route (VPR) suite, this algorithm yields an average of 8.1% reduction (maximum 30.5%) in the critical path delay and 5% reduction in channel width. Meanwhile, the average runtime of the algorithm is only 2.3X as of VPR.

Une réduction de l'inhibition segmentaire contribue vraisemblablement à l'hypersensibilité douloureuse persistante – qui se manifeste par l'hyperalgie, l'allodynie, et la douleur spontanée – au cours d'états douloureux chroniques. L'association fréquente d'une allodynie avec la migraine – une céphalée épisodique – suggère qu'une perte de l'inhibition synaptique contribue aussi à la manifestation de la douleur migraineuse. Cependant, la grande prévalence de la migraine – plus de 10% de la population générale – soulève la question de savoir si le traitement des informations méningées par le réseau neuronal – associant interneurones excitateurs et inhibiteurs – dans le complexe trigéminal, premier relais sur les voies nociceptives de la face et des méninges, est le même que celui des autres informations, par exemple cutanées. Nous avons caractérisé l'effet du blocage pharmacologique des récepteurs à la glycine (GlyR) et des récepteurs GABAA (GABAAR) sur la transmission synaptique entre fibres afférentes primaires, cutanées ou méningées, et neurones de second ordre en enregistrant des potentiels de champ dans le sous-noyau caudal superficiel (Sp5C). Une stimulation électrique transcutanée évoque trois potentiels de champ négatifs dus à l'activation, du plus précoce au plus tardif, de fibres afférentes primaires de type Aβ, Aδ et C. Bloquer les GlyRs et/ou GABAARs segmentaires facilite les potentiels de champ polysynaptiques excitateurs évoqués par l'activation des fibres afférentes primaires de type A et, au contraire, inhibe, ou même abolit, les potentiels de champ C. Bloquer les récepteurs GABAB (GABABR) segmentaires prévient cette suppression. Il est intéressant de noter que bloquer les GABABRs, potentialise aussi les potentiels de champ C en condition controle. Une stimulation électrique méningée évoque deux potentiels de champ négatifs dus à l'activation, du plus précoce au plus tardif, des fibres afférentes primaires de type Aδ et C. Au contraire du potentiel de champ C cutané, le potentiel de champ C méningé est potentialisé après blocage des GlyRs et/ou GABAARs segmentaires. Ces résultats démontrent que le traitement des informations cutanées et méningées par le Sp5C est différent. Seule l'activation des fibres afférentes primaires cutanées de type A inhibe les inputs cutanés de type C vers le Sp5C par l'intermédiaire d'un circuit polysynaptique excitateur, d'interneurones GABAergiques de dernier ordre et de GABABRs présynaptiques. La théorie du "gate control" postule que l'activité des afférences non-nociceptives ferme la porte à la transmission des inputs nociceptifs vers les centres supérieurs. Nos résultats suggèrent que l'état de la porte dépend de l'activité non seulement dans les fibres afférentes primaires de type A mais aussi dans les circuits polysynaptiques excitateurs de la corne dorsale. / Pathological disruption of segmental inhibition is thought to contribute to persistent pain hypersensitivity – including hyperalgesia, allodynia and spontaneous pain – that occurs during chronic pain states. That allodynia is also often associated with migraine – an episodic headache – suggests that a loss of synaptic inhibition is also involved in the manifestation of headache pain. However, the very high prevalence of migraine – more than 10% of the general population – raises the question as to whether processing of meningeous inputs by local neuronal network – consisting of excitatory and inhibitory interneurons – within the trigeminal nucleus, the first relay station for incoming nociceptive signals of the face and meninges, is the same as that of others, for instance cutaneous. We sought to characterize how pharmacological blockade of glycine and GABAA receptors modifies synaptic transmission between either cutaneous or meningeous primary afferent fibers and second order neurons by recording field potentials in the rat superficial medullary dorsal horn (MDH). Transcutaneous electrical stimulation evokes three negative field potentials elicited by, from the earliest to the latest, Aβ-, Aδ- and C-fiber primary afferents. Blocking segmental glycine and/or GABAA receptors strongly facilitates A-fiber-activated polysynaptic excitatory field potentials but, conversely, inhibits, or even abolishes, C-fiber field potentials. Blocking segmental GABAB receptors reverses such suppression. Interestingly, it also potentiates C-fiber field potentials under control conditions. Meningeous electrical stimulation evokes two negative field potentials elicited by, from the earliest to the latest, Aδ- and C-fiber primary afferents. Unlike cutaneous C-fiber field potentials, meningeous ones are facilitated by blocking segmental glycine and/or GABAA receptors. These results demonstrate that MDH processing of cutaneous and meningeous inputs are different. Only activation of cutaneous A-fiber primary afferents inhibits cutaneous C-fiber inputs to the MDH by the way of polysynaptic excitatory pathways, last-order GABAergic interneurons and presynaptic GABAB receptors. In view of the gate control theory postulating that afferent volleys in non-nociceptive afferents close the gate to central transmission of nociceptive inputs, our results suggest that the state of the gate depends on firing activities of both A-fiber primary afferents and polysynaptic excitatory circuits, i.e. the inhibitory tone, within the dorsal horn.

Bakgrund: Global konkurrens och teknologisk utveckling förkortar produkters livscykler och produktutveckling blir därmed ett allt viktigare element inom organisationer. Vid utvecklingen krävs styrning för att säkerställa att de innovationer som skapas är i linje med företagets mål och strategier. Ett av de mer välanvända styrsystemen som används vid produktutveckling har kritiserats för att vara en för linjär process som exkluderar lärande från utvecklingsarbetet. Alternativa metoder har på senare tid dykt upp i både forskning och på företag för att möjliggöra en mer dynamisk utvecklingsprocess. Syfte: Syftet med denna studie är att identifiera hur produktutvecklingsprocessen ser ut i några svenska företag. Vidare ska studien öka förståelsen för hur produktutvecklingsprocessen styrs i dessa företag och även identifiera och analysera de hinder som finns för innovation i denna process. Metod: Detta är en deduktiv flerfallstudie där semistrukturerade intervjuer och dokument har använts för att samla in det empiriska materialet. Slutsats: Utifrån studiens resultat bekräftas en generell produktutvecklingsprocess som presenteras i studiens referensram. Dessa är konceptualisering, prototyputveckling, lansering och uppföljning. Däremot finns det tecken på att företag med agila utvecklingsmetoder inte följer denna standardiserade modell. Vidare beskrivs vilka styrverktyg som används för att styra en produktutveckling. Dessa har kategoriserats efter Malmi och Browns styrpaket. I slutsatsens tredje och sista punkt presenteras hinder mot innovation som har identifierats i produktutvecklingsprocessen. Ett tydligt hinder som har identifierats är att Stage-Gate och kvalitetssäkring bromsar innovation efter tidiga stadier i processen. Ytterligare ett tydligt hinder är att ett fokus på att förkorta “time-to-market” kan göra att vissa innovationer inte hinner inkluderas i produkten. / Background: Global competition and technological advancements have shortened the product life cycle of countless products worldwide. Product development is therefore becoming an increasingly important element in organizations. In the process of product development, management control is required to ensure that new innovation follows the strategy and goals of the organization. The Stage-Gate system is a well-used new product development model that has been criticized for being too rigid and hinders learning in the development process. As of recent years, alternative methods have appeared in studies and in businesses in order to enable a more dynamic process. Purpose: The purpose of this study is to identify the different stages of a product development process at a number of Swedish firms. This study also aims to increase the understanding of how the product development process is being managed in these companies as well as to identify and analyze factors that can hinder innovation in the new product development process. Method: This is a deductive case study with a multiple-case design. Semi-structured interviews and documents have been used for the collection of empirical data. Conclusion: The results of this study settles a general development process as presented in the study’s theory chapter. The development process includes the following phases: concept development, prototype development, market introduction and follow-up. However, there are implications that show that companies who use an agile development model do not follow the aforementioned development process. This study also concludes the elements of a management control system that is used in the product development process at Swedish companies. These elements are categorized by the management control systems package of Malmi and Brown. Lastly, challenges to include innovations to the product is being identified. An obstacle that has been identified is the use of Stage-Gate and quality assurance that hinders innovation in the later stages of the development process. An additional obstacle is that a focus on shortening the time-to-market period may hinder some innovations of a product because of a short deadline.

Företag utvecklar nya produkter för att öka intäkterna och fortsätta vara konkurrenskraftiga. Produktutveckling är ett område det forskats mycket inom och forskningen fokuserar ofta på innovativa produkter. Det ursprungliga problemet för denna uppsats var att göra en undersökning inför utvecklingen av en produkt med låg grad av teknisk innovation. Den tidigare forskningens höga fokus på innovation kombinerat med att uppdragsgivaren inte har några processer för produktutveckling gjorde att uppsatsens omfattning utökades. Denna uppsats presenterar en modell för utveckling av produkter med låg innovation samt en applicering av modellen. Modellen utvecklades genom att studera tidigare litteratur om produktutveckling, främst kring Stage-Gate modeller, och även om kriterier och best-practice inom produktutveckling. Litteraturstudien kombinerades med resultat från intervjuer och resulterade i en modell för utveckling av låginnovativa produkter. Modellen är delad i två delar, den första fokuserar på analys av produktförslaget och den andra fokuserar på att utveckla produkten. Jämfört med tidigare modeller har omfattningen för de olika stegen och gaterna blivit mer fokuserad och tydlig. Den första delen av modellen testades genom att applicera den på det ursprungliga produktförslaget. Testet visade att modellen är passande för den typen av produkter och att de föreslagna generella kriterierna var rimliga. För den specifika produkten visade modellen att produkten var strategiskt passande för företaget och att den är tekniskt genomförbar. De finansiella beräkningarna visade att produkten möjligen inte är tillräckligt attraktiv finansiellt. Några av uppsatsens huvudsakliga slutsatser rör skillnader beroende på hur innovativ produkten är. Processens start skiljer sig signifikant, för innovativa produkter börjar den med en idé och för denna forsknings miljö med ett specifikt förslag. Fokus i finansiella frågor skiljer sig också. Överlag kunde slutsatsen att produktutveckling med en Stage-Gate-metod passar för produkter med låg grad av teknisk innovation dras men det krävs förändringar från tidigare forskning / To increase revenues and continue to stay competitive companies develop new products. Newproduct development is a widely researched field and the focus of the research is often on highly innovative products. The original problem for this thesis was to perform research for the development of a product with a low level of technological innovation. The high focus on innovation in previous research combined with the lack of product development processes in the case company led to a new more extensive scope of this thesis than the original problem. This thesis presents a model for development of products with low level of innovation that has been developed and tested.The model was developed by reviewing previous literature on new product development in general and Stage-Gate models for product development in particular. Literature about criteria and best practices in product development was also studied. The literature review was combined with findings from early interviews and resulted in a development model for low innovative products. The model is divided in two parts, the first focused on analysis of the product suggestion and the second focused on developing the actual product. Compared to previous models, the scope of the stages and gates has been more focused and clear.The first part of the model was tested by applying it to the initial case. The test showed that the model is suitable for a product of that type and that the general criteria proposed was reasonable. For the specific case, the model showed that the product was a strategic fit for the company and that it is technically feasible. The financial calculations showed that the product might not financially attractive enough.Some of the main conclusions of the research are regarding differences depending on how innovative the product is. The starting point differs significantly, with an idea for innovative products and a specific suggestion in the setting of this research. The financial focus also differs. Overall it could be concluded that development with a Stage-Gate approach is suitable for products with low level of technological innovation with some changes from previous literature.

De nos jours, la complexité de la conception des circuits intégrés et du logiciel croit régulièrement, faisant croître le besoin de la vérification dans chaque étape du cycle de conception. Le prototypage matériel sur une plateforme multi-FPGA présente le meilleur compromis entre le temps de conception d'un circuit et le temps d'exécution d'une application par ce circuit. Pour l'implémenter sur cette plateforme, une opération de partitionnement est effectuée avant de créer des partitions capables de s'intégrer dans chaque FPGAPar conséquent, des signaux coupés à l'interface des partitions doivent passer d'un FPGA à un autre. Cependant, le nombre de traces physiques inter-FPGA est limité ce qui crée des problèmes de routabilité du circuit prototypé. Cette thèse touche surtout la partie post-partitionnement et s'intéresse au problème deroutage inter-FPGA. Ainsi, les principaux travaux de cette thèse sont les suivants :Dans un premier temps, nous nous intéressons au développement d'un générateur debenchmarks qui permet, à l'aide d'une description architecturale simple du benchmark, de générer un circuit modélisé avec le langage de description matérielle VHDL. Le générateur utilise un ensemble de composants ce qui donne aux benchmarks un aspect réel semblable à celui des circuits industriels. Ces circuits de tests nous serviront pour évalue rles performances des techniques développées dans cette thèse. Dans un deuxième temps, nous proposons de développer un outil spécifique qui intervient après le partitionnement pour prendre en compte la contrainte liée à la limitation du nombre d'interconnexion entre les FPGAs. Cet outil est basé sur une approcheitérative visant à réduire le taux de multiplexage (nombre de signaux qui partagent un seul _l physique). Le routage en lui même est assuré par l'algorithme de routage Pathfinder adapté. Cet algorithme servira comme point de départ pour les techniques de routage développées durant cette thèse. Des adaptations adéquates seront faites pour cibler un ré-seau de routage inter-FPGA. Dans une deuxième partie, nous essayons de déterminer la meilleure forme du signal à router (bi-points ou multi-points) ainsi que le graphe de routage utilisé. Pour cela, nous proposons des scénarios de test a_n de sélectionner les critères qui donnent la fréquence de fonctionnement la plus performante. Par la suite, nous présentons une description détaillée des IPs de multiplexage utilisés.Ces IPs sont insérés dans les parties émettrices et réceptrices d'un canal de communication. Ces IPs incluent des composants spécifiques appelés SERDES pour assurer la sérialisation/déserialisation des données à transmettre. L'insertion de ces composants peut créer des problèmes de routabilité intra-FPGA. Ainsi, dans une deuxième partie, nous proposons un algorithme de placement basé sur l'estimation de la congestion afin d'améliorer la routabilité du circuit. / This thesis mainly deals with the post-partitioning task and addresses the problem of inter-FPGA routing. Thus, the main contributions of this thesis are: Firstly, we focus on the development of a benchmark generator which, using a simple architectural description of the benchmark, generates a circuit modelled with the hardware description language VHDL. The generator uses a set of industrial components providing benchmarks with real behaviour similar to that of industrial circuits. These benchmarks are used to evaluate the performance of the techniques developed in this thesis. In a second step , we propose a speci_c tool which acts after the partitioning to handle the constraints related to the limited number of interconnection between FPGAs. This tool is based on an iterative approach and aims to reduce the multiplexing ratio (the number of signals that share the same physical wire). The routing task itself is operated by the Pathfinder routing algorithm which is widely used by academic and industrial researchers . This algorithm is used as a starting point for routing techniques developed in this thesis . In a second part , we try to identify the best shape of the routed signals and the appropriate routing graph. For this reason, we propose scenarios to select criteria that give the best system frequency. Finally, we present a detailed description of the architecture of the multiplexing IPs. These IPs are inserted in the transmitting and receiving FPGAs of a communication channel. These IPs include speci_c components called SERDES for serialization/deserialization of the data. The insertion of these IPs can create problems of intra-FPGA routability. Thus, in a second part, we propose a placement algorithm based on congestion estimation to improve the routability of the circuit.

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