A new approach for the fine tuning of flexibility in MOFs, involving functionalization of the secondary building unit, is presented. The "gate pressure" MOF [Zn3(bpydc)2(HCOO)2] was used as a model material and SBU functionalization was performed by using monocarboxylic acids such as acetic, benzoic or cinnamic acids instead of formic acid in the synthesis. The resulting materials are isomorphous to [Zn3(bpydc)2(HCOO)2] in the "as made" form, but show different structural dynamics during the guest removal. The activated materials have entirely different properties in the nitrogen physisorption experiments clearly showing the tunability of the gate pressure, at which the structural transformation occurs, by using monocarboxylic acids with varying backbone structure in the synthesis. Thus, increasing the number of carbon atoms in the backbone leads to the decreasing gate pressure required to initiate the structural transition. Moreover, in situ adsorption/PXRD data suggest differences in the mechanism of the structural transformations: from "gate opening" in the case of formic acid to "breathing" if benzoic acid is used.

L’imagerie 3γ est une technique innovante d’imagerie médicale nucléaire qui est étudiée au laboratoire SUBATECH. Elle repose sur la localisation tridimensionnelle d’un radioisotope émetteur (β+, γ), le 44Sc, à l’aide d’un télescope Compton au xénon liquide. Le lieu de désintégration de ce radioisotope est obtenu par l’intersection de la ligne de réponse, construite à partir de la détection des deux photons de 511 keV issus de l’annihilation d’un positron, et du cône déterminé à partir du troisième photon. Un prototype de petite dimension XEMIS1 (XEnon Medical Imaging System) a été développé afin de faire la preuve expérimentale de la faisabilité de l’imagerie à 3γ. Les résultats de ce prototype sont très promoteurs en terme de résolution en énergie, de pureté du xénon liquide et de faible bruit électronique. La simulation Monte Carlo est un outil indispensable pour accompagner la R&D et évaluer les performances de la nouvelle technique d’imagerie proposée. Les travaux rapportés dans cette thèse concernent le développement de la simulation du système d’imagerie 3γ avec GATE (Geant4 Application for Tomographic Emission). De nouvelles fonctionnalités ont été implémentées dans GATE afin de simuler un détecteur de type TPC (Time Projection Chamber). Nous avons effectué une simulation du prototype XEMIS1 et obtenu des résultats en bon accord avec nos données expérimentales. La prochaine étape du projet consiste à construire une caméra cylindrique au xénon liquide pour l’imagerie du petit animal. Les résultats des simulations de cette caméra présentés dans cette thèse montrent la possibilité de localiser chaque désintégration le long de la ligne de réponse avec une très bonne précision et une bonne sensibilité de détection. Des premières images de fantômes simples, réalisées évènements par événements, et après reconstruction tomographiques ont également présentées. / Nuclear medical 3γ imaging is an innovative technique which is studied at the SUBATECH laboratory. It isbased on the three-dimensional localization of a (β+, γ) radioisotope emitter, the 44Sc, by using a liquid xenon Compton telescope. The position of the disintegration of this radioisotope is obtained by the intersection of the line of response, built by the detection of two 511 keVphotons from the annihilation of a positron, and the cone determined by the third photon. A small prototype XEMIS1 (XEnon Medical Imaging System) was developed to demonstrate experimentally the feasibility of 3γ imaging. The results of this prototype are quite encouraging in terms of energy resolution, purity of liquid xenon and electronic noise. The Monte Carlo simulation is an indispensable tool to support the R&D and to evaluate the new proposed technique of imaging ; this thesis work is to develop the simulation of 3γ imaging system by using GATE (Geant4 Application for Tomographic Emission). New functionalities have been added to GATE to simulate a TPC (Time Projection Chamber) detector. We performed a simulation of XEMIS1 prototype and obtained results in good agreement with our experimental data. The next step of the project is to build a full liquid xenon cylindrical camera for the small animal imaging. The results presented in this thesis of the simulations of this camera demonstrate the ability to locate every decayalong the line of response with very good accuracy and good detection sensitivity. The first direct images of simple phantoms, realized event by event, and after tomographic reconstruction are also presented.

Les méthodes de simulation Monte-Carlo s’étendent avec succès à différents domaines de la physique médicale mais aussi à différentes échelles, par exemple de la planification des traitements de radiothérapie jusqu’à une prévision des effets des rayonnements au niveau des cellules cancéreuses. La plateforme de simulation Monte-Carlo GATE, basée sur l’outil Geant4, propose des fonctionnalités dédiées aux simulations en physique médicale (médecine nucléaire et radiothérapie). Pour les applications en radiobiologie, les modèles physiques Geant4-DNA implémentés jusqu’à très basse énergie (eV) permettent d’estimer des quantités micro-dosimétriques d’intérêt. Dans le but d’implémenter une plateforme de simulation Monte-Carlo multi-échelles, nous nous sommes d’abord intéressés à la validation des modèles physiques de Geant4-DNA, puis à leur intégration dans la plateforme de simulation GATE et enfin à une validation de cette implémentation dans un contexte de radiothérapie et protonthérapie. De manière à valider les modèles physiques de Geant4-DNA, des points kernels de dose en électrons mono-énergétiques (de 10 keV à 100 keV) ont été simulés en utilisant les modèles physiques de Geant4 et de Geant4-DNA et ils ont comparés au code Monte-Carlo EGSnrc. Les parcours et pouvoirs d’arrêts des électrons (de 7,4 eV à 1 MeV) et des protons (de 1 keV à 100 MeV) calculés avec Geant4-DNA (processus et modèles préalablement intégrés dans GATE) ont ensuite été validés. Nous avons alors proposé de simuler avec la plateforme GATE l’impact de faisceaux cliniques et pré-cliniques sur l’ADN cellulaire. Nous avons ainsi modélisé un faisceau de protonthérapie de 193,1 MeV, un accélérateur linéaire en mode électrons de 6 MeV et un irradiateur RX de 250 kV. Ces simulations ont d’abord été validées en milieu aqueux par une comparaison de la dose macroscopique avec des mesures expérimentales. Les faisceaux ont ensuite été utilisés pour calculer, pour chacun d’entre eux, les fréquences de dépôts d’énergie à l’ADN. La molécule d’ADN a été simulée tout d’abord grâce à des cylindres équivalents en dimension à 10 paires de base (2 nm x 2 nm), équivalents à la taille d’un nucléosome (10 nm x 5 nm) et équivalents à la taille d’une fibre de chromatine (25 nm x 25 nm). Tous ces cylindres ont été placés aléatoirement dans un volume d’eau liquide (de rayon 500 nm). Nous avons ensuite reconstruit la molécule d’ADN dans Geant4 à partir de la lecture de fichiers PDB (Protein Data Bank) représentant douze paires de base de la molécule d’ADN et un dinucléosome (347 paires de base). Enfin, nous avons développé un outil permettant de corréler les positions de dépôts d’énergie directs dans l’eau liquide avec les coordonnées des paires de base de l’ADN, afin de calculer les nombres de cassures simple et double brin de l’ADN. Tous les calculs réalisés au cours de ce travail, ont été déployés sur l’Infrastructure de Grille Européenne ; des tests de performance sont proposés pour mesurer l’intérêt de ce type d’architecture pour les calculs Monte-Carlo. / The Monte Carlo simulation methods are successfully being used in various areas of medical physics but also at different scales, for example, from the radiation therapy treatment planning systems to the prediction of the effects of radiation in cancer cells. The Monte Carlo simulation platform GATE based on the Geant4 toolkit offers features dedicated to simulations in medical physics (nuclear medicine and radiotherapy). For radiobiology applications, the Geant4-DNA physical models are implemented to track particles till very low energy (eV) and are adapted for estimation of micro-dosimetric quantities. In order to implement a multi-scale Monte Carlo platform, we first validated the physical models of Geant4-DNA, and integrated them into GATE. Finally, we validated this implementation in the context of radiation therapy and proton therapy. In order to validate the Geant4-DNA physical models, dose point kernels for monoenergetic electrons (10 keV to 100 keV) were simulated using the physical models of Geant4-DNA and were compared to those simulated with Geant4 Standard physical models and another Monte Carlo code EGSnrc. The range and the stopping powers of electrons (7.4 eV to 1 MeV) and protons (1 keV to 100 MeV) calculated with GATE/Geant4-DNA were then compared with literature. We proposed to simulate with the GATE platform the impact of clinical and preclinical beams on cellular DNA. We modeled a clinical proton beam of 193.1 MeV, 6 MeV clinical electron beam and a X-ray irradiator beam. The beams models were validated by comparing absorbed dose computed and measured in liquid water. Then, the beams were used to calculate the frequency of energy deposits in DNA represented by different geometries. First, the DNA molecule was represented by small cylinders : 2 nm x 2 nm ( 10 bp), 5 nm x 10 nm ( nucleosome) and 25 nm x 25 nm ( chromatin fiber). All these cylinders were placed randomly in a sphere of liquid water (500 nm radius). Then we reconstructed the DNA molecule in Geant4 by reading PDB (Protein Data Bank) files representing twelve base pairs of the DNA molecule and a dinucleosome (347 base pairs). Finally, we developed a tool to correlate the positions of direct energy deposit in liquid water with the coordinates of the base pairs of DNA to calculate the number of single and double strand breaks in DNA. All calculations in this work were perfomed on the European Grid Infrastructure; performance tests are available to estimate the utility of this type of architecture for Monte Carlo calculations.

The increasing demand for energy efficient computing has endorsed the usage of Field-Programmable Gate Arrays to create hardware accelerators for large and complex codes. However, implementing such accelerators involve two complex decisions. The first one lies in deciding which code snippet is the best to create an accelerator, and the second one lies in how to implement the accelerator. When considering both decisions concomitantly, the problem becomes more complicated since the code snippet implementation affects the code snippet choice, creating a combined design space to be explored. As such, a fast design space exploration for the accelerators implementation is crucial to allow the exploration of different code snippets. However, such design space exploration suffers from several time-consuming tasks during the compilation and evaluation steps, making it not a viable option to the snippets exploration. In this work, we focus on the efficient implementation of pipelined hardware accelerators and present our contributions on speeding up the pipelines creation and their design space exploration. Towards loop pipelining, the proposed approaches achieve up to 100× speed-up when compared to the state-uf-the-art methods, leading to 164 hours saving in a full design space exploration with less than 1% impact in the final results quality. Towards design space exploration, the proposed methods achieve up to 9:5× speed-up, keeping less than 1% impact in the results quality. / A demanda crescente por computação energeticamente eficiente tem endossado o uso de Field- Programmable Gate Arrays para a criação de aceleradores de hardware para códigos grandes e complexos. Entretanto, a implementação de tais aceleradores envolve duas decisões complexas. O primeiro reside em decidir qual trecho de código é o melhor para se criar o acelerador, e o segundo reside em como implementar tal acelerador. Quando ambas decisões são consideradas concomitantemente, o problema se torna ainda mais complicado dado que a implementação do trecho de código afeta a seleção dos trechos de código, criando um espaço de projeto combinatorial a ser explorado. Dessa forma, uma exploração do espaço de projeto rápida para a implementação de aceleradores é crucial para habilitar a exploração de diferentes trechos de código. Contudo, tal exploração do espaço de projeto é impedida por várias tarefas que consumem tempo durante os passos de compilação a análise, o que faz da exploração de trechos de códigos inviável. Neste trabalho, focamos na implementação eficiente de aceleradores pipeline em hardware e apresentamos nossas contribuições para o aceleramento da criações de pipelines e de sua exploração do espaço de projeto. Referente à criação de pipelines, as abordagens propostas alcançam uma aceleração de até 100× quando comparadas às abordagens do estado-da-arte, levando à economia de 164 horas em uma exploração de espaço de projeto completa com menos de 1% de impacto na qualidade dos resultados. Referente à exploração do espaço de projeto, as abordagens propostas alcançam uma aceleração de até 9:5×, mantendo menos de 1% de impacto na qualidade dos resultados.

Ce mémoire s’inscrit dans le contexte général de la continuité de service des convertisseurs multiniveaux, lors de la défaillance d’un de leurs composants de puissance. Les structures concernées sont les topologies suivantes, largement utilisées dans les applications industrielles : Neutral Point Clamped (NPC) et Neutral Point Piloted (NPP) ou T-Type. Dans un premier temps, afin de limiter le taux de pannes du convertisseur, une commande contribuant à l’accroissement de la durée de vie des composants de puissance est tout d’abord proposée. Pour se faire, nous minimiserons sur chaque période le nombre de commutations des composants commandables à l’ouverture et à la fermeture. Cette idée a pour origine le fait qu’un convertisseur multiniveaux permet de générer le même niveau de tension de sortie à partir de plusieurs séquences de commutations différentes. Le principe de la commande proposée sera développé de manière générale, puis appliqué aux cas de structures type « Pont en H » à 5 niveaux, de type NPP (ou T-Type) et NPC. Ensuite, nous étudierons la continuité de service en mode nominal d’un convertisseur « Pont en H » à 5 niveaux, de type NPP (ou T-Type), suite à la défaillance en circuit ouvert d’un composant de puissance. Nous proposerons tout d’abord un diagnostic du défaut, constitué d’une première étape de détection, suivie d’une localisation précise du composant défaillant. Une topologie originale de convertisseur à tolérance de pannes permettra de garantir la continuité de service du système, en modifiant sa commande en adéquation avec le composant défaillant localisé. Des architectures électroniques numériques reconfigurables basées sur des composants FPGA (Field Programmable Gate Array) seront dédiées au diagnostic et à la reconfiguration de la commande ; elles permettront d’atteindre des performances temporelles élevées. L’ensemble des résultats présentés dans ce mémoire sera validé par modélisation/simulation, puis expérimentalement sur un banc de test / This thesis deals with continuity of service of multilevel power converters, during the failure of one of their power components. The studied converter topologies are the following, widely used in industrial applications: Neutral Point Clamped (NPC) and Neutral Point Piloted (NPP) or T-Type. First, to reduce the failure rate of the converter, an advanced control is proposed ; it increases the lifetime of the power components by minimizing the number of switchings over a period. This idea is based on the fact that a multilevel converter makes possible to generate the same output voltage level from several different switching sequences. The principle of the proposed control will be developed in a general way. Then, it is applied to the cases of 5-level "H-bridge" topologies, NPP (or T-Type) and NPC. Then, the continuity of service in nominal mode is studied for a 5 level "H-brige" NPP (or T-Type) converter, when an open circuit failure occurs on a power component. We first propose a fault diagnosis, consisting in a fault detection step, followed by the location of the faulty component. Then, an original fault-tolerant converter topology will ensure the continuity of service of the system, by modifying the control according to the localized faulty component. Reconfigurable digital electronic architectures based on Field Programmable Gate Array (FPGA) components will be dedicated to the diagnosis and the reconfiguration of the control; they will perform high temporal performances. All the results presented in this paper are validated by modeling and simulation. Then, they are experimentally validated on a test bench

La radiothérapie externe représente une part importante du traitement conservateur du sein. Le calendrier classique consiste à délivrer une dose totale de 50 Gy en 25 fractions sur 5 semaines. Pour certaines catégories de femmes, une radiothérapie de 5 à 6 semaines, avec des transports longs et fréquents est parfois difficile à réaliser. La radiothérapie peropératoire (RIOP) permet de prévenir le risque de récidive locale dans le lit tumoral, et ne nécessite que quelques jours d’hospitalisation. Cette étude se concentre sur l’utilisation d'une source de rayons X miniaturisée de faible énergie (50kV). Après résection chirurgicale de la tumeur, un applicateur est inséré dans le lit tumoral et le système délivre une dose unique de 20 Gy à sa surface. Cependant, il n'y a pas de prescription personnalisée ni d'information sur la dose délivrée et ce point est contestable, car un texte officiel recommande une optimisation de la dose individuelle. Dans ce contexte, un calcul Monte Carlo permet d'évaluer avec précision la dose délivrée à la patiente en simulant le transport des particules. Cette thèse propose d'évaluer ce critère de dose absorbée le plus justement possible à partir d'une modélisation réaliste de la source de rayons X et de calculs de dose individuels à l'aide de simulations de Monte Carlo en prenant en compte les hétérogénéités tissulaires du sein. Des mesures dosimétriques in vivo viennent également confirmer les résultats de simulations. / External radiation therapy is an important part of breast conservative treatment. The conventional calendar is to deliver a total dose of 50 Gy in 25 fractions over 5 weeks. For certain categories of women, 5 to 6 weeks of radiotherapy, with long and frequent transport is sometimes difficult to achieve. Intra-operative radiotherapy (IORT) helps to prevent the risk of local recurrence in the tumor bed, and only requires a few days of hospitalization. This study focuses on the use of a miniaturized low energy X-ray source (50kV). After surgical resection of the tumor, an applicator is inserted into the tumor bed and the system delivers a single dose of 20 Gy on its surface. However, there is no custom prescription and this is questionable since an official text recommends optimizing the individual dose. In this context, a Monte Carlo calculation makes it possible to accurately assess the dose delivered to the patient by simulating the transport of particles. This thesis proposes to assess the absorbed dose criterion as accurately as possible from a realistic model of the X-ray source and individual dose calculations using Monte Carlo simulations taking into account the tissue heterogeneities of the breast. In vivo dosimetric measurements also confirm the results of simulations.

With the continued and successful scaling of CMOS, process, voltage, and temperature (PVT), variations are increasing with each technology generation. The process variability impacts all design goals like performance, power budget and reliability of circuits significantly, resulting in yield loss. Hence, variability needs to be modeled and cancelled out by design techniques during the design phase itself. This thesis addresses the variability issues in 65 nm CMOS, across the domains of process technology, device physics and circuit design, with an eventual goal of accurate modeling and prediction of propagation delay and power dissipation. We have designed and optimized 65 nm gate length NMOS/PMOS devices to meet the specifications of the International Technology Roadmap for Semiconductors (ITRS), by two dimensional process and device simulation based design. Current design sign-off practices, which rely on corner case analysis to model process variations, are pessimistic and are becoming impractical for nanoscale technologies. To avoid substantial overdesign, we have proposed a generalized statistical framework for variability-aware circuit design, for timing sign-off and power budget analysis, based on standard cell characterization, through mixed-mode simulations. Two input NAND gate has been used as a library element. Second order statistical hybrid models have been proposed to relate gate delay, static leakage power and dynamic power directly in terms of the underlying process parameters, using statistical techniques of Design Of Experiments - Response Surface Methodology (DOE-RSM) and Least Squares Method (LSM). To extend this methodology for a generic technology library and for computational efficiency, analytical models have been proposed to relate gate delays to the device saturation current, static leakage power to device drain/gate resistance characterization and dynamic power to device CV-characterization. The hybrid models are derived based on mixed-mode simulated data, for accuracy and the analytical device characterization, for computational efficiency. It has been demonstrated that hybrid models based statistical design results in robust and reliable circuit design. This methodology is scalable to a large library of cells for statistical static timing analysis (SSTA) and statistical circuit simulation at the gate level for estimating delay, leakage power and dynamic power, in the presence of process variations. This methodology is useful in bridging the gap between the Technology CAD and Design CAD, through standard cell library characterization for delay, static leakage power and dynamic power, in the face of ever decreasing timing windows and power budgets. Finally, we have explored the gate-to-source/drain overlap length as a device design parameter for a robust variability-aware device structure and demonstrated the presence of trade-off between performance and variability, both at the device level and circuit level.

In this work, programmable analog techniques using floating-gate transistors have been developed to design precision analog circuits, low-power signal processing primitives and adaptive systems that learn on-chip. Traditional analog implementations lack programmability with the result that issues such as mismatch are corrected at the expense of area. Techniques have been proposed that use floating-gate transistors as an integral part of the circuit of interest to provide both programmability and the ability to correct for mismatch. Traditionally, signal processing has been performed in the digital domain with analog circuits handling the interface with the outside world. Such a partitioning of responsibilities is inefficient as signal processing involves repeated multiplication and addition operations that are both very power efficient in the analog domain. Using programmable analog techniques, fundamental signal processing primitives such as multipliers have been developed in a low-power fashion while preserving accuracy. This results in a paradigm shift in signal processing. A co-operative analog/digital signal processing framework is now possible such that the partitioning of tasks between the analog and digital domains is performed in a power efficient manner. Complex signal processing tasks such as adaptive filtering that learn the weight coefficients are implemented by exploiting the non-linearities inherent with floating-gate programming. The resulting floating-gate synapses are compact, low-power and offer the benefits of non-volatile weight storage. In summary, this research involves developing techniques for improving analog circuit performance and in developing power-efficient techniques for signal processing and on-chip learning.

With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.

This thesis describes the design, fabrication and characterization of AlGaN/GaN Heterostructure Field E ect Transistors (HFETs) grown by a Metal Organic Chemical Vapor Deposition (MOCVD) on sapphire substrates. The objective of this research is to develop AlGaN/GaN power devices with high breakdown voltage (greater than 1 kV) and low turn-on resistance. Various characteristics such as current drive (Idss), transconductance (gm) and threshold voltage (Vth) have also been measured and the results have been discussed. Two major challenges with the development of high breakdown voltage AlGaN/GaN HFETs in the past have been high material defect density and non-optimized fabrication technologies which gives rise to bu er leakage and surface leakage, respectively. In this thesis, mesa isolation, ohmic and gate metal contacts, and passivation techniques, have been discussed to improve the performance of these power transistors in terms of low contact resistance and low gate leakage. The relationship between breakdown voltage and Rds(ON)A with respect to the gate-drain length (Lgd) is also discussed. First, unit cell devices were designed (two-fingered cells with Wg = 100, 300, 400 m) and characterized, and then they were extended to form large area devices (upto Wg = 40 mm). The design goals were classied into three parts: - High Breakdown Voltage: This was achieved by designing devices with variations in Lgd, - Low turn-on resistance: This was achieved by optimizing the annealing temperatures as well as incorporating additional thick metal pads, as well as optimizing the passivation etch recipe, - Low Gate Leakage: The gate leakage was reduced signicantly by using a gate metal with a larger barrier height. All devices with Lgd larger than 10 m exhibited excellent breakdown voltage characteristics of over 800 V, and it progressed as the Lgd increased. The turn-on resistance was also reduced signicantly below 20 m-cm2, for devices with Lgd = 15, 25, and 20 m. The gate leakage was measured for all devices upto 200 V, and was in the range of 10-100 nA, which is one of the best values reported for multi-ngered devices with Lgd in the range of 2.4-5 mm. Some of the key challenges faced in fabrication were determining a better gate metal layer to reduce gate leakage, optimizing the passivation via etch recipe, and reducing surface leakage.