Une nouvelle méthode de test pour les convertisseurs ADC et DAC embarqués dans un système complexe a été développée en prenant en compte les nouvelles contraintes affectant le test. Ces contraintes, dues aux tendances de design de systèmes, sont un nombre réduit de point d'accès aux entrées/sorties des blocs analogiques du système et une augmentation galopante du nombre et des performances des convertisseurs intégrés. La méthode proposée consiste à connecter les convertisseurs DAC et ADC dans le domaine analogique pour n'avoir besoin que d'instruments de test numériques pour générer et capturer les signaux de test. Un algorithme de traitement du signal a été développé pour discriminer les erreurs des DACs et ADCs. Cet algorithme a été validé par simulation et par expérimentation sur des produits commercialisés par NXP. La dernière partie de la thèse a consisté à développer de nouvelles applications pour l'algorithme.

Submitted by Gilvanedja Silva (gilvanedja@biblioteca.ufpb.br) on 2018-03-22T20:42:08Z No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) / Made available in DSpace on 2018-03-22T20:42:09Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 11929036 bytes, checksum: e796f3e04cbf0cf6da3fa9648d4f9270 (MD5) Previous issue date: 2017-05-25 / This work presents a technique using carrier-based pulse width modulation (PWM) applied to single-phase asymmetrical multilevel inverters with diodes clamped, aiming to increase the amount of output voltage levels to improve signal quality, reducing the total harmonic distortion rate (THD). The technique was used in inverters of three, four and five levels per arm, providing an output signal with seven, thirteen and nineteen levels respectively, presenting two, six and ten levels higher than the equivalent symmetrical multilevel inverters. The technique was described with a set of equations and procedures that can be generalized for inverters of any number of levels. To verify the operation, simulations were performed using the PSIM program and an experimental assembly of an asymmetrical multilevel inverter of three levels was performed, using a field programmable gate array device (FPGA) in the implementation of the PWM modulator. Finally, the simulation and experimental results that prove the effectiveness of the modulation strategy employed in this work are presented and compared / Este trabalho apresenta uma técnica utilizando a modulação por largura de pulso (PWM) baseada em portadora, aplicada aos inversores multiníveis monofásicos assimétricos com diodos de grampeamento, com o objetivo de elevar a quantidade de níveis na tensão de saída, para melhorar a qualidade do sinal, reduzindo a taxa de distorção harmônica total (THD). A técnica foi empregada em inversores de três, quatro e cinco níveis por braço, fornecendo um sinal de saída com sete, treze e dezenove níveis respectivamente, apresentando dois, seis e dez níveis a mais que os inversores multiníveis simétricos equivalentes. A técnica foi descrita com um conjunto de equações e procedimentos que pode ser generalizada para inversores de qualquer número de níveis. Para comprovar o funcionamento, foram realizadas simulações utilizando o programa PSIM e efetuada montagem experimental de uma inversor multinível assimétrico de três níveis, utilizando na implementação do modulador PWM um dispositivo em matriz de porta programável em campo (FPGA). Por fim, são apresentados e comparados os resultados de simulações e experimentais que comprovam a eficácia da estratégia de modulação empregada neste trabalho

Este trabalho apresenta a análise e o desenvolvimento experimental de uma estrutura topológica de retificador híbrido trifásico que oferece as características operacionais de imposição de correntes de linha de entrada senoidais, de alto fator de potência, de reduzida distorção harmônica total de corrente e de fornecimento de um barramento CC com tensão regulada utilizando a inovadora técnica de Compensação Série de Tensão no Barramento CC tanto para condições normais de suprimento da rede elétrica como para condições de afundamentos temporários de tensão equilibrados e desequilibrados na rede CA. Para corroborar com a teoria exposta e com as análises de simulação computacional, um protótipo de 5 kW foi construído e ensaios experimentais realizados em laboratório permitiram demonstrar que para condições normais de suprimento da rede CA a solução proposta assegura distorções harmônicas de corrente na ordem de 2% e um fator de potência por fase próximo do valor unitário (0,996), além de ser capaz de regular e manter a tensão no barramento CC constante mesmo durante o transitório provocado por um degrau de carga de alta potência. Durante a ocorrência de afundamentos de tensão, a estrutura é capaz de regular a tensão do barramento CC no valor de referência estabelecido, assegurando elevado fator de potência mesmo durantes estes distúrbios da rede CA de alimentação. Destaca-se que estas características operacionais, além de serem alcançadas com os conversores chaveados que compõem a estrutura processando apenas uma parcela da potência total de saída, tornando o conjunto mais eficiente e robusto, fazem da estrutura proposta uma excelente alternativa para aplicações com elevados níveis de potência envolvendo a alimentação de cargas CC sensíveis aos distúrbios provocados pela rede CA e para aplicações que compreendem a compensação de oscilações de tensão devido às intermitências dos sistemas de microgeração que compõem as redes de distribuição em corrente contínua das microrredes. / This work presents the analysis and the experimental development of a topological structure of three-phase hybrid rectifier, which provides operational characteristics for imposing sinusoidal input line currents, with high power factor, low current total harmonic distortion and providing a DC bus with regulated voltage using the innovative technique of Series Voltage Compensation in the DC Bus for both normal conditions of mains power supply and for temporary sags for balanced and unbalanced voltage ac power supply conditions. In order to corroborate the exposed theory and with computational simulation analysis, a 5 kW prototype was assembled and experimental tests were conducted in laboratory. The results demonstrated that under normal conditions of AC mains supply the proposed solution ensures harmonic distortions about 2 % for the input AC currents and a power factor per phase approximately unitary (0.996). Moreover, the prototype can regulate and maintain the DC bus voltage in a constant value even during the transient caused by a high-power load step. During the occurrence of voltage sags, the structure can regulate the DC bus voltage in the established reference value, ensuring high power factor even during AC mains power supply disturbances. One can emphasize that these operational characteristics, in addition of being achieved with the switched converters that comprise the structure processing only an amount of the total output power, was observed that the whole assembly is more efficient and robust. The proposed structure is an excellent alternative for supplying high power DC loads sensitive to disturbances caused by AC mains and for applications involving voltage oscillations compensation due to intermittences of microgeneration systems that are connected to DC distribution of microgrids. / Tese (Doutorado)

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

This Master’s thesis deals with design of a new method for voltage quality benchmarking using voltage quality index. This index should determinate total voltage quality in the power grid and compare voltage quality in different places. There is design of several algorithms which value measured parameters in this thesis. The best suitable algorithm is selected. Program for this algorithm was compiled in GUI Matlab. The algorithm is verified by using measured parameters in this program. The last part of this thesis is focused on possible usage of created algorithm.

The presented dissertation thesis deals with a novel structure of delta-sigma () modulator which compensates influence of higher harmonic distortion and therefore it is possible to achieve high resolution up to 16 bits. This novel proposed structure combines advantages of one bit quantizer modulators with mutli-bit modulators. The novel second order structure is presented, correct function is verified in MATLAB simulation enviroment and requirements for partial block are studied. The second part of the work deals with design of converter with novel structure of modulator using switched capacitor technique utilizing ONSemi I3T25 technology. Advantages and disadvantages of the novel structure are evaluated and novel structure is compared with common structures of modulators.

Småskalig vattenkraft är en stor användare av reaktiv effekt då de ofta har asynkrongeneratorer. Det gör att det finns ett reellt behov för faskompensering, dels för att minska distorsion i nätet samt för att förbättra deras ekonomiska ställning, då elbolag ofta tar ut en avgift för överskridande användning av reaktiv effekt. Det ligger också i allmänhetens intresse att ha en god elkvalitet och hålla störningar och avbrott nere, vilket kan erhållas med faskompensering och filtrering av övertoner. Det finns olika tekniker för faskompensering med sina respektive för- och nackdelar som specificeras efter anläggningens krav och förhållanden. Dessa tekniker är ett kondensatorbatteri, passiv och aktiv reglering, övermagnetiserad synkronmaskin, static var compensator (SVC) och static synchronous compensator (STATCOM). Med hjälp av simuleringar och ekonomisk kalkylering har deras egenskaper och investeringspotential analyserats. Det har resulterat i att ett kondensatorbatteri är en ekonomiskt god investering men med nackdelen att det blir en stor transient vid inkoppling. Aktiv reglering bistår med en snabb, kontinuerlig faskompensering men har större driftkostnader och en kortare livslängd. Övermagnetiserad synkronmaskin har en god ekonomisk framtidsutsikt men med en något långsammare reaktionstid. SVC och STATCOM är mer applicerbar på större anläggningar, eller för nät som har en större nytta av dess flexibilitet. / Small scale hydropower is a big user of reactive power, mainly because of their use of asynchrounous generators. Power companies are charging their customers a fee for an extensive use of reactive power. Which gives rise to a need of correction of the power factor as well as reduction of distorsion in the network. It is also in the interest of the general public to acquire a good electric quality in terms of keeping distorsion and interruptions in the network to a minimum. This can be achieved by using different methods for power factor correction and filtration of harmonics. These methods have their own inherent advantages and disadvantages described after the facility’s specific needs and requirements. These methods are a capacitor bank, passive and active regulation, overexcited synchronous machine, static var compensator (SVC) and static synchronous compensator (STATCOM). Simulations and economical calculations have been used to determine these properties. A capacitor bank has been proven to be a good economical investment, but it has high transients during switching conditions. Active regulation also shows a good profitability and provides a fast, continuous regulation of the reactive power, though it has higher operating costs and low life expectancy. The overexcited synchronous generator has a positive outlook in economic terms, with the drawback of a slower response time. SVC and STATCOM are more applicable to larger facilities or weak networks.

This Diploma thesis deals with assessment of the influence of two fundamental types of resistance welders operation on chosen power quality parameters at the point of common coupling (PCC) of the power network. The assessed parameters of power quality are the total harmonic distortion of the supply voltage, asymmetry of the supply voltage and the level of short term flicker at the point of common coupling. The assessment is based on the comparison of the results of computer simulations done in PSCad 4.2.0 with the requirements of technical standards. The outcome of this thesis is the determination of allowable limits for physical and operation parameters for the general arrangement of a power distribution network and a resistance welder that should guarantee the power quality compliance.

Submitted by Maria Aparecida (cidazen@gmail.com) on 2017-04-17T13:14:17Z No. of bitstreams: 1 Elson Moreira.pdf: 7883984 bytes, checksum: cf59b3b0b24a249a7fd9e2390b7f16de (MD5) / Made available in DSpace on 2017-04-17T13:14:17Z (GMT). No. of bitstreams: 1 Elson Moreira.pdf: 7883984 bytes, checksum: cf59b3b0b24a249a7fd9e2390b7f16de (MD5) Previous issue date: 2017-02-10 / CNPQ / A problem of electric power quality that always affects the consumers of the distribution network are the harmonic distortions. Harmonic distortions arise from the presence of socalled harmonic sources, which are nonlinear equipment, i.e., equipment in which the voltage waveform differs from the current. Such equipment injects harmonic currents in the network generating distortions in the voltage waveform. Nowadays, the number of these equipment in the electrical network has increased considerably. However, the increasing use of such equipment over the network makes systems more vulnerable and prone to quality problems in the supply of electricity to consumers. In addition, it is important to note that in the current scenario, the generation of electricity from renewable sources, connected in the secondary distribution network, is increasing rapidly. This is mainly due to shortage and high costs of fossil fuels. In this context, the Photovoltaic Distributed Generation (PVDG), that uses the sun as a primary source for electric energy generation, is the main technology of renewable generation installed in distribution network. However, the PVDG is a potential source of harmonics, because the interface of the PVDG with the CA network is carried out by a CC/CA inverter, that is a highly nonlinear equipment. Thus, the electrical power quality problems associated with harmonic distortion in distribution networks tend to increase and be very frequent. One of the main indicators of harmonic distortion is the total harmonic distortion of voltage ( ) used by distribution utilities to limit the levels of harmonic distortion present in the electrical network. In the literature there are several deterministic techniques to estimate . These techniques have the disadvantage of not considering the uncertainties present in the electric network, such as: change in the network configuration, load variation, intermittence of the power injected by renewable distributed generation. Therefore, in order to provide a more accurate assessment of the harmonic distortions, this dissertation has as main objective to develop a probabilistic methodology to estimate the level of in secondary distribution networks considering the uncertainties present in the network and PVDG connected along the network. The methodology proposed in this dissertation is based on the combination of the following techniques: three-phase harmonic power flow in phase coordinate via method sum of admittance, point estimate method and series expansion of Gram-Charlier. The validation of the methodology was performed using the Monte Carlo Simulation. The methodology was tested in European secondary distribution network with 906 nodes of 416 V. The results were obtained by performing two case studies: without the presence of PVDG and with the PVDG connection. For the case studies, the following statistics for nodal were estimated: mean value, standard deviation and the 95% percentile. The results showed that the probabilistic estimation of is more complete, since it shows the variation of due to the uncertainties associated with harmonic sources and electric network. In addition, they show that the connection of PV-DG in the electric network significantly affects the levels of of the electric network. / Um problema de qualidade de energia elétrica que afeta os consumidores da rede de distribuição secundária são as distorções harmônicas. As distorções harmônicas são provenientes da presença das chamadas fontes de harmônicas que são equipamentos de características não-lineares, ou seja, equipamentos em que a forma de onda da tensão difere da de corrente. Tais equipamentos injetam correntes harmônicas na rede produzindo, portanto distorções na forma de onda da tensão. Nos dias atuais, a quantidade desses equipamentos na rede elétrica tem aumentado consideravelmente. Porém, o uso crescente desse tipo de equipamento ao longo da rede torna os sistemas mais vulneráveis e propensos a apresentarem problemas de qualidade no fornecimento de energia elétrica aos consumidores. Além disso, é importante destacar que no cenário atual, a geração de energia elétrica a partir de fontes renováveis, conectada na rede de distribuição secundária, está aumentando rapidamente. Isso se deve principalmente devido a escassez e altos custos dos combustíveis fosseis. Neste contexto, a Geração Distribuída Fotovoltaica (GDFV), que utiliza o sol como fonte primária para geração de energia elétrica, é a principal tecnologia de geração renovável instalada na rede de distribuição no Brasil. Contudo, a GDFV é uma potencial fonte de harmônica, pois a interface da GDFV com a rede CA é realizada por um inversor CC/CA, que é um equipamento altamente não-linear. Desde modo, os problemas de qualidade de energia elétrica associados à distorção harmônica nas redes de distribuição tendem a aumentar e a serem bem frequentes nos consumidores da rede de distribuição secundárias. Um dos principais indicadores de distorção harmônica é a distorção harmônica total de tensão ( do inglês “Total Harmonic Distortion of Voltage”) utilizada pelas concessionárias de energia elétrica para quantificar os níveis de distorção harmônica presentes na rede elétrica. Na literatura técnica existem várias técnicas determinísticas para estimar a . Essas técnicas possuem a desvantagem de não considerar as incertezas presentes na rede elétrica, tais como: mudança na configuração da rede, variação de carga e intermitência da potência injetada pela geração distribuída renovável. Portanto, a fim de fornecer uma avaliação mais precisa das distorções harmônicas, este trabalho tem como principal objetivo desenvolver uma metodologia probabilística para estimar o nível de em redes de distribuição secundária considerando as incertezas presentes na rede e na GDFV conectada ao longo da rede. A metodologia proposta nesta dissertação se baseia na combinação das seguintes técnicas: fluxo de potência harmônico trifásico em coordenadas de fase via método de soma de admitância, método de estimação por pontos e expansão em série de Gram-Charlier. Além disso, a validação da metodologia foi realizada utilizando a Simulação Monte Carlo. A metodologia desenvolvida foi testada na rede de distribuição secundária europeia com 906 nós de 416 V. Os resultados foram obtidos realizando dois casos de estudos: sem a presença de GDFV e com a conexão de GDFV. Para ambos os casos de estudo as seguintes estatísticas do nodal foram estimadas: valor médio, desvio padrão e o percentil de 95%. Os resultados demonstraram que a estimação probabilística da é mais completa, pois mostra a variação da devido às incertezas associadas com as fontes de harmônicas e as da rede elétrica. Os resultados também mostram que a conexão da GDFV afeta significativamente os níveis de da rede elétrica

Voltage source inverters (VSI) are popular in variable speed induction motor drive applications. Pulse width modulation (PWM) is employed to achieve variable voltage variable frequency output from a fixed DC bus voltage. The modulation method greatly influences the harmonic distortion in line current and the inverter switching loss. This thesis evaluates a few space vectorbased PWM techniques which reduce the harmonic distortion and/or the inverter switching loss, compared to conventional space vector PWM (CSVPWM), at a given average switching frequency. In space vector-based PWM, the average voltage vector applied over a sub-cycle equals the commanded reference vector, thereby maintaining voltsecond balance. The given average vector can be realized by applying the voltage vectors of the inverter in different sequences. CSVPWM employs a switching sequence in which all the phases switch once in a sub-cycle. Sequences, in which a phase is clamped, while the other two phases switch once in a sub-cycle have been reported in literature. Further, certain special switching sequences have also been reported recently. These special sequences involve switching a phase twice, while switching the second phase once and clamping the third phase in a sub-cycle. This work investigates the use of such special switching sequences to reduce line current distortion and inverter switching loss in an induction motor drive. The influence of various switching sequences on line current ripple and inverter switching loss is discussed in the thesis. Comparison of the sequences in terms of switching loss leads to a hybrid PWM technique, which deploys the best sequence to reduce switching loss under a given operating condition. This technique is referred to as minimum switching loss PWM (MSLPWM). Further, a procedure for design of hybrid PWM techniques to achieve reduced line current distortion as well as inverter switching loss is elaborated. Four such specially designed hybrid PWM techniques are discussed. Analytical methods are presented for the evaluation of total RMS harmonic distortion factor of line current and inverter switching loss corresponding to different PWM techniques. The MSLPWM and the hybrid PWM techniques are evaluated analytically in terms of harmonic distortion and switching loss. It is observed that the switching loss corresponding to MSLPWM is considerably less than that with CSVPWM over the entire range of power factor. The reduction in switching loss with MSLPWM is as high as 36% at high power factors close to unity, while it is not less than 22% at power factors close to zero. MSLPWM also reduces the harmonic distortion for power factors close to unity at high modulation indices. Compared to CSVPWM, the hybrid PWM techniques result in a maximum reduction of about 40% in the harmonic distortion at fundamental frequencies close to 50Hz, and about 30% reduction in switching loss at power factors close to unity. The various PWM techniques are tested on a constant V /f induction motor drive with a digital control platform based on ALTERA Cyclone II field programmable gate array (FPGA) device. With a 10kVA IGBT based inverter feeding a 2.2kW, 415V, 50Hz, three-phase induction motor, the total RMS harmonic distortion factor of line current (IT HD) is measured at different fundamental frequencies for the various PWM techniques. The average switching frequency is 2.44kHz. The measured values of IT HD show a reduction in distortion with the hybrid PWM techniques over CSVPWM at high speeds of the drive. The relative values of IT HD corresponding to different PWM techniques agree with the theoretical predictions. With the 10kVA IGBT based inverter feeding a 6kW, 400V, 50Hz, 4pole, three-phase induction motor, the switching losses corresponding to CSVPWM and MSLPWM are evaluated and compared. This is done by measuring the steady state temperature rise of the heat sink over the ambient for the two techniques under different conditions. The thermal measurements are carried out at different loads with power factor ranging from 0.14 to 0.77. The measurements are also carried out at different fundamental frequencies (or modulation indices). Further, to separate conduction (constant) losses and switching (variable) losses, the heat sink temperatures are measured at two different switching frequencies, namely 2.44kHz and 4.88kHz. It is observed that the temperature rise due to MSLPWM is less than that due to CSVPWM consistently under various operating conditions. The thermal measurements confirm the theoretical prediction of reduction in switching loss with MSLPWM. Measurements of heat sink temperature rise corresponding to CSVPWM, MSLPWM and the hybrid PWM techniques are carried out at a higher power factor of 0.98 (lag) with the inverter feeding an RL load (instead of an induction motor). The hybrid PWM and MSLPWM result in lower switching losses as indicated by the reduction in temperature rise.