La miniaturisation des transistors CMOS permet d'améliorer les performances, la densité d'intégration et le coût des circuits intégrés. Cependant, de nos jours, le transistor se heurte à des limitations physiques. Afin de perpétuer l'accroissement des performances, l'intégration de nouveaux matériaux devient incontournable. En particulier, l'oxyde d'hafnium, du fait de sa haute permittivité et de sa large bande interdite est largement étudié afin de remplacer l'oxyde de grille standard. L'utilisation du HfO2 vise ainsi à améliorer le compromis épaisseur d'oxyde/ courant de fuite. Dans ce contexte, ce travail porte sur l'élaboration, la caractérisation et l'intégration de films de HfO2 déposé par la technique MOCVD en phase liquide pulsée. La présence du système d'injection et l'utilisation d'une large fenêtre de procédé favorisent la croissance de films selon différentes phases cristallines. Selon la phase en présence, des constantes diélectriques de l'ordre de 20 et d'autres de l'ordre de 30 sont obtenues. Cette étude met aussi en évidence la présence d'une épaisseur de transition cristalline ainsi que la nature nano-cristallisée des films de HfO2. Ces différentes analyses ouvrent la voie à l'emploi de techniques de caractérisations non destructives qui peuvent être employées dans l'environnement salle blanche. L'ensemble de ces travaux ont permis la mise en place d'un procédé de référence, avec une EOT de 1,1 nm et une densité de courant de fuite de 0,84 A/cm², résultats en accord avec l'ITRS pour les applications haute performance

Si complementary metal-oxide-semiconductor (CMOS) technology has been prospered through continuously scaling of its feature size. As scaling is approaching its physical limitations, new materials and device structures are expected. High electron mobility III-V materials are attractive as alternative channel materials for future post-Si CMOS applications due to their outstanding transport property. High-k dielectrics/metal gate stack was applied to reduced gate leakage current and thus lower the power dissipation. Combining their benefits, great efforts have been devoted to explore III-V/high-k/metal metal-oxide-semiconductor field-effect-transistors (MOSFETs). The main challenges for III-V MOSFETs include interface issues of high-k/III-V, source and drain contact, silicon integration and reliability. A comprehensive study on III-V MOSFETs has been presented here focusing on three areas: 1) III-V/high-k/metal gate stack: material and electrical properties of various high-k dielectrics on III-V substrates have been systematically examined; 2) device architecture: device structures from planar surface channel MOSFETs and buried channel quantum well FETs (QWFETs) to 3D gate-wrapped-around FETs (GWAFETs) and tunneling FETs (TFETs) have been designed and analyzed; 3) fabrication process: process flow has been set up and optimized to build scaled planar and 3D devices with feature size down to 40nm. Potential of high performances have been demonstrated using novel III-V/high-k devices. Effective channel mobility was significantly improved by applying buried channel QWFET structure. Short channel effect control for sub-100nm devices was enhanced by shrinking gate dielectrics, reducing channel thickness and moving from 2D planar to 3D GWAFET structure. InGaAs TFETs have also been developed for ultra-low power application. This research work demonstrates that III-V/high-k/metal MOSFETs with superior device performances are promising candidates for future ultimately scaled logic devices. / text

The rapid progress of complementary-metal-oxide-semiconductor (CMOS) integrated circuit technology became feasible through continuous device scaling. The implementation of high-k/metal gates had a significantcontribution to this progress during the last decade. However, there are still challenges regarding the reliability of these devices. One of the main issues is the escalating 1/fnoise level, which leads to degradation of signal-to-noise ratio (SNR) in electronic circuits. The focus of this thesis is on low-frequency noise characterization and modeling of various novel CMOS devices. The devices include PtSi Schottky-barriers  for source/drain contactsand different high-kgatestacksusingHfO2, LaLuO3 and Tm2O3 with different interlayers. These devices vary in the high-k material, high-k thickness, high-k deposition method and interlayermaterial. Comprehensive electrical characterization and low-frequency noise characterization were performed on various devices at different operating conditions. The noise results were analyzed and models were suggested in order to investigate the origin of 1/f noise in these devices. Moreover, the results were compared to state-of-the-art devices. High constant dielectrics limit the leakage current by offering a higher physical dielectric thickness while keeping the Equivalent Oxide Thickness (EOT) low. Yet, the 1/f noise increases due to higher number of traps in the dielectric and also deterioration of the interface with silicon compared to SiO2. Therefore, in order to improve the interface quality, applying an interfacial layer (IL) between the high-k layer and silicon is inevitable. Very thin, uniform insitu fabricated SiO2 interlayers with HfO2 high-k dielectric have been characterized. The required thickness of SiO2 as IL for further scaling has now reached below 0.5 nm. Thus, one of the main challenges at the current technology node is engineering the interfacial layer in order to achieve both high quality interface and low EOT. High-k ILs are therefore proposed to substitute SiOx dielectrics to fulfill this need. In this work, we have made the first experiments on low-frequency noise studies on TmSiO as a high-k interlayer with Tm2O3 or HfO2 on top as high-k dielectric. The TmSiO/Tm2O3 shows a lower level of noise which is suggested to be related to smoother interface between the TmSiO and Tm2O3. We have achieved excellentnoise performancefor TmSiO/Tm2O3 and TmSiO/HfO2 gate stacks which are comparableto state-of-the-art SiO2/HfO2 gate stacks. / <p>QC 20151130</p>

The progress of the silicon-based complementary-metal-oxide-semiconductor (CMOS) technology is mainly contributed to the scaling of the individual component. After decades of development, the scaling trend is approaching to its limitation, and there is urgent needs for the innovations of the materials and structures of the MOS devices, in order to postpone the end of the scaling. Atomic layer deposition (ALD) provides precise control of the deposited thin film at the atomic scale, and has wide application not only in the MOS technology, but also in other nanostructures. In this dissertation, I study rapid thermal processing (RTP) treatment of thermally grown SiO2, ALD growth of SiO2, and ALD growth of high-k HfO2 dielectric materials for gate oxides of MOS devices. Using a lateral heating treatment of SiO2, the gate leakage current of SiO2 based MOS capacitors was reduced by 4 order of magnitude, and the underlying mechanism was studied. Ultrathin SiO2 films were grown by ALD, and the electrical properties of the films and the SiO2/Si interface were extensively studied. High quality HfO2 films were grown using ALD on a chemical oxide. The dependence of interfacial quality on the thickness of the chemical oxide was studied. Finally I studied growth of HfO2 on two innovative interfacial layers, an interfacial layer grown by in-situ ALD ozone/water cycle exposure and an interfacial layer of etched thermal and RTP SiO2. The effectiveness of growth of high-quality HfO2 using the two interfacial layers are comparable to that of the chemical oxide. The interfacial properties are studied in details using XPS and ellipsometry.

In der vorliegenden Arbeit wird die grundsätzliche Eignung von yttriumstabilisiertem Hafniumoxidschichten als neues Dielektrikum für Speicherkondensatoren in dynamischen Halbleiterspeichern (DRAM) untersucht. Bei diesem Werkstoff handelt es sich um einen high-k Isolator der neuen Generation mit großem anwendungstechnischem Potential zur Substitution der seit vier Jahrzehnten eingesetzten siliciumbasierten Materialien. Daraus abgeleitet ergibt sich die Aufgabenstellung einer umfassenden Charakterisierung der praxisrelevanten Eigenschaften der Oxidschicht, umfassend in dem Sinne, dass aus dem Ergebnis eine wissenschaftlich fundierte Beurteilung zu den Aussichten einer Überführung in die Produktion abgeleitet werden kann. Es wird aufgezeigt, dass der Wechsel zu high-k Isolatoren erhebliche technische Neuerungen voraussetzt und weitere Entwicklungsarbeit nötig ist. Zusammenfassend kann erstmals die Eignung der ALD-Technik zur Herstellung dünnster yttriumstabilisierter Hafniumoxidschichten und deren Verwendung als Isolatorwerkstoff in zukünftigen mikroelektronischen Speicherkondensatoren anhand einer umfangreichen und anwendungstechnisch fokussierten Mikrostrukturcharakterisierung nachgewiesen werden. / This thesis investigates the basic suitability of yttrium stabilized hafnium oxide as a new dielectric for storage capacitors in dynamic random access memory (DRAM) semiconductor devices. This material is a so-called high- insulator with high dielectric constant. It is a good candidate to replace the silicon-based materials that are used for four decades now. Therefore it is necessary to extensively investigate selected properties of the oxide material. Extensively in terms of significant results that enable or object the applicability for the production process. It shows that the shift to high-insulators requires significant technological innovations and that further development work is necessary. The suitability of the ALD technique for depositing thin films of yttrium oxide and hafnium oxide is identified. The suitability of yttrium stabilized hafnium oxide layers as a dielectric material in future microelectronic storage capacitors can be given for the first time.

Στην παρούσα Εργασία λεπτά υμένια (5 -25 nm) ZrO2 έχουν εναποτεθεί με τη μέθοδο ALD σε μη αδρανοποιημένο (100) Ge τύπου-p, με ειδική αντίσταση 0.2-0.5 Ω-cm. Η εναπόθεση του ZrO2 πραγματοποιήθηκε στους 2500C, με τη χρήση διαδοχικών παλμών H2O και Tetrakis (Dimethylamido) Zirconium που ήταν και οι πρόδρομες ενώσεις. Ο δομικός χαρακτηρισμός των υμενίων (στοιχειομετρία, σύνθεση και τραχύτητα της διεπιφάνειας, κρυσταλλογραφική φάση του διηλεκτρικού κλπ) πραγματοποιήθηκε μέσω των μεθόδων XPS και ΤΕΜ. Ο λεπτομερής ηλεκτρικός χαρακτηρισμός των υμενίων έγινε με παράμετρο τη θερμοκρασία σε δομές (πυκνωτές) MOS που έφεραν λευκόχρυσο, Pt, ως μέταλλο πύλης. Πραγματοποιήθηκαν μετρήσεις C-V, C-f με παράμετρο τη θερμοκρασία και για θερμοκρασίες από 300Κ έως 80 Κ. Σύμφωνα με τα αποτελέσματα που προέκυψαν από την παρούσα μελέτη τα υμένια με πάχος μικρότερο των 15 nm εμφανίζουν πολύ φτωχή ηλεκτρική συμπεριφορά, η οποία βελτιώνεται με την αύξηση του πάχους. Σχετικά παχιά (25 nm) υμένια ZrO2 εμφανίζουν πυκνότητα διεπιφανειακών παγίδων της τάξης των 1011 eV-1cm-2, όπως προκύπτουν από μετρήσεις που πραγματοποιήθηκαν στους 80K. Από μετρήσεις I-V με παράμετρο τη θερμοκρασία προκύπτουν οι μηχανισμοί αγωγιμότητας που διέπουν τις μελετούμενες δομές. Η επίδραση της ανόπτησης σε περιβάλλον Forming Gas μετά την εναπόθεση του μετάλλου μελετάται επίσης. Τέλος, μελετώνται οι ηλεκτρικές ιδιότητες δομών Pt/ZrO2 (25 nm)/p-Ge, σε υποστρώματα που περιέχουν ταυτόχρονα περιοχές που έχουν υποστεί ανόπτηση με Laser και περιοχές που δεν έχουν υποστεί ανόπτηση. Η ανόπτηση με Laser φαίνεται να υποβαθμίζει την ηλεκτρική συμπεριφορά της δομής. Ωστόσο, σύμφωνα με τα αποτελέσματα της παρούσας εργασίας, υπάρχουν ενδείξεις ότι οι δομές σε περιοχές που γειτνιάζουν με αυτές που έχουν υποστεί ανόπτηση με Laser εμφανίζουν βελτιωμένες ηλεκτρικές ιδιότητες ακόμη και σε σχέση με τα δείγματα αναφοράς που περιλαμβάνουν δομές που αναπτύχθηκαν σε μη ακτινοβολημένο υπόστρωμα. / In the present Thesis, thin (5 -25 nm) films of ZrO2 have been deposited by Atomic Layer Deposition (ALD) on non-passivated p-type (100) Germanium substrates with resistivity 0.2-0.5 Ω-cm. ZrO2 deposition has been performed at 2500C using a series of alternating pulses of H2O and Tetrakis(Dimethylamido) Zirconium, which were the deposition precursors. Structural characterization of the films in terms of stoichiometry, interface composition and roughness, crystallographic phase of the dielectric etc., has been performed using XPS and TEM analysis. Detailed electrical characterization [C-V, and C-f measurements] of the films as a function of temperature has been performed in MOS capacitors using Pt as gate metal. It has been observed that the electrical behaviour of the films is extremely poor in thickness range below 15 nm, while they show an improvement in higher thickness regime. Thick (25 nm) ZrO2 showed an interface trap density of the order of 1011 eV-1cm-2 extracted at 80K. The conductivity mechanisms of the structures are revealed by I-V measurement at various temperatures. Finally the effect of post-metallization annealing in Forming Gas ambient has been studied. In parallel the electrical properties of structures Pt/ZrO2 (25 nm)/p-Ge, on substrates containing simultaneously laser annealed and non-annealed areas has been studied. It has been obtained that laser annealing of the substrate deteriorates the electrical behaviour of the structure, while it seems that structures on the areas in proximity to the annealed ones revealed superior electrical properties as compared to the corresponding deposited on non-annealed (reference) samples.

Les semiconducteurs composés III-V, et en particulier l’InGaAs, sont considéréscomme une alternative attractive pour remplacer le Silicium (Si) habituellement utilisépour former le canal dans les dispositifs Métal-Oxide-Semiconducteur (MOS). Sa hautemobilité électronique et sa bande interdite modulable, des paramètres clés pourl’ingénierie de dispositifs à haute performance, ont fait de l’InGaAs un candidatprometteur. Cependant, la stabilité thermique et la chimie des interfaces desdiélectriques high-k sur InGaAs est beaucoup plus complexe que sur Si. Tandis que laplupart des études se concentrent sur diverses méthodes de passivation, telles que lacroissance de couches passivantes d’interface (Si, Ge, et Si/Ge) et/ou le traitementchimique afin d’améliorer la qualité de l’interface high-k/InGaAs, les phénomènes telsque la diffusion d’espèces atomiques provenant du substrat dus aux traitementsthermiques n’ont pas été étudiés attentivement. Les traitements thermiques liés auxprocédés d’intégration de la source (S) et du drain (D) induisent des changementsstructurels qui dégradent les performances électriques du dispositif MOS. Unecaractérisation adaptée des altérations structurelles associées à la diffusion d’élémentsdepuis la surface du substrat est importante afin de comprendre les mécanismes defaille. Dans ce travail, une analyse de la structure ainsi que de la stabilité thermiquedes couches TiN/ZrO2/InGaAs par spectroscopie de photoélectrons résolue en angle(ARXPS) est présentée. Grâce à cette méthode d’analyse non destructive, il a étépossible d’observer des effets subtils tels que la diffusion d’espèces atomiques àtravers la couche diélectrique due au recuit thermique. A partir de la connaissance dela structure des couches, les profils d’implantation d’In et de Ga ont pu être estiméspar la méthode des scenarios. L’analyse de l’échantillon avant recuit thermique apermis de localiser les espèces In-O et Ga-O à l’interface oxide-semiconducteur. Aprèsrecuit, les résultats démontrent de façon quantitative que le recuit thermique cause ladiffusion de In et Ga vers les couches supérieures. En considérant différents scénarios,il a pu être démontré que la diffusion d’In et de Ga induite par le recuit atteint lacouche de TiO2. Dans le cas où l’échantillon est recuit à 500 °C, seule la diffusion d’Inest clairement observée, tandis que dans le cas où l’échantillon est recuit à 700 °C, onobserve la diffusion d’In et de Ga jusqu’à la couche de TiO2. L’analyse quantitative~ viii ~montre une diffusion plus faible de Gallium (~ 0.12 ML) que d’Indium (~ 0.26 ML) à 700°C /10 s. L’analyse quantitative en fonction de la température de recuit a permisd’estimer la valeur de l’énergie d’activation pour la diffusion d’Indium à travers leZircone. La valeur obtenue est très proche des valeurs de diffusion de l’Indium àtravers l’alumine et l’hafnia précédemment rapportées. Des techniquescomplémentaires telles que la microscopie électronique en transmission à hauterésolution (HR-TEM), la spectroscopie X à dispersion d’énergie (EDX) et laspectrométrie de masse à temps de vol (TOF-SIMS) ont été utilisés pour corréler lesrésultats obtenus par ARXPS. En particulier, la TOF-SIMS a révélé le phénomène dediffusion des espèces atomiques vers la surface. / III-V compound semiconductors, in particular InGaAs, are considered attractivealternative channel materials to replace Si in complementary metal-oxidesemiconductor(MOS) devices. Its high mobility and tunable band gap, requirementsfor high performance device design, have placed InGaAs as a promising candidate.However, the interfacial thermal stability and chemistry of high-k dielectrics on InGaAsis far more complex than those on Si. While most studies are focused on variouspassivation methods, such as the growth of interfacial passivation layers (Si, Ge, andSi/Ge) and/or chemical treatments to improve the quality of high-k/InGaAs interface,phenomena such as the out-diffusion of atomic species from the substrate as aconsequence of the thermal treatments have not been carefully studied. The thermaltreatments, which are related with integration processes of source and drain (S/D),lead to structural changes that degrade the electrical performance of the MOS device.A proper characterization of the structural alterations associated with the out-diffusionof elements from the substrate is important for understanding failure mechanisms. Inthis work it is presented an analysis of the structure and thermal stability ofTiN/ZrO2/InGaAs stacks by angle-resolved x-ray photoelectron spectroscopy (ARXPS).Through a non-destructive analysis method, it was possible to observe subtle effectssuch as the diffusion of substrate atomic species through the dielectric layer as aconsequence of thermal annealing. The knowledge of the film structure allowed forassessing the In and Ga depth profiles by means of the scenarios-method. For the asdeposited sample, In-O and Ga-O are located at the oxide-semiconductor interface. Byassuming different scenarios for their distribution, it was quantitatively shown thatannealing causes the diffusion of In and Ga up to the TiO2 layer. For the sampleannealed at 500 °C, only the diffusion of indium was clearly observed, while for thesample annealed at 700 °C the diffusion of both In and Ga to the TiO2 layer wasevident. The quantitative analysis showed smaller diffusion of gallium (~ 0.12 ML) thanof indium (~ 0.26 ML) at 700 °C/10 s. Since the quantification was done at differenttemperatures, it was possible to obtain an approximate value of the activation energyfor the diffusion of indium through zirconia. The value resulted to be very similar topreviously reported values for indium diffusion through alumina and through hafnia.~ vi ~Complementary techniques as high resolution transmission electron microscopy (HRTEM),energy dispersive x-ray spectroscopy (EDX) and time of flight secondary ion massspectrometry (TOF-SIMS) were used to complement the results obtained with ARXPS.Specially, TOF-SIMS highlighted the phenomenon of diffusion of the substrate atomicspecies to the surface. / Compuestos semiconductores III-V, en particular InxGa1-xAs, son consideradosmateriales atractivos para reemplazar el silicio en estructuras metal-oxidosemiconductor(MOS). Su alta movilidad y flexible ancho de banda, requisitos para eldiseño de dispositivos de alto rendimiento, han colocado al InxGa1-xAs como uncandidato prometedor. Sin embargo, la estabilidad térmica en la interfazdieléctrico/InxGa1-xAs es mucho más compleja que aquella formada en la estructuraSiO2/Si. Mientras que la mayoría de los estudios se centran en diversos métodos depasivación tales como el crecimiento de las capas intermedias (Si, Ge y Si/Ge) y/otratamientos químicos para mejorar la calidad de la interfaz, fenómenos como ladifusión de las especies atómicas del sustrato como consecuencia del recocido no hansido cuidadosamente estudiados. Los tratamientos térmicos, los cuales estánrelacionados con los procesos de integración de la fuente y el drenador (S/D) en undispositivo MOSFET, conducen a cambios estructurales que degradan el rendimientoeléctrico de un dispositivo MOS. Una caracterización apropiada de las alteracionesestructurales asociadas con la difusión de los elementos del substrato hacia las capassuperiores es importante para entender cuáles son los mecanismos de falla en undispositivo MOS. En este trabajo se presenta un análisis de la estructura y laestabilidad térmica de la estructura TiN/ZrO2/InGaAs por la espectroscopía defotoelectrones por rayos X con resolución angular (ARXPS). A través de un método deanálisis no destructivo, fue posible observar efectos sutiles tales como la difusión delas especies atómicas del sustrato a través del dieléctrico como consecuencia delrecocido. El conocimiento detallado de la estructura permitió evaluar los perfiles deprofundidad para las componentes de In-O y Ga-O por medio del método deescenarios. Para la muestra en estado como se depositó, las componentes de In-O yGa-O fueron localizadas en la interfaz óxido-semiconductor. Después del recocido, semuestra cuantitativamente que éste causa la difusión de átomos de In y Ga hacia a lascapas superiores. Asumiendo diferentes escenarios para su distribución, se muestraque el recocido provoca la difusión de In y Ga hasta la capa de TiO2. Para la muestrarecocida a 500 °C, se observó claramente la difusión de indio, mientras que para lamuestra recocida a 700 °C tanto In y Ga difunden a la capa de TiO2. El análisis~ iv ~cuantitativo mostró que existe menor difusión de átomos de galio (0.12 ML) que deindio (0.26 ML) a 700 °C/10 s. Puesto que el análisis sobre la cantidad de materialdifundido se realizó a diferentes temperaturas, fue posible obtener un valoraproximado para la energía de activación del indio a través del ZrO2. El valor resultóser muy similar a los valores reportados previamente para la difusión de indio a travésde Al2O3 y a través de HfO2. Con el fin de correlacionar los resultados obtenidos porARXPS, se emplearon técnicas complementarias como la microscopía electrónica detransmisión (TEM), la espectroscopía de energía dispersiva (EDX) y la espectrometríade masas de iones secundarios por tiempo de vuelo (SIMS-TOF). Particularmente, TOFSIMSdestacó el fenómeno de difusión de las especies atómicas sustrato hacia lasuperficie.

Design of systems in the low-end nanometer domain has introduced new dimensions in power consumption and dissipation in CMOS devices. With continued and aggressive scaling, using low thickness SiO2 for the transistor gates, gate leakage due to gate oxide direct tunneling current has emerged as the major component of leakage in the CMOS circuits. Therefore, providing a solution to the issue of gate oxide leakage has become one of the key concerns in achieving low power and high performance CMOS VLSI circuits. In this thesis, a new approach is proposed involving dual dielectric of dual thicknesses (DKDT) for the reducing both ON and OFF state gate leakage. It is claimed that the simultaneous utilization of SiON and SiO2 each with multiple thicknesses is a better approach for gate leakage reduction than the conventional usage of a single gate dielectric (SiO2), possibly with multiple thicknesses. An algorithm is developed for DKDT assignment that minimizes the overall leakage for a circuit without compromising with the performance. Extensive experiments were carried out on ISCAS'85 benchmarks using 45nm technology which showed that the proposed approach can reduce the leakage, as much as 98% (in an average 89.5%), without degrading the performance.

In der vorliegenden Arbeit wird die grundsätzliche Eignung von yttriumstabilisiertem Hafniumoxidschichten als neues Dielektrikum für Speicherkondensatoren in dynamischen Halbleiterspeichern (DRAM) untersucht. Bei diesem Werkstoff handelt es sich um einen high-k Isolator der neuen Generation mit großem anwendungstechnischem Potential zur Substitution der seit vier Jahrzehnten eingesetzten siliciumbasierten Materialien. Daraus abgeleitet ergibt sich die Aufgabenstellung einer umfassenden Charakterisierung der praxisrelevanten Eigenschaften der Oxidschicht, umfassend in dem Sinne, dass aus dem Ergebnis eine wissenschaftlich fundierte Beurteilung zu den Aussichten einer Überführung in die Produktion abgeleitet werden kann. Es wird aufgezeigt, dass der Wechsel zu high-k Isolatoren erhebliche technische Neuerungen voraussetzt und weitere Entwicklungsarbeit nötig ist. Zusammenfassend kann erstmals die Eignung der ALD-Technik zur Herstellung dünnster yttriumstabilisierter Hafniumoxidschichten und deren Verwendung als Isolatorwerkstoff in zukünftigen mikroelektronischen Speicherkondensatoren anhand einer umfangreichen und anwendungstechnisch fokussierten Mikrostrukturcharakterisierung nachgewiesen werden.:Kurzbeschreibung Abstract Abkürzungen und Symbole 1. Einleitung 1.1. Motivation 1.2. DRAM-Technik 1.3. Ziel der Arbeit 2. Grundlagen 2.1. Isolatorschichten mit hoher dielektrischer Konstante 2.2. Hafniumbasierte Isolatorschichten 2.3. Weitere elektrische Kenngrößen 2.3.1. Ladungsträgertransport in Isolatoren 2.3.2. Elektrische Zuverlässigkeit 2.4. Atomlagenabscheidung 2.4.1. Grundlagen der Atomlagenabscheidung 2.4.2. Abscheidung in Strukturen mit hohem Aspektverhältnis 2.5. Eigenspannungen 3. Experimentelle Methodik 3.1. Substrate und Schichtabscheidung 3.2. Wärmebehandlung 3.2.1. Muffelofen mit Quarzglasrohr 3.2.2. Schnelle thermische Bearbeitung 3.2.3. Wärmebehandlung unter Vakuum 3.3. Präparation der Proben für die Transmissionselektronenmikroskopie . 3.4. Physikalische Analysemethoden 3.4.1. Röntgenbeugung und -reflektometrie 3.4.2. Mikroskopische Verfahren 3.4.3. Spektroskopische Verfahren 3.4.4. Substratkrümmungsmessung 3.4.5. Elektrische Messverfahren 3.4.6. Weitere Methoden 4. Ergebnisse und Diskussion 4.1. Mikrostruktur ebener Hf-Y-O-Schichten 4.1.1. Schichtwachstum 4.1.2. Rauheit und Dichte 4.1.3. Elementzusammensetzung 4.1.4. Kristallinität 4.1.5. Kristallphasen 4.1.6. Schichteigenspannungen 4.1.7. Linearer thermischer Ausdehnungskoeffizient und biaxialer Modul 4.1.8. Grenzfläche zum Substrat und der TiN-Elektrode 4.1.9. Zusammenfassung 4.2. Mikrostruktur in beschichteten Löchern mit hohem Aspektverhältnis 4.2.1. Schichtdicke als Funktion der Lochtiefe 4.2.2. Mikrostruktur und Grenzfläche 4.2.3. Modellierung der Bedeckungstiefe 4.2.4. Zusammenfassung 4.3. Einfluss der Mikrostruktur auf die elektrischen Eigenschaften 4.3.1. C-V und I-V Messungen 4.3.2. CAFM-Messungen 4.3.3. Zusammenfassung 5. Zusammenfassung und Ausblick A. Anhang A.1. Probenherstellung A.1.1. Probenbezeichnung A.1.2. Datenerfassung, Archivierung A.1.3. Probenliste A.1.4. Beschichtungsablauf für Hf-Y-Mischoxidschichten A.2. Wärmebehandlung A.3. C-V- und I-V-Messungen B. Veröffentlichungsliste C. Danksagung D. Literaturverzeichnis E. Stichwortverzeichnis / This thesis investigates the basic suitability of yttrium stabilized hafnium oxide as a new dielectric for storage capacitors in dynamic random access memory (DRAM) semiconductor devices. This material is a so-called high- insulator with high dielectric constant. It is a good candidate to replace the silicon-based materials that are used for four decades now. Therefore it is necessary to extensively investigate selected properties of the oxide material. Extensively in terms of significant results that enable or object the applicability for the production process. It shows that the shift to high-insulators requires significant technological innovations and that further development work is necessary. The suitability of the ALD technique for depositing thin films of yttrium oxide and hafnium oxide is identified. The suitability of yttrium stabilized hafnium oxide layers as a dielectric material in future microelectronic storage capacitors can be given for the first time.:Kurzbeschreibung Abstract Abkürzungen und Symbole 1. Einleitung 1.1. Motivation 1.2. DRAM-Technik 1.3. Ziel der Arbeit 2. Grundlagen 2.1. Isolatorschichten mit hoher dielektrischer Konstante 2.2. Hafniumbasierte Isolatorschichten 2.3. Weitere elektrische Kenngrößen 2.3.1. Ladungsträgertransport in Isolatoren 2.3.2. Elektrische Zuverlässigkeit 2.4. Atomlagenabscheidung 2.4.1. Grundlagen der Atomlagenabscheidung 2.4.2. Abscheidung in Strukturen mit hohem Aspektverhältnis 2.5. Eigenspannungen 3. Experimentelle Methodik 3.1. Substrate und Schichtabscheidung 3.2. Wärmebehandlung 3.2.1. Muffelofen mit Quarzglasrohr 3.2.2. Schnelle thermische Bearbeitung 3.2.3. Wärmebehandlung unter Vakuum 3.3. Präparation der Proben für die Transmissionselektronenmikroskopie . 3.4. Physikalische Analysemethoden 3.4.1. Röntgenbeugung und -reflektometrie 3.4.2. Mikroskopische Verfahren 3.4.3. Spektroskopische Verfahren 3.4.4. Substratkrümmungsmessung 3.4.5. Elektrische Messverfahren 3.4.6. Weitere Methoden 4. Ergebnisse und Diskussion 4.1. Mikrostruktur ebener Hf-Y-O-Schichten 4.1.1. Schichtwachstum 4.1.2. Rauheit und Dichte 4.1.3. Elementzusammensetzung 4.1.4. Kristallinität 4.1.5. Kristallphasen 4.1.6. Schichteigenspannungen 4.1.7. Linearer thermischer Ausdehnungskoeffizient und biaxialer Modul 4.1.8. Grenzfläche zum Substrat und der TiN-Elektrode 4.1.9. Zusammenfassung 4.2. Mikrostruktur in beschichteten Löchern mit hohem Aspektverhältnis 4.2.1. Schichtdicke als Funktion der Lochtiefe 4.2.2. Mikrostruktur und Grenzfläche 4.2.3. Modellierung der Bedeckungstiefe 4.2.4. Zusammenfassung 4.3. Einfluss der Mikrostruktur auf die elektrischen Eigenschaften 4.3.1. C-V und I-V Messungen 4.3.2. CAFM-Messungen 4.3.3. Zusammenfassung 5. Zusammenfassung und Ausblick A. Anhang A.1. Probenherstellung A.1.1. Probenbezeichnung A.1.2. Datenerfassung, Archivierung A.1.3. Probenliste A.1.4. Beschichtungsablauf für Hf-Y-Mischoxidschichten A.2. Wärmebehandlung A.3. C-V- und I-V-Messungen B. Veröffentlichungsliste C. Danksagung D. Literaturverzeichnis E. Stichwortverzeichnis

We present a comprehensive investigation of the low-¯eld hole mobility in strained Ge and III-V (GaAs, GaSb, InSb and In1¡xGaxAs) p-channel inversion layers with both SiO2 and high-· insulators. The valence (sub)band structure of Ge and III-V channels, relaxed and under strain (tensile and compressive) is calculated using an effcient self-consistent method based on the six-band k ¢ p perturbation theory. The hole mobility is then computed using the Kubo-Greenwood formalism accounting for non-polar hole-phonon scattering (acoustic and optical), surface roughness scatter- ing, polar phonon scattering (III-Vs only), alloy scattering (alloys only) and remote phonon scattering, accounting for multi-subband dielectric screening. As expected, we find that Ge and III-V semiconductors exhibit a mobility significantly larger than the \universal" Si mobility. This is true for MOS systems with either SiO2 or high-k insulators, although the latter ones are found to degrade the hole mobility compared to SiO2 due to scattering with interfacial optical phonons. In addition, III-Vs are more sensitive to the interfacial optical phonons than Ge due to the existence of the substrate polar phonons. Strain { especially biaxial tensile stress for Ge and biaxial compressive stress for III-Vs (except for GaAs) { is found to have a significant beneficial effect with both SiO2 and HfO2. Among strained p-channels, we find a large enhancement (up to a factor of 10 with respect to Si) of the mobility in the case of uniaxial compressive stress added on a Ge p-channel similarly to the well-known case of Si. InSb exhibits the largest mobility enhancement. In0:7Ga0:3As also exhibits an increased hole mobility compared to Si, although the enhancement is not as large. Finally, our theoretical results are favorably compared with available experimental data for a relaxed Ge p-channel with a HfO2 insulator.