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<div>Power electronic converters are being used in a variety of applications, from electric vehicles to the utility grid. These converters are designed to offer high efficiency, which is achieved by switching semiconductor devices between on or off states at a high frequency. Associated with this switching is a common-mode voltage. The high-frequency components in this voltage excite the parasitic capacitances in the system, resulting in the flow of common-mode current. Since this current completes its path through an unintended path, it can interfere with the functioning of other devices or equipment. One way to reduce the CM current in a system is through the use of passive components. These include strategically placed capacitors and common-mode inductors to limit the impact of the common-mode quantities. </div><div><br></div><div>While the design of common-mode inductors has been set forth in the literature, the effect of magnetic hysteresis in the core has been inappropriately ignored. This phenomenon becomes increasingly important when the allowable common-mode current is significantly smaller than the differential-mode current, such as in high-power converters.</div><div><br></div><div>In this work, passive mitigation of common-mode current in three-phase two-level voltage-source-inverter based systems is considered. A mitigation strategy is proposed and described. The components used in this strategy, namely a common-mode inductor and a proposed common-mode shorting network, are introduced. This is followed by a discussion on the time domain hysteresis modeling that facilitates the magnetic design of a common-mode inductor. The issue of self-capacitance of a common-mode inductor is then addressed. Then, a rigorous multi-objective optimization-based design methodology for a common-mode inductor which addresses magnetic hysteresis at a fundamental level is set forth. </div><div><br></div><div>This is followed by a discussion of a new tool in common-mode current mitigation, a proposed common-mode shorting network. A design strategy for this component is also set forth. The dissertation concludes with two experimental system demonstrations of the proposed strategy and components on laboratory test systems.</div>

<p>The phenomenon of image blurring on laser-printed or electro-photocopied paper has been discovered since the 1980s. In the 1990s, the problem was confirmed to be associated with the undesired surface conduction along the unique photoconductive polymer surface during the photoconduction process. Other than this, little progress has been made in investigating this phenomenon, due to the limited experimental techniques.</p> <p>In this thesis, the electrical properties of a commercially available photoconductor as a result of Corona charging were studied. Various techniques including vacuum deposition and step-function impedance spectroscopy were employed, to overcome the nature of the photoconductor that prevented the use of conventional techniques such as AC impedance spectroscopy. Negative dielectric constant (NDC) has been prevalently discovered at a broad range of frequencies (below 1Hz and up to 1 MHz) and it was questioned in the form of a physically-impossible inductor. This precipitous sign switch of dielectric constant is found in various areas ranging from physics, chemistry, biology to electronics. The magnitude of the NDC decreased drastically with the decrease of electric field frequency. The system obeyed the proposed free-carrier plasma model with a resonance frequency at MHz level.</p> <p>Commercially available polymeric photoconducting materials showing NDC at extremely low frequency are expected to provide unusual scattering to electromagnetic waves and therefore demonstrate profound implications with reduced cost. It has paved the way for many applications such as inductors in integrated chips without bulky coils and provides an insight into a possible revolution in electronics and photonics.</p> / Doctor of Philosophy (PhD)

Today, every microprocessor is powered with a Voltage Regulator (VR), which is also known as a high current Point-of-Load converter (POL). These circuits are mostly constructed using discrete components, and populated on the motherboard. With this solution, the passive components such as inductors and capacitors are bulky. They occupy a considerable footprint on the motherboard. The problem is exacerbated with the current trend of reducing the size of all forms of portable computing equipment from laptop to netbook, increasing functionalities of PDA and smart phones. In order to solve this problem, a high power density POL needs to be developed. An integration solution was recently proposed to incorporate passive components, especially magnetic components, with active components in order to realize the needed power density for the POL. Today's discrete VR only has around 100W/in3 power density. The 3D integration concept is widely used for low current integrated POL. With this solution, a very low profile planar inductor is built as a substrate for the active components of the POL. By doing so, the POL footprint can be dramatically saved, and the available space is also fully utilized. This 3D integrated POL can achieve 300-1000W/in3 power density, however, with considerably less current. This might address the needs of small hand-held equipment such as PDA and Smart phone type of applications. It does not, however, meet the needs for such applications as netbook, laptop, desk-top and server applications where tens and hundreds of amperes are needed. So, although the high density integrated POL has been demonstrated at low current level, magnetic integration is still one of the toughest barriers for integration, especially for high current POL. In order to alleviate the intense thirst from the computing and telecom industry for high power density POL, the 3D integration concept needs be extended from low current applications to high current applications. The key technology for 3D integration is the low profile planar inductor design. Before this research, there was no general methodology to analyze and design a low profile planar inductor due to its non-uniform flux distribution, which is totally different as a conventional bulky inductor. A Low Temperature Co-fired Ceramic (LTCC) inductor is one of the most promising candidates for 3D integration for high current applications. For the LTCC inductor, besides the non-uniform flux, it also has non-linear permeability, which makes this problem even more complicated. This research focuses on penetrating modeling and design barriers for planar magnetic to develop high current 3D integrated POL with a power density dramatically higher than today's industry products in the same current level. In the beginning, a general analysis method is proposed to classify different low profile inductor structures into two types according to their flux path pattern. One is a vertical flux type; another one is a lateral flux type. The vertical flux type means that the magnetic flux path plane is perpendicular with the substrate. The lateral flux type means that the magnetic flux path plane is parallel with the substrate. This analysis method allows us to compare different inductor structures in a more general way to reveal the essential difference between them. After a very thorough study, it shows that a lateral flux structure is superior to a vertical flux structure for low profile high current inductor design from an inductance density point of view, which contradicts conventional thinking. This conclusion is not only valid for the LTCC planar inductor, which has very non-linear permeability, but is also valid for the planar inductor with other core material, which has constant permeability. Next, some inductance and loss models for a planar lateral flux inductor with a non-uniform flux are also developed. With the help of these models, different LTCC lateral flux inductor structures (single-turn structure and multi-turn structures) are compared systematically. In this comparison, the inductance density, winding loss and core loss are all considered. The proposed modeling methodology is a valuable extension of previous uniform flux inductor modeling, and can be used to solve other modeling problems, such as non-uniform flux transformer modeling. After that, a design method is proposed for the LTCC lateral flux inductor with non-uniform flux distribution. In this design method, inductor volume, core thickness, winding loss, core loss are all considered, which has not been achieved in previous conventional inductor design methods. With the help of this design method, the LTCC lateral flux inductor can be optimized to achieve small volume, small loss and low profile at the same time. Several LTCC inductor substrates are also designed and fabricated for the 3D integrated POL. Comparing the vertical flux inductor substrate with the lateral flux inductor substrate, we can see a savings of 30% on the footprint, and a much simpler fabrication process. A 1.5MHz, 5V to 1.2V, 15A 3D integrated POL converter with LTCC lateral flux inductor substrate is demonstrated with 300W/in3 power density, which has a factor of 3 improvements when compared to today's industry products. Furthermore, the LTCC lateral flux coupled inductor is proposed to further increase power density of the 3D integrated POL converter. Due to the DC flux cancelling effect, the size of LTCC planar coupled inductor can be dramatically reduced to only 50% of the LTCC planar non-coupled inductor. Compared to previous vertical flux coupled inductor prototypes, a lateral flux coupled inductor prototype is demonstrated to have a 50% core thickness reduction. A 1.5MHz, 5V to 1.2V, 40A 3D integrated POL converter with LTCC lateral flux coupled inductor substrate is demonstrated with 700W/in3 power density, which has a factor of 7 improvements when compared to today's industry POL products in the same current level. In conclusion, this research not only overcame some major academia problems about analysis and design for planar magnetic components, but also made significant contributions to the industry by successfully scaling the integrated POL from today's 1W-5W case to a 40W case. This level of integration would significantly save the cost, and valuable motherboard real estate for other critical functions, which may enable the next technological innovation for the whole computing and telecom industry. / Ph. D.

State-of-the-art silicon-based power supplies have reached a point of maturity in performance. Efficiency, power density, and cost are major trade-offs involved in further improvements. Most products are custom designed with significant non-recurrent engineering and manufacturing processes that are labor intensive. In particular, conventional magnetic components, including transformers and inductors, have largely remained the same for the past five decades. Those large and bulky magnetic components are major roadblocks toward an automated manufacturing process. In addition, there is no specific approach to reduce electromagnetic interference (EMI) in conventional practices. In certain cases, EMI filter design even requires a trial-and-error process. With recent advances in wide-bandgap (WBG) power semiconductor devices, namely, SiC and GaN, we have witnessed significant improvements in efficiency and power density, compared to their silicon counterparts. In a power factor correction (PFC) rectifier/inverter, the totem-pole configuration with critical conduction mode (CRM) operation to realize zero-voltage switching (ZVS) is deemed most desirable for a switching frequency 10 times higher than current practice. With a significantly higher operating frequency, the integration of inductors with embedded windings in the printed circuit board (PCB) is feasible. However, a PCB winding-based inductor has a fundamental limitation in terms of its power handling capability. The winding loss is proportional to the magnetomotive force (MMF), which is Ni. That is to say, with the number of layers (turns) and currents increased, winding loss is increased nonlinearly. Furthermore, for a large-size planar inductor, flux distribution is usually non-uniform, resulting in dramatically increased hysteresis loss and eddy loss. Thus, current designs are challenged by the capability to increase their power range. To address those issues, a modular building block approach is proposed in this dissertation. A planar PCB inductor is formed by an array of pillars that are integrated into one magnetic core, where each pillar handles roughly 750 W of power. The winding loss is reduced by limiting the number of turns for each pillar. The core loss is minimized with a proposed planar magnetic structure where rather uniformly distributed fluxes were observed in the plates. The proposed approach has a similar loss to a conventional litz wire-based design but features a higher power density and can be easily assembled in automation. A 3 kW high frequency PFC converter with 99% efficiency is demonstrated as an example. Furthermore, PCB-based designs up to 6 kW are provided. Another challenge in a WBG-based PFC/inverter is the high common-mode (CM) noises associated with the high dv/dt of the WBG devices. Symmetry and cancellation techniques are often employed to suppress CM noises in switching power converters. Meanwhile, shielding technique has been demonstrated to effectively suppress CM noises in an isolated converter with PCB-based transformer design. However, for non-isolated converters, such as PFC circuits, none of the techniques mentioned above are deemed applicable or justifiable. Recently, the balance technique has been demonstrated to effectively suppress CM noises up to a point where the parasitic ringing between the inductor and its winding capacitor is observed. This dissertation presents an improved balance technique in a PCB-based coupled inductor design that compensates for the detrimental effect of the interwinding capacitors. A CM noise model is established to simplify the convoluted couplings into a decoupled representation so as to illustrate the necessary conditions for realizing a balanced network. In the given 1 kW PFC example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. The parasitic oscillation of inductors, known to be detrimental for CM noise reduction, is circumvented with the improved magnetic structure. By applying the balance technique to a PFC converter and the shielding technique to an LLC DC/DC converter, significant noise reductions were realized. This provides the opportunity to use a simple one-stage EMI filter to achieve the required EMI noise attenuation for a server power supply. This dissertation further offers an in-depth study on reducing the unwanted near-field couplings between the CM/DM inductors and DM filter capacitors, as well as unwanted self-parasitics such as the ESL of the DM capacitors. An exhaustive finite element analysis (FEA) and near field measurements are conducted to better understand the effect of frequency on the polarization of the near field due to the displacement current. The knowledge gained in this study enables one to minimize unwanted mutual coupling effects by means of physical placement of these filter components. Thus, for the first time, a single-stage EMI filter is demonstrated to meet the EMI standard in an off-line 1 kW, 12 V server power supply. With the academic contributions in this dissertation, a PCB winding-based inductor can be successfully applied to a high-frequency PFC/inverter to achieve high efficiency, high power density, automation in manufacturing, lower EMI, and lower cost. Suffice it to say, the proposed approach enables a paradigm shift in the designing and manufacturing of a PFC/inverter for the next generation of power supplies. / Doctor of Philosophy / State-of-the-art silicon device-based switching power supplies have reached a point of maturity in performance. Efficiency, power density, and cost are major trade-offs involved in performance improvements. Most products are custom designed, requiring significant non-recurrent engineering and labor-intensive manufacturing processes. In particular, conventional magnetic components, including transformers and inductors, have largely remained the same for the past five decades. Those large and bulky magnetic components are major roadblocks toward an automated manufacturing process. In addition, there is no specific approach to reduce electromagnetic interference (EMI) in conventional practices. In consequence, a large multi-stage EMI filter is usually adopted between the power converter and the grid to reduce the EMI noise. It generally occupies 1/4-1/3 of the total converter volume. In certain cases, EMI filter design even requires a trial-and-error process. Suffice it to say, EMI is still regarded as both science and art. With recent advances in wide-bandgap (WBG) power semiconductor devices, namely, SiC and GaN, we have witnessed significant improvements in efficiency and power density, compared to their silicon counterparts. With GaN devices, the switching frequency of a PFC converter is able to be increased by 10 times compared to the state-of-the-art design without compromising efficiency. With a significantly higher operating frequency, the integration of inductors with embedded windings in the printed circuit board (PCB) is feasible. However, the state-of-the-art PCB winding-based inductor has a fundamental limitation in power range. Its winding loss and core loss increase dramatically in high powers. To address this issue, a modular building block approach is proposed in this dissertation. A planar PCB inductor is formed by an array of pillars that are integrated into one magnetic core, where each pillar handles roughly 750 W of power. The winding loss is reduced by limiting the number of turns for each pillar. The core loss is minimized with a proposed planar magnetic structure where rather uniformly distributed fluxes have been observed in the magnetic core plates. A 3 kW high-frequency PFC converter with a 99% peak efficiency is demonstrated as an example. Furthermore, PCB-based designs up to 6 kW are provided. Another challenge in a WBG-based PFC/inverter is the high common-mode (CM) noises caused by the high switching speed of the WBG devices. Symmetry and cancellation techniques are often employed to suppress CM noises in switching power converters. Meanwhile, shielding technique has been demonstrated to effectively suppress CM noises in an isolated converter with PCB-based transformer. However, for non-isolated converters, such as PFC circuits, none of the techniques mentioned above are deemed applicable or justifiable. Recently, the balance technique has been demonstrated to effectively suppress CM noises up to several MHz. However, the CM noise reduction is not effective beyond that. This dissertation presents an improved balance technique in a PCB-based coupled inductor to circumvent the limits. In the given 1 kW PFC example, CM noise suppression is effective in the frequency range of interest up to 30 MHz. By applying the balance technique to a PFC converter and the shielding technique to an LLC DC/DC converter, significant noise reductions were realized. This provides the opportunity to use a simple one-stage EMI filter to achieve the required EMI noise attenuation for a server power supply. It features a smaller volume compared to a conventional multi-stage filter. To further enhance the filter's performance at high frequencies, an exhaustive finite element analysis and near field measurements are conducted to better understand the effect of frequency on the polarization of the near field due to the displacement current. The knowledge gained in this study enables one to minimize unwanted mutual coupling effects through physical placement of these filter components. Several approaches for improving the filter performance at high frequency are conducted. With these approaches applied, a single-stage filter is demonstrated in an off-line 1 kW, 12 V server power supply. Thus, for the first time, a single-stage EMI filter can be contemplated to meet the EMI standard in server power supplies. With the academic contributions in this dissertation, a PCB-winding based inductor can be successfully applied to a high-frequency PFC/inverter to achieve high efficiency, high power density, automation in manufacturing, lower EMI, and lower cost. Suffice it to say, the proposed approach in this work enables a paradigm shift in the designing and manufacturing of a PFC/inverter for the next generation of power supplies.

Point-of-load (POL) converters are used extensively in IT products. Every piece of the integrated circuit (IC) is powered by a point-of-load (POL) converter, where the proximity of the power supply to the load is very critical in terms of transient performance and efficiency. A compact POL converter with high power density is desired because of current trends toward reducing the size and increasing functionalities of all forms of IT products and portable electronics. To improve the power density, a 3D integrated POL module has been successfully demonstrated at the Center for Power Electronic Systems (CPES) at Virginia Tech. While some challenges still need to be addressed, this research begins by improving the 3D integrated POL module with a reduced DCR for higher efficiency, the vertical module design for a smaller footprint occupation, and the hybrid core structure for non-linear inductance control. Moreover, as an important category of the POL converter, the voltage regulator (VR) serves an important role in powering processors in today's electronics. The multi-core processors are widely used in almost all kinds of CPUs, ranging from the big servers in data centers to the small smartphones in almost everyone's pocket. When powering multiple processor cores, the energy consumption can be reduced dramatically if the supply voltage can be modulated rapidly based on the power demand of each core by dynamic voltage and frequency scaling (DVFS). However, traditional discrete voltage regulators (VRs) are not able to realize the full potential of DVFS since they are not able to modulate the supply voltage fast enough due to their relatively low switching frequency and the high parasitic interconnect impedance between the VRs and the processors. With these discrete VRs, DVFS has only been applied at a coarse timescale, which can scale voltage levels only in tens of microseconds (which is normally called a coarse-grained DVFS). In order to get the full benefit of DVFS, a concept of an integrated voltage regulator (IVR) is proposed to allow fine-grained DVFS to scale voltage levels in less than a microsecond. Significant interest from both academia and industry has been drawn to IVR research. Recently, Intel has implemented two generations of very high frequency IVR. The first generation is implemented in Haswell processors, where air core inductors are integrated in the processor's packaging substrate and placed very closely to the processor die. The air core inductors have very limited ability in confining the high frequency magnetic flux noise generated by the very high switching frequency of 140MHz. In the second generation IVR in Broadwell processors, the inductors are moved away from the processor substrate to the 3DL PCB modules in the motherboard level under the die. Besides computers, small portable electronics such as smartphones are another application that can be greatly helped by IVRs. The smartphone market size is now larger than 400 billion US dollars, and its power consumption is becoming higher and higher as the functionality of smartphones continuously advances. Today's multi-phase VR for smartphone processors is built with a power management integrated circuit (PMIC) with discrete inductors. Today's smartphone VRs operate at 2-8MHz, but the discrete inductor is still bulky, and the VR is not close enough to the processor to support fine-grained DVFS. If the IVR solution can be extended to the smartphone platform, not only can the battery life be greatly improved, but the total power consumption of the smartphone (and associated charging time and charging safety issues) can also be significantly reduced. Intel's IVR may be a viable solution for computing applications, but the air core inductor with un-confined high-frequency magnetic flux would cause very severe problems for smartphones, which have even less of a space budget. This work proposes a three-dimensional (3D) integrated voltage regulator (IVR) structure for smartphone platforms. The proposed 3D IVR will operate with a frequency of tens of MHz. Instead of using an air core, a high-frequency magnetic core without an air gap is applied to confine the very high frequency flux. The inductor is designed with an ultra-low profile and a small footprint to fit the stringent space requirement of smartphones. A major challenge in the development of the very high frequency IVR inductor is to accurately characterize and compare magnetic materials in the tens of MHz frequency range. Despite the many existing works in this area, the reported measured properties of the magnetics are still very limited and indirect. In regards to permeability, although its value at different frequencies is often reported, its saturation property in real DC-biased working conditions still lacks investigation. In terms of loss property, the previous works usually show the equivalent resistance value only, which is usually measured with small-signal excitation from an impedance/network analyzer and is not able to represent the real magnetic core loss under large-signal excitation in working conditions. The lack of magnetic properties in real working conditions in previous works is due to the significant challenges in the magnetic characterization technique at very high frequencies, and it is a major obstacle to accurately designing and testing the IVR inductors. In this research, an advanced core loss measurement method is proposed for very high frequency (tens of MHz) magnetic characterization for the IVR inductor design. The issues of and solutions for the permeability and loss measurement are demonstrated. The LTCC and NEC flake materials are characterized and compared up to 40MHz for IVR application. Based on the characterized material properties, both single-phase and multi-phase integrated inductor are designed, fabricated and experimentally tested in 20MHz buck converters, featuring a simple single-via winding structure, small size, ultra-low profile, ultra-low DCR, high current-handling ability, air-gap-free magnetics, multi-phase integration within one magnetic core, and lateral non-uniform flux distribution. It is found that the magnetic core operates at unusually high core loss density, while it is thermally manageable. The PCB copper can effectively dissipate inductor heat with 3D integration. In addition, new GaN device drivers and magnetic materials are evaluated and demonstrated with the ability to increase the IVR frequency to 30MHz and realize a higher density with a smaller loss. In summary, this research starts with improving the 3D integrated POL module, and then explores the use of the 3D integration technique along with the very high frequency IVR concept to power the smartphone processor. The challenges in a very high frequency magnetic characterization are addressed with a novel core loss measurement method capable of 40MHz loss characterization. The very high frequency multi-phase inductor integrated within one magnetic component is designed and demonstrated for the first time. A 20MHz IVR platform is built and the feasibility of the concept is experimentally verified. Finally, new GaN device drivers and magnetic materials are evaluated and demonstrated with the ability to increase the IVR frequency to 30MHz and realize higher density with smaller loss. / Ph. D.

General-purpose step-down converter is essential in electronic system for processing energy from high-voltage rail to low-voltage circuits. The applications can be found at the auxiliary supplies in automobile, industrial and communication systems. Buck converter is a common circuit topology to fulfill step-down conversion, especially in low-power application since it is well-studied and straightforward. However, it suffers from low duty cycle under high step-down condition, and typically operates in continuous conduction mode (CCM) that generates large switching loss. On the other hand, as an extension of the buck converter, tapped-inductor (TI) buck converter has larger duty cycle while maintaining the structural simplicity. Therefore, the main objective of this thesis is to explore the potential of TI buck converter as a wide conversion range, high power density and high efficiency topology for low power application. To achieve high efficiency at switching frequency of MHz-level, synchronous conduction mode (SCM) is applied for turn-on losses elimination. The operation principle and power stage design of SCM TI buck is first introduced. The design of high switching frequency coupled inductor is emphasized since its size plays a critical role in power density. Loss breakdown is also provided to perform a comprehensive topological study. Secondly, detailed zero-voltage-switching (ZVS) condition of SCM TI buck is derived so that the converter does not experience redundant circulating energy. The experimental results of 15-W SCM TI buck converter prototypes are provided with 90.7% of peak power stage efficiency. The size of coupled inductor is down to 116 mm3. To enhance light-load efficiency, a variable frequency control scheme based on derived ZVS conditions is implemented with the switching frequency ranging from 2 MHz to 2.9 MHz. / Master of Science / General-purpose step-down converter is essential in electronic system for processing energy from high-voltage rail to low-voltage circuits. The applications can be found at the auxiliary supplies in automobile, industrial and communication systems. Typically, the ultimate goals of general-purpose step-down converter are versatility, high efficiency and compact size. Recently, tapped-inductor (TI) buck converter is studied since it could overcome the drawback of commonly used buck converter under high step-down conversion. Therefore, the potential of TI buck converter as a general-purpose step-down converter candidate is explored in this thesis, including control method, hardware design, etc. The thesis verifies that TI buck converter could have compact size while remaining efficient and adaptable.

Low-frequency vibrations typically occur in many practical structures and systems when in use, for example, in aerospaces and industrial machines. Piezoelectric materials feature compactness, lightweight, high integration potential, and permit to transduce mechanical energy from vibrations into electrical energy. Because of their properties, piezoelectric materials have been receiving growing interest during the last decades as potential vibration- harvested energy generators for the proliferating number of embeddable wireless sensor systems in applications such as structural health monitoring (SHM). The basic idea behind piezoelectric energy harvesting (PEH) powered architectures, or energy harvesting (EH) more in general, is to develop truly “fit and forget” solutions that allow reducing physical installations and burdens to maintenance over battery-powered systems. However, due to the low mechanical energy available under low-frequency conditions and the relatively high power consumption of wireless sensor nodes, PEH from low-frequency vibrations is a challenge that needs to be addressed for the majority of the practical cases. Simply saying, the energy harvested from low-frequency vibrations is not high enough to power wireless sensor nodes or the power consumption of the wireless sensor nodes is higher than the harvested energy. This represents a main barrier to the widespread use of PEH technology at the current state of the development, despite the advantages it may offer. The main contribution of this research work concerns the proposal of a novel EH circuitry, which is based on a whole-system approach, in order to develop enhanced PEH powered wireless sensor nodes, hence to compensate the existing mismatch between harvested and demanded energy. By whole-system approach, it is meant that this work develops an integrated system-of-systems rather than a single EH unit, thus getting closer to the industrial need of a ready- to-use energy-autonomous solution for wireless sensor applications such as SHM. To achieve so, this work introduces: Novel passive interfaces in connection with the piezoelectric harvester that permit to extract more energy from it (i.e., a complex conjugate impedance matching (CCIM) interface, which uses a PC permalloy toroidal coil to achieve a large inductive reactance with a centimetre- scaled size at low frequency; and interfaces for resonant PEH applications, which exploit the harvester‟s displacement to achieve a mechanical amplification of the input force, a magnetic and a mechanical activation of a synchronised switching harvesting on inductor (SSHI) mechanism). A novel power management approach, which permits to minimise the power consumption for conditioning the transduced signal and optimises the flow of the harvested energy towards a custom-developed wireless sensor communication node (WSCN) through a dedicated energy-aware interface (EAI); where the EAI is based on a voltage sensing device across a capacitive energy storage. Theoretical and experimental analyses of the developed systems are carried in connection with resistive loads and the WSCN under excitations of low frequency and strain/acceleration levels typical of two potential energy- autonomous applications, that are: 1) wireless condition monitoring of commercial aircraft wings through non-resonant PEH based on Macro-Fibre Composite (MFC) material bonded to aluminium and composite substrates; and wireless condition monitoring of large industrial machinery through resonant PEH based on a cantilever structure. shown that under similar testing conditions the developed systems feature a performance in comparison with other architectures reported in the literature or currently available on the market. Power levels up to 12.16 mW and 116.6 µW were respectively measured across an optimal resistive load of 66 277 kΩ for an implemented non-resonant MFC energy harvester on aluminium substrate and a resonant cantilever-based structure when no interfaces were added into the circuits. When the WSCN was connected to the harvesters in place of the resistive loads, data transmissions as fast as 0.4 and s were also respectively measured. By use of the implemented passive interfaces, a maximum power enhancement of around 95% and 452% was achieved in the two tested cases and faster data transmissions obtained with a maximum percentage improvement around 36% and 73%, respectively. By the use of the EAI in connection with the WSCN, results have also shown that the overall system‟s power consumption is as low as a few microwatts during non- active modes of operation (i.e., before the WSCN starts data acquisition and transmission to a base station). Through the introduction of the developed interfaces, this research work takes a whole-system approach and brings about the capability to continuously power wireless sensor nodes entirely from vibration-harvested energy in time intervals of a few seconds or fractions of a second once they have been firstly activated. Therefore, such an approach has potential to be used for real-world energy- autonomous applications of SHM.

The telecommunications market is one of the large rapidly growing fields in today’s power supply industry due to the increasing demand for telecom distributed power supply (DPS) systems. The half-bridge LLC (Inductor-Inductor-Capacitor) resonant converter is currently the most attractive topology for the design and implementation of 24V/48V DC telecom power converters. The current doubler rectifier (CDR) converter topology was invented and described in the early 1950s which can offer the unique characteristic of halving the output voltage while doubling the output current compared to a standard rectifier. In this thesis, the current doubler converter topology with its unique characteristic is evaluated as a complementary solution to improve the LLC resonant converter performance, especially for the low output voltage and high output current telecommunication applications. A novel half-bridge LLC resonant current doubler converter (LLC-CDR) is proposed in this thesis which can offer several performance benefits compared to conventional LLC-standard rectifier design . The unique characteristics of the LLC-CDR topology can offer significant improvements by transformation of a 48V converter into a 24V converter with the same power density. This thesis introduces a new SPICE-based simulation model to analyse the operation of this novel LLC-CDR converter circuit design. This model can be used to define the critical component parameters for the LLC -CDR circuit output inductor values. It can also be used to predict the circuit overall performance under different load conditions. Both time-domain based transient simulation analysis and frequency-domain based AC analysis provided by this simulation model showed favourable results in comparison to bench measurement results on a prototype. The model provides a valuable insight to reveal some of the unique characteristics of this LLC -CDR topology. It demonstrates a proof of concept that the conventional LLC resonant converter can be easily redesigned for low voltage, high current applications by using the LLC-CDR topology without requiring a new design for the LLC resonant stage components and the power transformer. A new magnetic integration solution was proposed to significantly improve the overall performance in the LLC-CDR topology that had not been published before. The LLC-CDR converter hardware prototypes with two output inductors coupled and uncoupled configurations were extensively modelled, constructed and bench tested.Test results demonstrated the suitability of an integrated coupled inductors design for the novel LLC-CDR converter application. The integrated coupled inductors design can significantly improve the LLC-CDR converter frequency-domain based AC simulation analysis results. In addition, these results also illustrate the potential benefit of how the magnetic integration design in general could reduce the magnetic component size, cost, and weight compared to the uncoupled inductors design. Finally, a hardware prototype circuit was constructed based on a commercial 1800 W single phase telecom power converter to verify the operation of this novel half bridge LLC-CDR topology. The converter prototype successfully operated at both no load and full load conditions with the nominal output voltage halved from 48VDC to 24VDC, and doubled the output current to match the same output power density. It also demonstrates that the efficiency of this novel half bridge LLC –CDR is 92% compares to 90% of EATON’s commercial 24VDC LLC resonant converter, which can fulfill the research goals.

<p>Tematika disertacije obuhvata projektovanje, izradu i karakterizaciju pasivnih induktivnih RF komponenti u PCB i LTCC tehnologiji, kao i poboljšanje njihovih performansi. Izvršena je i karakterizacijarazličitih tipova dielektričnih i feritnih&nbsp; LTCC materijala koji su korišćeni za izradu komponenti. Ukupno je projektovano i izrađeno 37 struktura, 14 induktora i 23 transformatora. Na poboljšanje karakteristika projektovanih struktura, koje se ogleda prvenstveno u povećanju induktivnosti zavojaka, uticalo se izradom projektovanih struktura na supstratima izrađenih od različitih materijala, supstratima formiranih od kombinacije materijala različitih karakteristika, redizajnom osnovnih (polaznih) geometrija struktura i optimizcijom parametara LTCC postupka izrade.</p> / <p>Topic of this theases focuses on design, fabrication and characterization of industive passive RF components in PCB and LTCC technology, as well as on improvement of their performances. Characterization of different types ofdielectric and ferrite LTCC materials that were implemented for component fabrication was also performed. In total, 37 structures were designed and fabricated, of those 14 are inductor structures and 23 are transformers. Performance improvement of designed structures that is manifested through increase of inductance value of structures windings implied fabrication of designed components on substrates formed from different materials, or from combination of two or more materials with different properties, redesign of original design and optimization of LTCC fabrication process parameters.</p>