While a lot of time and resources have been placed into transceiver design, due to the pace of a conventional engineering design process, the design of a power amplifier is often completed using scattered resources; and not always in a methodological manner, and frequently even by an iterative trial and error process. In this thesis, a research question is posed which enables for the investigation of the possibility of streamlining the design flow for power amplifiers. After thorough theoretical investigation of existing power amplifier design methods and modelling, inductors inevitably used in power amplifier design were identified as a major drawback to efficient design, even when examples of inductors are packaged in design HIT-Kits. The main contribution of this research is engineering of an inductor design process, which in-effect contributes towards enhancing conventional power amplifiers. This inductance search algorithm finds the highest quality factor configuration of a single-layer square spiral inductor within certain tolerance using formulae for inductance and inductor parasitics of traditional single-π inductor model. Further contribution of this research is a set of algorithms for the complete design of switch-mode (Class-E and Class-F) power amplifiers and their output matching networks. These algorithms make use of classic deterministic design equations so that values of parasitic components can be calculated given input parameters, including required output power, centre frequency, supply voltage, and choice of class of operation. The hypothesis was satisfied for SiGe BiCMOS S35 process from Austriamicrosystems (AMS). Several metal-3 and thick-metal inductors were designed using the abovementioned algorithm and compared with experimental results provided by AMS. Correspondence was established between designed, experimental and EM simulation results, enabling qualification of inductors other than those with experimental results available from AMS by means of EM simulations with average relative errors of 3.7% for inductors and 21% for the Q factor at its peak frequency. For a wide range of inductors, Q-factors of 10 and more were readily experienced. Furthermore, simulations were performed for number of Class-E and Class-F amplifier configurations with HBTs with ft greater than 60 GHz and total emitter area of 96 μm² as driving transistors to complete the hypothesis testing. For the complete PA system design (including inductors), simulations showed that switch-mode power amplifiers for 50 Ω load at 2.4 GHz centre frequency can be designed using the streamlined method of this research for the output power of about 6 dB less than aimed. This power loss was expected, since it can be attributed to non-ideal properties of the driving transistor and Q-factor limitations of the integrated inductors, assumptions which the computations of the routine were based on. Although these results were obtained for a single micro-process, it was further speculated that outcome of this research has a general contribution, since streamlined method can be used with a much wider range of CMOS and BiCMOS processes, when low-gigahertz operating power amplifiers are needed. This theory was confirmed by means of simulation and fabrication in 180 nm BiCMOS process from IBM, results of which were also presented. The work presented here, was combined with algorithms for SPICE netlist extraction and the spiral inductor layout extraction (CIF and GDSII formats). This secondary research outcome further contributed to the completeness of the design flow. All the above features showed that the routine developed here is substantially better than cut-and-try methods for design of power amplifiers found in the existing body of knowledge. / Thesis (PhD(Eng))--University of Pretoria, 2011. / Electrical, Electronic and Computer Engineering / unrestricted

No description available.

Rapid growth in the field of communications industry has led to newer opportunities and challenges in the design of CMOS based monolithic integrated circuits. ASK modulators are a class of digital modulators which are known for their relative simplicity of implementation for low cost applications in the industrial and biomedical domains. This thesis presents a LC-based CMOS Amplitude Shift Keying (ASK) modulator scheme which demonstrates promising capability for radio frequency designs. This work describes the design and implementation of differential cross-coupled NMOS only LC power oscillator with ASK modulation to operate at 2.4 GHz frequency. In this work, 65nm CMOS process technology has been used for implementation. The work mainly focused on system parameters such as oscillation frequency, output signal power, power consumption and phase noise. The LC tank was created with a centre-tap on-chip differential spiral inductor and a Metal Insulator Metal (MIM) capacitor. The method of a current mirror with switching technique is employed for biasing the LC oscillator as well as ASK modulation output. The oscillator circuit has been optimised by using a simulation based approach to study the design and measurements to gain a greater insight into the performance of the ASK modulator. An output signal power of -1.59dBm at 2.30 GHz with a phase noise of -115.39dBc/Hz@1MHz and a power consumption of 5.92mW has been achieved at the layout level. Optimal ASK modulated output performance has been obtained for the data rate of up to around 40Mbits/s. In this thesis, simulation results have been presented for both the schematic and the layout levels.

No description available.

Hydrogen has been identified by the European Commission to be a competitive alternative to fossil fuels within the transport sector in the medium to long perspective. Because of this, an increased understanding is required of the electrical power train present within such vehicles. An integral aspect of these systems is the interface converter, which is located between the fuel cell and the rest of the power train. During the design process of high-powered fuel cell interface converters used in transport applications, it is important to achieve designs of low losses, size and cost. One of the most important parts to achieve these goals is the inductor present within the converter; this is generally the bulkiest part of the converter. To analyse how the inductor’s properties are affected by the converter topology, three different topologies have been analysed: the conventional single-phase boost converter and two versions a two-phase interleaved boost converter, where one uses two single inductors and the other an inversely coupled inductor. These three cases’ steady-state properties have then been characterised and used to select designs minimising either the self-inductance or the flux levels induced in the inductor, while maintaining a permissible input current ripple and continuous conduction mode throughout the converter’s operational region. Finally, a preliminary design framework has been developed for both the single and coupled inductors, where initially the so-called geometrical constant method and then a multiobjective optimisation method using evolutionary algorithms was used to design each inductor. Provided the optimisation framework was fed appropriate bounds and constraints, it was able to outperform the geometrical method. For the case of an inductor operating under a high DC bias, it was found that it is better to premiere a core material with a high saturation flux density over a reduction in the losses. Moreover, the inductor’s dimensions are reduced by using an inversely coupled core irrespective if the switching frequency was the same or halved compared to the test case of the conventional boost converter inductor. Irrespective of the switching frequency, a coupling factor of 0.55 is deemed to provide the best overall performance and most robust design at the price of a slightly worse transient response compared to using a stronger coupling. / Vätgas har blivit identifierat av den Europeiska kommissionen till att vara ett konkurrenskraftigt alternativ till fossila bränslen inom transportsektorn i ett mellan- till långtidsperspektiv. På grund av det krävs en bättre förståelse av det elektriska drivsystemet som används inom dessa fordon. En viktig del av ett sådant drivsystem är gränssnittsomvandlaren som är placerad emellan bränslecellen och de resterande delarna av drivsystemet. Under designprocessen av gränssnittsomvandlare till kraftfulla bränsleceller, ämnade till att användas inom transportapplikationer, är det viktigt att uppnå designer med låga förluster, storlek och kostnad. En av de viktigaste delarna till att uppnå dessa målsättningar är induktansen; detta är generellt den största delen av omriktaren. Som metod till att analysera hur induktorns egenskaper påverkas av omriktarens topologi, har tre olika topologier analyserats: den konventionella boost omriktaren och två versioner av en två-fas interleaved boost omriktare, där en använder två induktanser och den andra en omvänt kopplad induktans. Dessa tre olika falls egenskaper under stabilt tillstånd karakteriserades och sedan användes för att välja designer som antingen minimerade själv-induktansen eller järnkärnans magnetiska flöde, medan ett godkänt rippel och kontinuerlig ledningsläge säkerhetsställdes för hela omriktarens operativa region. Slutgiltigen formulerades en reluktansbaserad dimensionerings metod för varje fall av induktor, där initialt den såkallade geometriska konstant metoden och sedan en multiobjektiv heuristisk optimerings metod, som baserades på evolutionära algoritmer, användes för att designa induktanserna. Förutsatt optimerings algoritmen fick ta del av korrekta gränser och begränsningar, utklassade den geometriska metoden. För induktanser utsatta för stora DC-komponenter i strömmen, är det bättre att premiera material med en hög mättningsgrad för den magnetisk flödestäthet över låga järnförluster. Utöver det är induktorns dimensioner reducerade genom att använda en omvänt kopplad induktor oavsett om samma eller en halverad switch frekvens användes jämfört med testfallet av den konventionella boost omvandlarens induktans. Oavsett switch frekvensen, en kopplings faktor på 0.55 ansågs ge den bästa prestandan samt mest robusta designen, till priset av ett någorlunda sämre transitenrespons jämfört med en starkare kopplingsfaktor.

No description available.

Over the past ten years, there has been increased use of electronic power processing in alternative, sustainable, and distributed energy sources, as well as energy storage systems, transportation systems, and the power grid. Three-phase voltage source converters (VSCs) have become the converter of choice in many ac medium- and high-power applications due to their many advantages, such as high efficiency and fast response. For transportation applications, high power density is the key design target, since increasing power density can reduce fuel consumption and increase the total system efficiency. While power electronics devices have greatly improved the efficiency, overall performance and power density of power converters, using power electronic devices also introduces EMI issues to the system, which means filters are inevitable in those systems, and they make up a significant portion of the total system size and cost. Thus, designing for high power density for both power converters and passive components, especially filters, becomes the key issue for three-phase converters. This dissertation explores two different approaches to reducing the EMI filter size. One approach focuses on the EMI filters itself, including using advanced EMI filter structures to improve filter performance and modifying the EMI filter design method to avoid overdesign. The second approach focuses on reducing the EMI noise generated from the converter using a three-level and/or interleaving topology and changing the modulation and control methods to reduce the noise source and reduce the weight and size of the filters. This dissertation is divided into five chapters. Chapter 1 describes the motivations and objectives of this research. After an examination of the surveyed results from the literature, the challenges in this research area are addressed. Chapter 2 studies system-level EMI modeling and EMI filter design methods for voltage source converters. Filter-design-oriented EMI modeling methods are proposed to predict the EMI noise analytically. Based on these models, filter design procedures are improved to avoid overdesign using in-circuit attenuation (ICA) of the filters. The noise propagation path impedance is taken into consideration as part of a detailed discussion of the interaction between EMI filters, and the key design constraints of inductor implementation are presented. Based on the modeling, design and implementation methods, the impact of the switching frequency on EMI filter weight design is also examined. A two-level dc-fed motor drive system is used as an example, but the modeling and design methods can also be applied to other power converter systems. Chapter 3 presents the impact of the interleaving technique on reducing the system passive weight. Taking into consideration the system propagation path impedance, small-angle interleaving is studied, and an analytical calculation method is proposed to minimize the inductor value for interleaved systems. The design and integration of interphase inductors are also analyzed, and the analysis and design methods are verified on a 2 kW interleaved two-level (2L) motor drive system. Chapter 4 studies noise reduction techniques in multi-level converters. Nearest three space vector (NTSV) modulation, common-mode reduction (CMR) modulation, and common-mode elimination (CME) modulation are studied and compared in terms of EMI performance, neutral point voltage balancing, and semiconductor losses. In order to reduce the impact of dead time on CME modulation, the two solutions of improving CME modulation and compensating dead time are proposed. To verify the validity of the proposed methods for high-power applications, a 100 kW dc-fed motor drive system with EMI filters for both the AC and DC sides is designed, implemented and tested. This topology gains benefits from both interleaving and multilevel topologies, which can reduce the noise and filter size significantly. The trade-offs of system passive component design are discussed, and a detailed implementation method and real system full-power test results are presented to verify the validity of this study in higher-power converter systems. Finally, Chapter 5 summarizes the contributions of this dissertation and discusses some potential improvements for future work. / Ph. D.

Fast and accurate diagnosis is always in demand by modern medical professionals and in the area of national defense. At present, limitations of testing speed, sample conditions, and levels of precision exist under current technologies, which are usually slow and involve testing the specimen under laboratory conditions. Typically, these methods also involve several biochemical processing steps and subsequent detection of low energy luminescence or electrical changes, all of which reduce the speed of the test as well as limit the precision. In order to solve these problems and improve the sensing performance, this project proposes an innovative CMOS magnetic biological sensor system for rapidly testing the presence of potential pathogens and bioterrorism agents (zoonotic microorganisms) both in specimens and especially in the environment. The sensor uses an electromagnetic detection mechanism to measure changes in the number of microorganisms--tagged by iron nanoparticles--that are placed on the surface of an integrated circuit (IC) chip. Measured magnetic effects are transformed into electronic signals that count the number and type of organisms present. This biosensor introduces a novel design of a conical-shaped inductor, which achieves ultra-accuracy of sensing biological pathogens. The whole system is integrated on a single chip based on the fabrication process of IBM 180 nm (CMOS_IBM_7RF), which makes the sensor small-sized, portable, high speed, and low cost. The results of designing, simulating, and fabricating the sensor are reported in this dissertation. / Ph. D.

Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor. This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components. The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end. Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches. This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered. / Master of Science

The passive components such as inductors and capacitors are bulky parts on circuit boards. Researchers in academia, government, and industry have been searching for ways to improve the magnetic energy density and reduce the package size of magnetic parts. The "constant-flux" concept discussed herein is leveraged to achieve high magnetic-energy density by distributing the magnetic flux uniformly, leading to inductor geometries with a volume significantly lower than that of conventional products. A relatively constant flux distribution is advantageous not only from the density standpoint, but also from the thermal standpoint via the reduction of hot spots, and from the reliability standpoint via the suppression of flux crowding. For toroidal inductors, adding concentric toroidal cells of magnetic material and distributing the windings properly can successfully make the flux density distribution uniform and thus significantly improve the power density. Compared with a conventional toroidal inductor, the constant-flux inductor introduced herein has an enclosed-winding geometry. The winding layout inside the core is configured to distribute the magnetic flux relatively uniformly throughout the magnetic volume to obtain a higher energy density and smaller package volume than those of a conventional toroidal inductor. Techniques to shape the core and to distribute the winding turns to form a desirable field profile is described for one class of magnetic geometries with the winding enclosed by the core. For a given set of input parameters such as the inductor's footprint and thickness, permeability of the magnetic material, maximum permissible magnetic flux density for the allowed core loss, and current rating, the winding geometry can be designed and optimized to achieve the highest time constant, which is the inductance divided by resistance (L/Rdc). The design procedure is delineated for the constant-flux inductor design together with an example with three winding windows, an inductance of 1.6 µH, and a resistance of 7 mΩ. The constant-flux inductor designed has the same inductance, dc resistance, and footprint area as a commercial counterpart, but half the height. The uniformity factor α is defined to reflect the uniformity level inside the core volume. For each given magnetic material and given volume, an optimal uniformity factor exists, which has the highest time constant. The time constant varies with the footprint area, inductor thickness, relative permeability of the magnetic material, and uniformity factor. Therefore, the objective for the constant-flux inductor design is to seek the highest possible time constant, so that the constant-flux inductor gives a higher inductance or lower resistance than commercial products of the same volume. The calculated time-constant-density of the constant-flux inductor designed is 4008 s/m3, which is more than two times larger than the 1463 s/m3 of a commercial product. To validate the concept of constant-flux inductor, various ways of fabrication for the core and the winding were explored in the lab, including the routing process, lasing process on the core, etching technique on copper, and screen printing with silver paste. The most successful results were obtained from the routing process on both the core and the winding. The core from Micrometals has a relative permeability of around 22, and the winding is made of copper sheets 0.5 mm thick. The fabricated inductor prototype shows a significant improvement in energy density: at the same inductance and resistance, the volume of the constant-flux inductor is two times smaller than that of the commercial counterpart. The constant-flux inductor shows great improvement in energy density and the shrinking of the total size of the inductor below that of the commercial products. Reducing the volume of the magnetic component is beneficial to most power. The study of the constant-flux inductor is currently focused on the dc analysis, and the ac analysis is the next step in the research. / Master of Science