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The data center serves as the hardware foundation for artificial intelligence (AI) and cloud computing, constituting a global market that has surpassed $200 billion and is experiencing rapid growth. It is estimated that data centers contribute to 1.7-2.2% of the world's electricity generation. Conversely, up to 80% of the long-term operational expenditure of data centers is allocated to electricity consumption. Consequently, enhancing the efficiency of electric energy conversion in data centers is not only economically advantageous but also crucial for achieving carbon-neutral objectives. Through collaborative efforts between the industrial and academic sectors, substantial advancements have been achieved in the energy conversion efficiency of data centers. Most converters within the data center power architecture now boast efficiencies exceeding 99%. However, the bottleneck for further improvements in system efficiency lies in the voltage regulator modules (VRMs), which grapple with challenges such as high conversion ratios, elevated output currents, and substantial load transients. These challenges are particularly pronounced for AI processors and graphics processing units (GPUs), given their heightened power demands compared to conventional central processing units (CPUs). To enhance system efficiency, a revolutionary shift in power architecture has been introduced, advocating for the adoption of a 48 V data center power architecture to replace the conventional 12 V architecture. The higher 48 V bus voltage significantly reduces distribution loss on the bus. However, the primary challenge lies in managing high step-down voltage conversion while maintaining high efficiency. Additionally, high-performance microprocessors, including CPUs, GPUs, application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs), require hundreds of amperes of current at low voltage levels (e.g., GPUs need >220 A at <1.85 V, CPUs need >1000 A at <1.0 V). An unavoidable consequence of upscaling processor current and size is the substantial resistive loss in VRMs. This is because such loss scales with the square of the current [I2R], and the power path area (and resistance R) expands with the processor size. The Power Delivery Network (PDN) resistance in the "last inch" of the power delivery path is becoming a limiting factor in processor performance and system efficiency. The key to reducing the I2R loss is minimizing the distance between the VRMs and processors by utilizing ultra-high power density VRMs. Furthermore, the design of Voltage Regulator Modules (VRMs) for high-performance microprocessors encounters additional formidable challenges, especially when dealing with the requirements of contemporary computing architectures. The key hurdles encompass achieving high efficiency, handling low output voltage, accommodating wide voltage ranges, managing elevated output currents, and addressing significant load transients. These challenges prompt both academia and industry to explore novel topologies, innovative magnetic integration methods, and advanced control strategies. The prevailing trend in state-of-the-art 48V solutions centers around the adoption of two-stage configurations, wherein the second stage can leverage conventional 12V solutions. However, this approach imposes limitations on power density and efficiency, given that power traverses two cascaded DC/DC converters. Additionally, the footprint of decoupling capacitors and I2R loss on the intermedia bus between the two stages is emerging as a noteworthy consideration in designs. In response to these challenges, a novel proposition introduces a single-stage 48V coupled-transformer voltage regulator (CTVR) tailored for high-performance microprocessors. This innovative design aims to deliver ultra-high power density and superior efficiency. The converter employs a unique magnetic structure that integrates transformers and coupled inductors from multiple current-doubler rectifiers. Significantly, by utilizing the magnetizing inductors of transformers as output inductors, there is a substantial reduction in the size of magnetic components. Various implementations are explored, each addressing specific design objectives. Initially, a single-stage coupled-transformer voltage regulator (CTVR) with discrete magnetics is presented, offering a 48V solution while maintaining a comparable size and cost to a state-of-the-art 12V multiphase buck regulator. Leveraging the indirect-coupling concept, magnetic components are standardized, enabling scalability and facilitating multiphase operation. A prototype is constructed and tested to validate the CTVR's performance. With a 48V input and 1.8V output, the peak efficiency registers at 92.1%, and the power area density is 0.45 W/mm2. However, voltage ringing is observed in both primary and secondary switches due to a larger leakage inductance and hard-switching operation. Subsequently, a transition to soft-switching operation is implemented to address the voltage ringing issue. The leakage inductance is intentionally designed to supply energy for zero-voltage switching (ZVS) of primary switches, turning the previously perceived drawback into an opportunity for efficiency improvement. As a result, testing demonstrates a peak efficiency increase of more than 1%, reaching 93.6%. Furthermore, efforts are made to enhance small leakage inductance by employing well-interleaved printed circuit board (PCB) windings. Following a series of design optimizations, the prototype achieves a peak efficiency of 93.1% and a remarkable power density of 1037 W/in3, accounting for gate driver loss and size. Despite an increase in cost associated with PCB windings, this proposed solution attains the highest power density and stands as the pioneering 48V single-stage design surpassing 1000 W/in3 power density. When prioritizing efficiency in the design, the quasi-parallel Sigma converter emerges as another optimal choices for a 48V solution. However, the intricate and distinctive quasi-parallel structure of the Sigma converter necessitates a thorough examination of its control mechanism, particularly in light of the rapid load transient response requirements. To address this, an adaptive voltage positioning (AVP) design for the Sigma converter is introduced, employing enhanced V2 control. Guidelines and limitations are provided to stabilize the converter and enhance its overall performance. Ultimately, the AVP function and load transient performance are substantiated through simulation and experimental results. / Doctor of Philosophy / Data center is the hardware foundation of artificial intelligence (AI) and cloud computing. The global data center market has exceeded $200 billion and is fast growing. It is estimated that data center accounts for 1.7~2.2% of the world's electricity generation. On the other hand, up to 80% of the long-term operation expenditure of data centers is electricity. Thus, improving the efficiency of electric energy conversion in data centers is economically beneficial and critical to reaching the carbon neutral goal. The bottleneck for further improvements in system efficiency lies in the voltage regulator modules (VRMs), which grapple with challenges such as high conversion ratios, elevated output currents, and substantial load transients. These challenges are particularly pronounced for AI processors and graphics processing units (GPUs). In response to these challenges, a novel proposition introduces a single-stage 48V coupled-transformer voltage regulator (CTVR) tailored for high-performance microprocessors. This innovative design aims to deliver ultra-high power density and superior efficiency. The converter employs a unique magnetic structure that integrates transformers and coupled inductors from multiple current-doubler rectifiers. Significantly, by utilizing the magnetizing inductors of transformers as output inductors, there is a substantial reduction in the size of magnetic components. Various implementations are explored, each addressing specific design objectives. When prioritizing efficiency in the design, the quasi-parallel Sigma converter emerges as another optimal choices for a 48V solution. However, the intricate and distinctive quasi-parallel structure of the Sigma converter necessitates a thorough examination of its control mechanism, particularly in light of the rapid load transient response requirements. To address this, an adaptive voltage positioning (AVP) design for the Sigma converter is introduced, employing enhanced V2 control. Guidelines and limitations are provided to stabilize the converter and enhance its overall performance. Ultimately, the AVP function and load transient performance are substantiated through simulation and experimental results.

This dissertation focuses on the development of low-temperature co-fired ceramics (LTCC) technology for power converter magnetics integration. Because magnetic samples must be fabricated with thick conductors for power applications, the conventional LTCC process is modified by cutting trenches in the LTCC tapes where conductive paste is filled to produce thick conductors to adapt to this requirement. Characterization of the ceramic magnetic material is performed, and an empirical model based on the Steinmetz equation is developed to help in the estimation of losses at frequencies between 1 MHz to 4 MHz, operating temperature between 25 °C and 70 °C, DC pre-magnetization from 0 A/m to 1780 A/m, and AC magnetic flux densities between 5 mT to 50 mT. Temperature and DC pre-magnetization dependence on Steinmetz exponents are included in the model to describe the loss behavior. In the development of the LTCC chip inductor, various geometries are evaluated. Rectangular-shaped conductor geometry is selected due to its potential to obtain a much smaller footprint, as well as the likelihood of having lower losses than almond-shaped conductors with the same cross-sectional area, which are typically a result of screen printing. The selected geometry has varying inductance with varying current, which helps improve converter efficiency at light load. The efficiency at a light-load current of 0.5 A can be improved by 30 %. Parametric variation of inductor geometry is performed to observe its effect on inductance with DC current as well as on converter efficiency. An empirical model is developed to describe the change in inductance with DC current from 0 A to 16 A for LTCC planar inductors fabricated using low-permeability tape with conductor widths between 1 mm to 4 mm, conductor thickness 180 μm to 550 μm, and core thickness 170 μm to 520 μm. An inductor design flow diagram is formulated to help in the design of these inductors. Configuring the inductor as the substrate carrying the semiconductor and the other electronic components is a next step to freeing the surface area of the bulky component and improving the power density. A conductive shield is introduced between the circuitry and the magnetic substrate to avoid adversely affecting circuit operation by having a magnetic substrate in close proximity to the circuitry. The shield helps reduce parasitic inductances when placed in close proximity to the circuitry. A shield thickness in the range of 50 μm to 100 μm is found to be a good compromise between power loss and parasitic inductance reduction. The shield is effective when its conductivity is above 10⁷ S/m. When a shield is introduced between the inductor substrate and the circuitry, the sample exhibits a lower voltage overshoot (47 % lower) and an overall higher efficiency (7 % higher at 16 A), than an inductor without a shield. A shielded active circuitry placed on top of an inductive substrate performs similarly to a shielded active circuitry placed side-by-side with the inductor. Using a floating shield for the active circuitry yields a slightly better performance than using a grounded shield. / Ph. D.

The work in this dissertation presents the first attempt in the literature to propose the concept of "soft switch". The goal of "soft switch" is to develop a standard PWM switch cell with built-in adaptive soft switching capabilities. Just like a regular switch, only one PWM signal is needed to drive the soft switch under soft switching condition. The core technique in soft switch development is a built-in adaptive soft switching circuit with minimized circulation energy. The necessity of minimizing circulation energy is first analyzed. The design and implementation of a universal controller for implementation of variable timing control to minimize circulation energy is presented. The controller has been tested successfully with three different soft switching inverters for electric vehicles application in the Partnership for a New Generation Vehicles (PNGV) project. To simplify the control, several methods to achieve soft switching with fixed timing control are proposed by analyzing a family of zero-voltage switching converters. The driver based soft switch concept was originated from development of a base driver circuit for current driven bipolar junction transistor (BJT). A new insulated-gate-bipolar-transistor (IGBT) and power metal-oxide-semiconductor field-effect-transistor (MOSFET) gated transistor (IMGT) base drive structure was initially proposed for a high power SiC BJT. The proposed base drive method drives SiC BJTs in a way similar to a Darlington transistor. With some modification, a new base driver structure can adaptively achieve zero voltage turn-on for BJT at all load current range with one single gate. The proposed gate driver based soft switching method is verified by experimental test with both Si and SiC BJT. The idea is then broadened for "soft switch" implementation. The whole soft switched BJT (SSBJT) structure behaves like a voltage-driven soft switch. The new structure has potentially inherent soft transition property with reduced stress and switching loss. The basic concept of the current driven soft switch is then extended to a voltage-driven device such as IGBT and MOSFET. The key feature and requirement of the soft switch is outlined. A new coupled inductor based soft switching cell is proposed. The proposed zero-voltage-transition (ZVT) cell serves as a good candidate for the development of soft switch. The "Equivalent Inductor" and state plane based analysis method are used to simply the analysis of coupled inductor based zero-voltage switching scheme. With the proposed analysis method, the operational property of the ZVT cell can be identified without solving complicated differential equations. Detailed analysis and design is proposed for a 3kW boost converter example. With the proposed soft switch design, the boost converter can achieve up to 98.9% efficiency over a wide operation range with a single gate drive. A high power inverter with coupled inductor scheme is also designed with simple control compared to the earlier implementation. A family of soft-switching converters using the proposed "soft switch" cell can be developed by replacing the conventional PWM switch with the proposed soft switch. / Ph. D.

In order to extend the battery life of smart cameras, it is essential to increase the efficiency of power converters, especially at light load. This thesis research investigated a power converter to supply power for the microprocessor of a smart camera. The input voltage of the converter is 5 V, and the output voltage is 1.2 V with the load ranging from 10 mA (12 mW) to 1200 mA (1440 mW). The conventional buck converter is typically optimized for high efficiency at maximum load at the cost of light-load efficiency. A converter is investigated in this thesis to improve light load efficiency, while being able to handle heavy load, to prolong the battery life of smart cameras. The proposed converter employs two modes, a baby-buck mode and a heavy-load mode, in which each mode is optimized for its respective load range to achieve high efficiency throughout entire range. The heavy-load mode converter adopts the conventional synchronous buck approach, as it generally achieves high efficiency at heavy load. However, the synchronous buck approach is inefficient at light load due to the large switching, driving, and controller losses. The proposed baby-buck mode converter employs the following schemes or technique to reduce those losses. First, the baby buck mode converter adopts pulse frequency modulation (PFM) with discontinuous conduction mode (DCM) to lower the switching frequency at light load, so frequency-dependent switching and driving losses are reduced. Second, a simple control scheme, constant on-time V2 control, is adopted to simplify the controller and hence minimize the controller power dissipation. Third, the top switch of the baby-buck mode uses a small MOSFET, which is optimized for light load, and the bottom switch uses Schottky diode in lieu of a MOSFET to simplify the COT V2 controller. Fourth, the proposed converter combines the heavy-load and baby-buck mode converter into a single converter with a shared inductor, capacitors, and the feedback controller to save space. Finally, a simple and low power feedback controller with an optimum mode selector, a COT V 2 controller, and gate drivers are designed. The optimum mode selector selects an appropriate mode based on the load condition, while shutting down the opposing mode. The proposed converter was fabricated in CMOS 0.25 µm technology in two phases. Phase 1 contains design of the proposed converter with open loop, and its functionality is verified through measurements of test chips. Phase 2 includes the entire converter design with the feedback controller. Since the test chips of phase 2 are not delivered, yet, its functionality during the steady state and transient responses are verified through simulations. Simulation results indicate that the efficiency of the proposed converter ranges from 74% to 93% at 12 mW and 1440 mW, respectively. This result demonstrates that the proposed converter can achieve higher efficiency for the entire load range when compared to an off-the-shelf synchronous buck converters. / Master of Science

This thesis focuses on the design issues of the multiple-output boost full-bridge converter, which is constructed by cascading the boost regulator with the inductor-less full-bridge converter. The design of the boost regulator has been proposed briefly with component selection and compensator design. After that, the inductor-less full-bridge converter is analyzed extensively. In the first place, the operation principle of the inductor-less full-bridge converter is introduced. Later, the effect of parasitic resistance and inductance is analyzed in an L-R series circuit model as step-response, which relates the drop of output voltage to the load current. Then, the effects of the dc blocking capacitor for the unbalanced load condition and unbalanced duty cycle are tackled. The theoretical results are compared with the experimental results and the simulation results to verify the relationship between the output voltage drop and load current. The overall efficiency of the converter is tested under various conditions. The design of the planar transformer is critical to limit the profile of the converter and the leakage phenomenon. A planar transformer fit for the inductor-less full-bridge converter is designed and analyzed in 3D FEA software. An N-port transformer model is proposed to implement the inductance matrix into the leakage inductance matrix for circuit analysis. Based on this N-port model several measurements to extract the parameters in this model are proposed, where only the impedance analyzer is needed. Finally, the effects of trace layout and encapsulation on breakdown voltage in PCB are summarized from experimental results. / Master of Science

A wearable body temperature sensor would allow for early detection of fever or infection, as well as frequent and accurate hassle-free recording. This thesis explores the design of a body-temperature-sensing device inkjet-printed on a flexible substrate. All structures were first modeled by first-principles, theoretical calculations, and then simulated in HFSS. A variety of planar square inductor geometries were studied before selecting an optimal design. The designs were fabricated using multiple techniques and compared to the simulation results. It was determined that inductance must be carefully measured and documented to ensure good functionality. The same is true for parallel-plate and interdigitated capacitors. While inductance remains relatively constant with temperature, the capacitance of the device with a temperature-sensitive dielectric layer will result in a shift in the resonant frequency as environmental or ambient temperature changes. This resonant frequency can be wirelessly detected, with no battery required for the sensing device, from which the temperature can be deduced. From this work, the optimized version of the design comprises of conductive silver in with a temperature-sensitive graphene oxide layer, intended for inkjet-printing on flexible polyimide substrates. Graphene oxide demonstrates a high dielectric permittivity with good sensing capabilities and high accuracy. This work pushes the state-of-the-art in applying these novel materials and techniques to enable flexible body temperature sensors for future biomedical applications.

This dissertation focuses on high-performance LC-tank CMOS VCO design at 2 GHz. The high-Q inductors are realized using wiring metal lines in advanced packages. Those inductors are used in the resonator of the VCO to achieve low phase noise, low power consumption, and a wide frequency tuning range. In this dissertation, a fine-pitch ball-grid array (FBGA) package, a multichip module (MCM)-L package, and a wafer-level package (WLP) are incorporated to realize the high-Q inductor. The Q-factors of inductors embedded in packages are compared to those of inductors monolithically integrated on Si and GaAs substrates. All the inductors are modeled with a physical, simple, equivalent two-port model for the VCO design as well as for phase noise analysis. The losses in an LC-tank are analyzed from the phase noise perspective. For the implementation of VCOs, the effects of the interconnection between the embedded inductor and the VCO circuit are investigated. The VCO using the on-chip inductors is designed as a reference. The performance of VCOs using the embedded inductor in a FBGA and a WLP is compared with that of a VCO using the on-chip inductor. The VCO design is optimized from the high-Q perspective to enhance performance. Through this optimization, less phase noise, lower power consumption, and a wider frequency tuning range are obtained simultaneously.

Cette thèse s’inscrit dans le contexte d’alimentation des systèmes électroniques portables à faible puissance (1W environ) et fonctionnant sous faible tension. Avec la demande croissante pour la conversion d’énergie dans ces systèmes, l’intégration et la miniaturisation du convertisseur DC-DC devient une zone d’intérêt fort. Des recherches récentes ont montré des convertisseurs avec des fréquences de commutation pouvant atteindre 100 MHz. Pour de faibles niveaux de tension (1 V) et des puissances aux environs du Watt, les valeurs d’inductance de lissage de ces convertisseurs envisagées sont de l’ordre d’une centaine de nanoHenry. Ceci relance l’intérêt d’étudier l’intégration des composants passifs de dimensions millimétriques au sein d’un même boîtier avec les parties actives. Dans ce contexte, les travaux présentés dans ce manuscrit sont abordés par la conception d’inductances planaires en forme de spirale avec un noyau magnétique. Les simulations ont permis d’analyser les liens entre les paramètres géométriques et les paramètres électriques de l’inductance pour établir une structure d’inductance optimale en fonction de la limite de la technologie de réalisation. Une inductance planaire prise en sandwich entre deux couches de matériau magnétique est proposée. Les simulations ont montré l’intérêt de réaliser un tel composant. Sa structure présente plusieurs avantages, elle permet d’augmenter considérablement la valeur d’inductance tout en gardant le même encombrement par rapport à une inductance sans noyau magnétique. Elle permet également de réduire les perturbations électromagnétiques avec les composants environnants. Un procédé technologique de réalisation des inductances, basé sur la croissance électrolytique de cuivre à température ambiante, a été développé et optimisé pour valider les modélisations précédentes. Ce procédé est reproductible et permet une fabrication collective de composants. Un banc de caractérisation impédance métrique a également été conçu afin de déterminer les limites du fonctionnement fréquentiel des composants réalisés et de valider les performances de ces derniers. Ce travail propose une solution pour la réalisation de la puce active sur l’inductance dans le cadre d’un SOC (System-On-Chip). Il souligne par ailleurs l’importance de l’intégration pour l’électronique de faible puissance / The work in this thesis contributes to the domain of low power (1W approximately) portable electronic systems. These systems require integrated and miniaturized of DC-DC converters. Recent studies have demonstrated converters with high switching frequency as high as 100 MHz, requiring smaller passive components. For low voltage values (1V approximately) and 1 watt output power, the inductance value of these converter filters is about a hundred nanoHenry. Such inductors can be integrated on a millimetric scale in the same package as the active die. In this context, the work presented in this thesis starts with the design of planar spiral inductors with a magnetic core. Simulations allowed to analyze the relation between geometrical and electrical parameters of the inductor in order to design an optimal inductor. A planar inductor sandwiched between two layers of magnetic material is proposed. Simulations showed the advantages of fabricating of such component. Its structure allows to increase the inductance value without modifying the inductor’s surface compared to a coreless inductor. It also allows to reduce the electromagnetic interferences with the rest of the circuit. A technological process for the fabrication of the inductors has been developed and optimized in order to valid the previous design. This process is based on copper electroplating technique which is compatible with a repeatable and a mass fabrication of inductors. A characterization bench was also developed in order to determine the operating frequency limits of the fabricated components as well as to validate their performance. This work offers a solution for the realization of the active chip on the inductor (SOC, System- On-Chip). It also emphasizes the importance of the integration for low power electronics

Thesis dissertate power reactors and analyses techniques of an air-core power coils and inductors with ferromagnetic circuit and an air gap. Construction of the inductors verified the accuracy of the calculated values against the measured parameters. According to the outcome of this analysis, corrections of the design process are derived. Thesis design optimization to minimize size, weight, efficiency and in comparsion of these two factoctors.