La miniaturisation nécessaire à l'accroissement des performances des composants microélectroniques est en passe d'atteindre ses limites. Ainsi, une nouvelle approche dite « intégration 3D » semble prometteuse pour outrepasser les limitations observées. Cette nouvelle intégration consiste à empiler les différentes puces qui sont reliées entre elles par des vias appelées Through Silicon Vias (TSV). L'une des clés pour la réalisation de circuits en 3 dimensions est la métallisation des TSVs. Cette dernière nécessite les dépôts d'une barrière et d'une couche d'accroche qui sert à initier le remplissage par électrolyse. Ces travaux s'intéressent plus spécifiquement à la réalisation de la couche d'accroche et au remplissage des TSVs.La couche d'accroche est généralement déposée par pulvérisation, ce qui ne permet pas d'obtenir une couverture de marche satisfaisante pour la réalisation du remplissage. Cette étude propose une solution électrolytique appelée SLE (Seed Layer Enhancement) qui permet de restaurer la continuité de la couche d'accroche déposée par PVD. L'application de ce procédé associé à un traitement de désoxydation de la surface permet l'optimisation de la nucléation du cuivre et donc la réalisation d'une couche de cuivre continue et conforme. Le procédé SLE a été intégré à la séquence de métallisation et a démontré sa capacité à initier un remplissage superconforme. De plus, des tests électriques ont confirmé l'efficacité du procédé SLE une fois intégré. Ces expériences ont ouvert la voie à l'étude du dépôt électrolytique de cuivre direct sur la barrière à la diffusion du cuivre, c'est le procédé Direct On Barrier. Les premiers résultats ont permis de démontrer la possibilité de déposer une couche de cuivre conforme sur des barrières résistives. Le second volet de ces travaux s'intéresse au remplissage par électrolyse des TSVs. Dans ce but, deux électrolytes (d'ancienne et de nouvelle génération) ont été considérés. L'effet des additifs sur le dépôt et leurs actions sur le remplissage superconforme ont été étudiés par voltampérométrie et chronopotentiométrie pour chacune des solutions. Ces analyses ont permis de monter deux mécanismes de remplissage différents principalement dû à l'action de l'additif inhibiteur durant l'électrolyse. Contrairement au cas de l'électrolyte d'ancienne génération inspiré des procédés pour le damascène, l'inhibiteur de l'électrolyte de nouvelle génération s'adsorbe fortement et irréversiblement à la surface du cuivre. Il bloque efficacement la croissance sur les flancs et le haut des TSVs, sans toutefois pouvoir contrarier l'action de l'accélérateur en fond de motif. / Nowadays, 2D integration shows serious limitations when it comes to manufacturing devices with increased functionality and performance. In this context, 3D integration approaches using Through Silicon Vias (TSVs) have been investigated as a promising solution to fabricate tomorrow's microelectronics devices. In this architecture, the key challenge is the metallization of high aspect ratios (>5) TSVs by copper electrochemical deposition (Cu ECD). This metallization sequence includes barrier and seed layer deposition followed copper filling. This study is focused on seed layer deposition and TSV filling. Usually, the seed layer is grown by sputtering based deposition techniques (PVD). This technique suffers from limited sidewall coverage, eventually leading to electrical discontinuity in the features. In this work, an electrolytic process called Seed Layer Enhancement (SLE) has been investigated as a solution to improve copper seed continuity. For this purpose, copper nucleation on the resistive barrier material has been optimized using a specific surface treatment to remove native oxide on samples surface. As a result, the SLE process has been successfully inserted in the metallization sequence, as testified by good electrical performances. These promising results open the route to an alternative solution to PVD using an electrochemical process performed directly on the barrier diffusion layer (Direct On Barrier). On the other hand, two electrolytes (an old and a new generation) have been evaluated as solutions for TSV filling. In each case, the impact of additives on copper deposition and superfilling mechanism were analyzed by voltammetric and chronopotentiometric measurements on rotating disk electrode. This study shows two different filling behaviors, close to damascene electrolyte with the older generation electrolyte, and a bottom-up filling with the last generation. The main difference comes from the action of the inhibiting additive during the filling process. In the case of the last generation electrolyte, the inhibitor adsorbs strongly and irreversibly on the copper surface. Then, a strong inhibition of copper growth occurs on the sides and on the top of the TSVs, but the action of accelerator is still efficient at the pattern bottom.

Avec la miniaturisation continue des circuits intégrés et le remplacement de l’oxydede silicium par des diélectriques low-κ poreux à base de SiOCH, la fiabilité des circuitsmicroélectroniques a été fortement compromise. Il est aujourd’hui extrêmement importantde mieux appréhender les mécanismes de dégradation au sein de ces matériaux afin deréaliser une estimation précise de leur durée de vie.Dans ce contexte, ces travaux de thèse ont consisté à étudier les mécanismes de dégradationau sein du diélectrique afin de proposer un modèle de durée de vie plus pertinent.Par une étude statistique du temps à la défaillance sous différents types de stress électrique,un mécanisme de génération des défauts par impact est mis en évidence. En l’associantau mécanisme de conduction au sein du diélectrique, il a été possible de développer unmodèle de durée de vie cohérent pour les interconnexions permettant une estimation de ladurée de vie plus fiable que les modèles de la littérature. L’impact du piégeage de chargesdans le diélectrique a ensuite été analysé grâce à ce modèle. / With the constant size reduction of integrated circuits and the replacement of silicon dioxide with porous SiOCH, the reliability of interconnects has been sharply reduced. A better understanding of degradation mechanisms is now required in order to have a precise estimation of product lifetime. In this work, degradation mechanisms have been studied in order to propose a more accurate lifetime model. A statistical study of times to failure under various electrical stresses is used to explain the physical mechanisms involved in defect creation. Combining these degradation mechanisms and Poole-Frenkel conduction mechanism enables the use of a new lifetime model. This model leads to a better estimation of the lifetime than existing models. Finally, the effects of charge trapping on lifetime in these materials have been studied.

La photonique au silicium est une technologie émergente considérée comme l'une des solutions clés pour les interconnexions sur puce de génération future, offrant plusieurs avantages potentiels tels qu'une faible latence de transmission et une bande passante élevée. Cependant, elle reste confrontée à des défis en matière d'efficacité énergétique. Différentes topologies, layout et architectures offrent diverses options d'interconnexion. Ceci conduit à une grande variation des pertes optiques, qui est l'un des facteurs prédominants dans la consommation d'énergie. De plus, les composants photoniques au silicium sont très sensibles aux variations de température. Sous une activité de puces donnée, ceci conduit à une réduction de l’efficacité des lasers et à une dérive des longueurs d'onde des composants optiques, ce qui entraîne un «Bit Error Ratio (BER)» plus élevé et réduit par conséquent l'efficacité énergétique des interconnexions optiques. Dans cette thèse, nous travaillons sur des méthodologies de conception pour les interconnexions photoniques sur silicium économes-en-énergie et prenant en compte la topologie / le layout, la variation thermique et l'architecture. / Silicon photonics is an emerging technology considered as one of the key solutions for future generation on-chip interconnects, providing several prospective advantages such as low transmission latency and high bandwidth. However, it still encounters challenges in energy efficiency. Different topologies, physical layouts, and architectures provide various interconnect options for on-chip communication. This leads to a large variation in optical losses, which is one of the predominant factors in power consumption. In addition, silicon photonic devices are highly sensitive to temperature variation. Under a given chip activity, this leads to a lower laser efficiency and a drift of wavelengths of optical devices (on-chip lasers and microring resonators (MRs)), which in turn results in a higher Bit Error Ratio (BER) and consequently reduces the energy efficiency of optical interconnects. In this thesis, we work on design methodologies for energy-efficient silicon photonic interconnects on chip related to topology/layout, thermal variation, and architecture.

Avec l’augmentation du nombre de cœurs, les problèmes de congestion sont commencé avec les interconnexions conventionnelles. Afin de remédier à ces défis, WiNoCoD projet (Wired RF Network-on-Chip Reconfigurable-on-Demand) a été initié par le financement de l’Agence Nationale de Recherche (ANR). Ce travail de thèse contribue à WiNoCoD projet. Une structure de contrôleur de RF est proposé pour l’interconnexion OFDMA de WiNoCoD et plusieurs algorithmes d’allocation de bande passante efficaces (distribués et centralisés) sont développés, concernant les demandes et contraintes très spécifiques de l’environnement sur-puce. Un protocole innovante pour l’arbitrage des sous-porteuses pour des longueurs bimodales de paquets sur-puce, qui ne nécessite aucun signalisation supplémentaire est introduit. Utilisation des ordres de modulation élevés avec plus grande consommation d’énergie est évaluée. / With rapidly increasing number of cores on a single chip, scalability problems have arised due to congestion and latency with conventional interconnects. In order to address these issues, WiNoCoD project (Wired RF Network-on-Chip Reconfigurable-on-Demand) has been initiated by the support of French National Research Agency (ANR). This thesis work contributes to WiNoCoD project. A special RF controller structure has been proposed for the OFDMA based wired RF interconnect of WiNoCoD. Based on this architecture, effective bandwidth allocation algorithms have been presented, concerning very specific requirements and constraints of on-chip environment. An innovative subcarrier allocation protocol for bimodal packet lengths of cache coherency traffic has been presented, which is proven to decrease average latency significantly. In addition to these, effective modulation order selection policies for this interconnect have been introduced, which seeks the optimal delay-power trade-off.

<div>The design of advanced integrated circuits (ICs) and systems calls for multiphysics and large-scale modeling and simulation methods. On the one hand, novel devices and materials are emerging in next-generation IC technology, which requires multiphysics modeling and simulation. On the other hand, the ever-increasing complexity of ICs requires more efficient numerical solvers.</div><div><br></div><div>In this work, we propose a multiphysics modeling and simulation algorithm to co-simulate Maxwell's equations, dispersion relation of materials, and Boltzmann equation to characterize emerging new devices in IC technology such as Cu-Graphene (Cu-G) hybrid nano-interconnects. We also develop an unconditionally stable time marching scheme to remove the dependence of time step on space step for an efficient simulation of the multiscaled and multiphysics system. Extensive numerical experiments and comparisons with measurements have validated the accuracy and efficiency of the proposed algorithm. Compared to simplified steady-state-models based analysis, a significant difference is observed when the frequency is high or/and the dimension of the Cu-G structure is small, which necessitates our proposed multiphysics modeling and simulation for the design of advanced Cu-G interconnects. </div><div><br></div><div>To address the large-scale simulation challenge, we develop a new split-field domain-decomposition algorithm amenable for parallelization for solving Maxwell’s equations, which minimizes the communication between subdomains, while having a fast convergence of the global solution. Meanwhile, the algorithm is unconditionally stable in time domain. In this algorithm, unlike prevailing domain decomposition methods that treat the interface unknown as a whole and let it be shared across subdomains, we partition the interface unknown into multiple components, and solve each of them from one subdomain. In this way, we transform the original coupled system to fully decoupled subsystems to solve. Only one addition (communication) of the interface unknown needs to be performed after the computation in each subdomain is finished at each time step. More importantly, the algorithm has a fast convergence and permits the use of a large time step irrespective of space step. Numerical experiments on large-scale on-chip and package layout analysis have demonstrated the capability of the new domain decomposition algorithm. </div><div><br></div><div>To tackle the challenge of efficient simulation of irregular structures, in the last part of the thesis, we develop a method for the stability analysis of unsymmetrical numerical systems in time domain. An unsymmetrical system is traditionally avoided in numerical formulation since a traditional explicit simulation is absolutely unstable, and how to control the stability is unknown. However, an unsymmetrical system is frequently encountered in modeling and simulating of unstructured meshes and nonreciprocal electromagnetic and circuit devices. In our method, we reduce stability analysis of a large system into the analysis of dissembled single element, therefore provides a feasible way to control the stability of large-scale systems regardless of whether the system is symmetrical or unsymmetrical. We then apply the proposed method to prove and control the stability of an unsymmetrical matrix-free method that solves Maxwell’s equations in general unstructured meshes while not requiring a matrix solution.<br></div><div><br></div>

Existing optical networks are driven by dynamic user and application demands but operate statically at their maximum performance. Thus, optical links do not offer much adaptability and are not very energy-effcient. In this paper a novel approach of implementing performance and power adaptivity from system down to optical device, electrical circuit and transistor level is proposed. Depending on the actual data load, the number of activated link paths and individual device parameters like bandwidth, clock rate, modulation format and gain are adapted to enable lowering the components supply power. This enables exible energy-efficient optical transmission links which pave the way for massive reductions of CO2 emission and operating costs in data center and high performance computing applications. Within the FP7 research project Adaptive Data and Power Aware Transceivers for Optical Communications (ADDAPT) dynamic high-speed energy-efficent transceiver subsystems are developed for short-range optical interconnects taking up new adaptive technologies and methods. The research of eight partners from industry, research and education spanning seven European countries includes the investigation of several adaptive control types and algorithms, the development of a full transceiver system, the design and fabrication of optical components and integrated circuits as well as the development of high-speed, low-loss packaging solutions. This paper describes and discusses the idea of ADDAPT and provides an overview about the latest research results in this field.

Optical connectivity has the potential to outperform copper-based TSVs in terms of bandwidth at the cost of more complexity due to the required electro-optical and opto-electrical conversion. The continuously increasing demand for higher bandwidth pushes the breakeven point for a profitable operation to shorter distances. To integrate an optical communication network in a 3D-chip-stack optical through-silicon vertical VIAs (TSV) are required. While the necessary effort for the electrical/optical and vice versa conversion makes it hard to envision an on-chip optical interconnect, a chip-to-chip optical link appears practicable. In general, the interposer offers the potential advantage to realize electro-optical transceivers on affordable expense by specific, but not necessarily CMOS technology. We investigated the realization and characterization of optical interconnects as a polymer based waveguide in high aspect ratio (HAR) TSVs proved on waferlevel. To guide the optical field inside a TSV as optical-waveguide or fiber, its core has to have a higher refractive index than the surrounding material. Comparing different material / technology options it turned out that thermal grown silicon dioxide (SiO2) is a perfect candidate for the cladding (nSiO2 = 1.4525 at 850 nm). In combination with SiO2 as the adjacent polymer layer, the negative resist SU-8 is very well suited as waveguide material (nSU-8 = 1.56) for the core. Here, we present the fabrication of an optical polymer based multimode waveguide in TSVs proved on waferlevel using SU-8 as core and SiO2 as cladding. The process resulted in a defect-free filling of waveguide TSVs with SU-8 core and SiO2 cladding up to aspect ratio (AR) 20:1 and losses less than 3 dB.

This paper describes simulation, technology- and process development for the manufacturing of single mode polymeric waveguides by photolithography. Simulations for single mode operation in O- and C-band are carried out. Waveguides are directly patterned with UV-photolithography using Ormocere®-material. Fiber to waveguide coupling and near field are characterized.

Since its inception as the Tungsten Workshop in 1984, AMC has served as the leading conference for the interconnect and contact metallization communities, and has remained at the leading edge of the development of tungsten, aluminum, and copper/low-K interconnects. As the semiconductor industry evolves, exciting new challenges in metallization are emerging, particularly in the areas of contacts to advanced devices, local interconnect solutions for highly-scaled devices, advanced memory device metallization, and 3D/packaging technology. While the conference content has evolved, the unique workshop environment of AMC fosters open discussion to create opportunities for cross-pollination between academia and industry. Submissions are covering materials, process, integration and reliability challenges spanning a wide range of topics in metallization for interconnect/contact applications, especially in the areas of: - Contacts to advanced devices (FinFET, Nanowire, III/V, and 2D materials) - Highly-scaled local and global interconnects - Beyond Cu interconnect - Novel metallization schemes and advanced dielectrics - Interconnect and device reliability - Advanced memory (NAND/DRAM, 3D NAND, STT and RRAM) - 3D and packaging (monolithic 3D, TSV, EMI) - Novel and emerging interconnects Executive Committee: Sang Hoon Ahn (Samsung Electronics Co., Ltd.) Paul R. Besser (Lam Research) Robert S. Blewer (Blewer Scientific Consultants, LLC) Daniel Edelstein (IBM) John Ekerdt (The University of Texas at Austin) Greg Herdt (Micron) Chris Hobbs (Sematech) Francesca Iacopi (Griffith University) Chia-Hong Jan (Intel Corporation) Rajiv Joshi (IBM) Heinrich Koerner (Infineon Technologies) Mehul Naik (Applied Materials Inc.) Fabrice Nemouchi (CEA LETI MINATEC) Takayuki Ohba (Tokyo Institute of Technology) Noel Russell (TEL Technology Center, America) Stefan E. Schulz (Chemnitz University of Technology) Yosi Shacham-Diamand (Tel-Aviv University) Roey Shaviv (Applied Materials Inc.) Zsolt Tokei (IMEC)

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