The central thesis of this research is that VLSI interconnect design strategies should shift from using global wires that can support only a single binary transition during the latency of the line to global wires that can sustain multiple bits traveling simultaneously along the length of the line. It is shown in this thesis that such throughput-centric multibit transmission can be achieved by wave-pipelining the interconnects using repeaters. A holistic analysis of wave-pipelined interconnect circuits, along with the full-custom optimization of these circuits, is performed in this research. With the help of models and methodologies developed in this thesis, the design rules for repeater insertion are crafted to simultaneously optimize performance, power, and area of VLSI global interconnect networks through a simultaneous application of voltage scaling and wire sizing. A qualitative analysis of latency, throughput, signal integrity, power dissipation, and area is performed that compares the results of design optimizations in this work to those of conventional global interconnect circuits. The objective of this thesis is to study the circuit- and system-level opportunities of voltage scaling, wire sizing, and repeater insertion in wave-pipelined global interconnect networks that are implemented in deep submicron technologies.

Electron Beam Induced Deposition (EBID) is an emerging additive nanomanufacturing tool which enables growth of complex 3-D parts from a variety of materials with nanoscale resolution. Fundamentals of EBID and its application to making a robust, low-contact-resistance electromechanical junction between a Multiwall Carbon Nanotube (MWNT) and a metal electrode are investigated in this thesis research. MWNTs are promising candidates for next generation electrical and electronic devices, and one of the main challenges in MWNT utilization is a high intrinsic contact resistance of the MWNT-metal electrode junction interface. EBID of an amorphous carbon interface has previously been demonstrated to simultaneously lower the electrical contact resistance and to improve mechanical characteristics of the MWNT-electrode junction. In this work, factors contributing to the EBID formation of the carbon joint between a MWNT and an electrode are systematically explored via complimentary experimental and theoretical investigations. A comprehensive dynamic model of EBID using residual hydrocarbons as a precursor molecule is developed by coupling the precursor mass transport, electron transport and scattering, and surface deposition reaction. The model is validated by comparison with experiments and is used to identify different EBID growth regimes and the growth rates and shapes of EBID deposits for each regime. In addition, the impact of MWNT properties, the electron beam impingement location and energy on the EBID-made carbon joint between the MWNT and the metal electrode is critically evaluated. Lastly, the dominant factors contributing to the overall electrical resistance of the MWNT-based electrical interconnect and relative importance of the mechanical contact area of the EBID-made carbon joint to MWNT vs. that to the metal electrode are determined using carefully designed experiments.

Small form-factor packages with high integration density are driving the innovations in chip-to-package interconnections. Metallurgical interconnections have evolved from the conventional eutectic and lead-free solders to fine pitch copper pillars with lead-free solder cap. However, scaling down the bump pitch below 50-80µm and increasing the interconnect density with this approach creates a challenge in terms of accurate solder mask lithography and joint reliability with low stand-off heights. Going beyond the state of the art flip-chip interconnection technology to achieve ultra-fine bump pitch and high reliability requires a fundamentally- different approach towards highly functional and integrated systems. This research demonstrates a low-profile copper-to-copper interconnect material and process approach with less than 20µm total height using adhesive bonding at lower temperature than other state-of-the-art methods. The research focuses on: (1) exploring a novel solution for ultra-fine pitch (< 30µm) interconnections, (2) advanced materials and assembly process for copper-to-copper interconnections, and (3) design, fabrication and characterization of test vehicles for reliability and failure analysis of the interconnection. This research represents the first demonstration of ultra-fine pitch Cu-to-Cu interconnection below 200°C using non-conductive film (NCF) as an adhesive to achieve bonding between silicon die and organic substrate. The fabrication process optimization and characterization of copper bumps, NCF and build-up substrate was performed as a part of the study. The test vehicles were studied for mechanical reliability performance under unbiased highly accelerated stress test (U-HAST), high temperature storage (HTS) and thermal shock test (TST). This robust interconnect scheme was also shown to perform well with different die sizes, die thicknesses and with embedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu bonding was demonstrated offering a potential solution for future flip chip packages as well as with chip-last embedded active devices in organic substrates.

For decades, advances in device scaling has proven to be critical in improving the performance and productivity of 2D systems. In this thesis, we explore how advances in technology have pushed functional integration to such a high-level that interconnection and packaging issues represent real barriers to further progress. While three-dimensional (3D) integration offers to be a potential contender to overcome the barriers of increased energy consumption due to interconnects and bandwidth limitations, there are certain challenges that must be overcome before systems can be successfully stacked. Cooling and power delivery are among these key challenges in the integration of high performance 3D ICs. To address these challenges, microchannel heat sinks for inter-stratum cooling and through-silicon vias (TSVs) for signaling and power delivery between stacked ICs were explored. Novel integration schemes to integrate these uidic and electrical interconnects in conventional CMOS processes were also explored. Compact physical modeling was utilized to understand the trade-offs involved in the integration of electrical and microfluidic interconnects in a 3D IC stack. These concepts were demonstrated experimentally by showing different CMOS compatible methods of fabricating microchannels and integration of high aspect ratio (~20:1) and high density (200,000/cm²) electrical TSVs in the fins of the microchannels for signaling and power delivery. A novel mesh process for bottom up plating of high aspect ratio TSVs is also shown in this work. Fluidic reliability measurements are shown to demonstrate the feasibility of this technology. This work also demonstrates the design and fabrication of a 3D testbed which consists of a 2 chip stack with microchannel cooling on each level. Preliminary testing of the stack along with interlayer electro-fluidic I/Os has also been demonstrated.

As the current electronic trend is toward integrating multiple functions in a single electronic device, there is a clear need for increasing integration density which is becoming more emphasized than in the past. To meet the industrial need and realize the new system-integration law [1], three-dimensional (3-D) integration is becoming necessary. 3-D integration of multiple functional IC chip/package modules requires co-simulation of the chip and the package to evaluate the performance of the system accurately. Due to large scale differences in the physical dimensions of chip-package structures, the chip-package co-simulation in time-domain using the conventional FDTD scheme is challenging because of Courant-Friedrich-Levy (CFL) condition that limits the time step. Laguerre-FDTD has been proposed to overcome the limitations on the time step. To enhance performance and applicability, SLeEC methodology [2] has been proposed based on the Laguerre-FDTD method. However, the SLeEC method still has limitations to solve practical 3-D integration problems. This dissertation proposes further improvements of the Laguerre-FDTD and SLeEC method to address practical problems in 3-D interconnects and 3-D integration. A method that increases the accuracy in the conversion of the solutions from Laguerre-domain to time-domain is demonstrated. A methodology that enables the Laguerre-FDTD simulation for any length of time, which was challenging in prior work, is proposed. Therefore, the analysis of the low-frequency response can be performed from the time-domain simulation for a long time period. An efficient method to analyze frequency-domain response using time-domain simulations is introduced. Finally, to model practical structures, it is crucial to model dispersive materials. A Laguerre-FDTD formulation for frequency-dependent dispersive materials is derived in this dissertation and has been implemented.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.

The continuing scaling of integrated circuits beyond 22nm technology node poses increasing challenges to Electromigration (EM) reliability for Cu on-chip interconnects. First, the width of Cu lines in advanced technology nodes is less than the electron mean free path which is 39nm in Cu at room temperature. This is a new size regime where any new scaling effect on EM is of basic interest. And second, the reduced line width necessitates the development of new methods to analyze the EM characteristics. Such studies will require the development of well controlled processes to fabricate suitable test structures for EM study and model verification. This dissertation is to address these critical issues for EM in Cu interconnects. The dissertation first studies the initial void growth under EM, which is critical for measurement of the EM lifetime and statistics. A method based on analyzing the resistance traces obtained from EM tests of multi-link structures has been developed. The results indicated that there are three stages in the resistance traces where the rate of the initial void growth in Stage I is lower than that in Stage III after interconnect failure and they are linearly correlated. An analysis extending the Korhonen model has been formulated to account for the initial void formation. In this analysis, the stress evolution in the line during void growth under EM was analyzed in two regions and an analytic solution was deduced for the void growth rate. A Monte Carlo grain growth simulation based on the Potts model was performed to obtain grain structures for void growth analysis. The results from this analysis agreed reasonably well with the EM experiments. The next part of the dissertation is to study the size effect on the electron wind force for a thin film and for a line with a rectangular cross section. The electron wind force was modeled by considering the momentum transfer during collision between electrons and an atom. The scaling effect on the electron wind force was found to be represented by a size factor depending on the film/line dimensions. In general, the electron wind force is enhanced with increasing dimensional confinement. Finally, a process for fabrication of Si nanotrenches was developed for deposition of Cu nanolines with well-defined profiles. A self-aligned sub-lithographic mask technique was developed using polymer residues formed on Si surfaces during reactive ion etching of Si dioxide in a fluorocarbon plasma. This method was capable to fabricate ultra-narrow Si nanotrenches down to 20nm range with rectangular profiles and smooth sidewalls, which are ideal for studying EM damage mechanisms and model verification for future technology nodes. / text

Copper interconnect requires liner materials that function as a diffusion barrier, a seed layer for electroplating, and an adhesion promoting layer. Ruthenium has been considered as a promising liner material, however it has been reported that Ru itself is not an effective Cu diffusion barrier due to its microstructure, which is polycrystalline with columnar grains. The screening study of Ru precursors revealed that all Ru films were polycrystalline with columnar structure, and, due to its strong 3D growth mode, a conformal and ultrathin Ru film was difficult to form, especially on high aspect ratio features. The microstructure of Ru films can be modified by incorporating P. Amorphous Ru(P) films are formed by chemical vapor deposition at 575 K using a single source precursor, cis-RuH₂(P(CH₃)₃)₄, or dual sources, Ru₃(CO)₁₂ and P(CH₃)₃ or P(C6H5)₃ The films contain Ru and P, which are in zero-valent states, and C as an impurity. Phosphorus dominantly affects the film microstructure, and incorporating > 13% P resulted in amorphous Ru(P) films. Metastable Ru(P) remains amorphous after annealing at 675 K for 3 hr, and starts recrystallization at ~775 K. The density of states analysis of the amorphous Ru(P) alloy illustrates metallic character of the films, and hybridization between Ru 4d and P 3p orbitals, which contributes to stabilizing the amorphous structure. Co-dosing P(CH)₃ with Ru₃(CO)₁₂ improves film step coverage, and the most conformal Ru(P) film is obtained with cis-RuH2(P(CH₃)₃)₄; a fully continuous 5 nm Ru(P) film is formed within 1 µm deep, 8:1 aspect ratio trenches. First principles density functional theory calculations illustrate degraded Cu/Ru adhesion by the presence of P at the interface, however, due to the strong Ru-Cu bonds, amorphous Ru(P) forms a stronger interface with Cu than Ta and TaN do. Cu diffusion studies at 575 K suggests improved barrier property of amorphous Ru(P) films over polycrystalline PVD Ru.

M. Tech. Metallurgical Engineering. / Aims at improving Cu interconnection problem by homogeneous distribution of ruthenium and tantalum in Cu matrix for excellent interconnection in electronics packaging. The aim will be achieved through the following objectives.Development of appropriate technology for homogenizing submicron metal powders with suitable methods for controlling grain growth during sintering. Study the mechanisms of synergistic incorporation of Ru, and Ta on improving copper interconnection properties. To investigate metallurgical interactions and phenomena occurring during sintering. To investigate specific property and behaviour advantages intrinsic due to the composites and material mix.

Disertacijos darbo tikslas buvo, modeliuojant bei vykdant eksperimentus, suprasti plonų sluoksnių, naudojamų Saulės elementuose, abliacijos procesus ultratrumpais impulsais, siekiant juos pritaikyti integruotų jungčių fotovoltiniuose moduliuose formavimui. Eksperimento rezultatams pagrysti buvo vykdomas lazerio spinduliuotės sklidimo bei pasiskirstymo plonasluoksnėje Saulės elemento struktūroje modeliavimas. Sugerta lazerio energija lokaliai užkaitiną medžiagą. Kadangi lazerinio proceso selektyvumas priklauso nuo medžiagos optinių savybių, todėl yra itin svarbu parinkti tinkamą lazerio spinduliuotės bangos ilgį, norint sukaupti spinduliuotę reikiamame plonasluoksnės struktūros sluoksnyje. Nustatyta, kad fundamentinė pikosekundinio lazerio spinduliuotė (1064 nm) yra optimaliausia P3 tipo rėžio formavimui CIGS Saulės elemente. Pramonės taikymams tai yra itin svarbu, nes tokiu atveju mažėja industrinės lazerinės sistemos sudėtingumas bei kaina. Saulės elementų efektyvumo tyrimai parodė nežymų fotoelektrinio efektyvumo sumažėjimą po lazerinio apdirbimo ultra trumpais impulsais, tačiau nebuvo užfiksuota defektų generacijos lazeriais paveiktose kanalo kraštų zonose. Disertacijoje pasiūlyti ir išbandyti pluošto formavimo ir lygiagretaus sluoksnių raižymo metodai, didinantys proceso našumą ir raižymo kokybę. Pikosekundiniai, didelio impulsų pasikartojimo dažnio lazeriai gali būti panaudoti didelės spartos bei aukštos kokybės Saulės elementų raižymo procesuose. / Present PhD thesis is the experimental and theoretical analysis of thin layer ultrashort pulsed laser ablation processes for photovoltaic devices. Experimental work was supported by modeling and simulation of energy coupling and dissipation inside the layers. The absorbed laser energy was transformed to localized transient heating inside the structure. Selectiveness of the ablation process was defined by optical and mechanical properties of the materials, and selection of the laser wavelength facilitated control of the structuring process. The 1064 nm wavelength was found optimal for the CIGS solar cell scribing in terms of quality and process speed. It is very positive result for industrial applications as the cost and the system complexity are decreased. The solar cell efficiency test revealed minor degradation in photo-electrical efficiency after the laser scribing was applied to the solar cell samples. Lock-in thermography measurements did not revealed any internal shunt formation during laser scribing with picosecond pulse duration. Picosecond lasers with fundamental harmonics and high repetition rates can be used to accomplish efficient and fast scribing process which is able to fit the demands for industrial solar cell scribing applications.