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Amplificador de baixo ruído totalmente integrado em CMOSEsteves Távora, Filipe 31 January 2010 (has links)
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Previous issue date: 2010 / Esta dissertação descreve o projeto de dois amplificadores de baixo ruído (LNA),
que é um dos blocos mais relevantes do sistema de recepção de rádio frequencia. Os
circuitos, desenvolvidos em tecnologia CMOS 0,35 m da (Austria Micro System),
foram baseados na norma IEEE 802.15.4 para serem aplicados a sistemas de redes de
sensores sem fio.
Apresenta-se uma dedução detalhada do fator de ruído para a configuração de
fonte comum com degeneração indutiva, incluindo o ruído induzido no gate e o ruído
devido a resistência parasita do gate, bem como duas adaptações de uma técnica de
otimização para a figura de ruído em função do tamanho do transistor e da indutância
de gate.
Por fim, são apresentados dois casos de testes para operar em 915 MHz com seus
desempenhos vericados através de simulações
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Multi-Band Multi-Standard CMOS Receiver Front-Ends for 4G Mobile ApplicationsRodriguez Duenas, Saul Alejandro January 2009 (has links)
The development of the transistor and its continuous down-scaling has allowed during the last decades the appearance of cheap wireless communication systems targeting consumer products. The complexity of these systems has increased dramatically during the last years, mainly fueled by both the Moore law and improvements in communication theory. Originally, the radio transceivers were composed of only a few transistors, and supported simple analog modulation schemes. Currently, radio transceivers are composed of thousands of transistors including not only radio/analog blocks but also a huge amount of digital circuitry as well. These radios use advanced digital modulation schemes, channel coding, and multiple access schemes. Despite the fact that digital circuits currently offer an impressive performance, pure digital signal processing of radio signals remains limited for relatively low frequencies below a few hundred MHz. On the other hand, frequency bands used in current mobile applications span from around 800MHz up to 6 GHz and hence demand the use of analog circuits to down-convert the radio signals to lower frequencies that are suitable for digital processing. The group of circuits that form this part of the receiver is known as the radio receiver front-end. The design of modern radio receiver front-ends has many challenges. One requirement is support of a multitude of standards with bands that are scattered all along the mobile radio spectrum. Accordingly, the noise and linearity specifications for these front-ends are very stringent. Also, these specifications have to be accomplished using low-power, low-cost, highly integrated circuit solutions. This thesis presents the design of multi-band multi-standard receiver front-ends for fourth generation mobile communications. A novel methodology that speeds up the development of multi-band multi-standard RF blocks by automating some steps in the design is shown. Examples of submicron and nanometer CMOS wideband receiver front-ends targeting 4G mobile applications are presented. New techniques for inductorless wideband front-ends using current-mode technology are presented. Finally, novel RF calibration techniques to cope with process, voltage, and temperature variations in modern CMOS processes are demonstrated. / QC 20100806 / RaMSiS
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Radio frequency circuits for wireless receiver front-endsXin, Chunyu 01 November 2005 (has links)
The beginning of the 21st century sees great development and demands on wireless communication technologies. Wireless technologies, either based on a cable replacement or on a networked environment, penetrate our daily life more rapidly than ever. Low operational power, low cost, small form factor, and function diversity are the crucial requirements for a successful wireless product. The receiver??s front-end circuits play an important role in faithfully recovering the information transmitted through the wireless channel.
Bluetooth is a short-range cable replacement wireless technology. A Bluetooth receiver architecture was proposed and designed using a pure CMOS process. The front-end of the receiver consists of a low noise amplifier (LNA) and mixer. The intermediate frequency was chosen to be 2MHz to save battery power and alleviate the low frequency noise problem. A conventional LNA architecture was used for reliability. The mixer is a modified Gilbert-cell using the current bleeding technique to further reduce the low frequency noise. The front-end draws 10 mA current from a 3 V power supply, has a 8.5 dB noise figure, and a voltage gain of 25 dB and -9 dBm IIP3.
A front-end for dual-mode receiver is also designed to explore the capability of a multi-standard application. The two standards are IEEE 802.11b and Bluetooth. They work together making the wireless experience more exciting. The front-end is designed using BiCMOS technology and incorporating a direct conversion receiver architecture. A number of circuit techniques are used in the front-end design to achieve optimal results. It consumes 13.6 mA from a 2.5 V power supply with a
5.5 dB noise figure, 33 dB voltage gain and -13 dBm IIP3.
Besides the system level contributions, intensive studies were carried out on the development of quality LNA circuits. Based on the multi-gated LNA structure, a CMOS LNA structure using bipolar transistors to provide linearization is proposed. This LNA configuration can achieve comparable linearity to its CMOS multi-gated counterpart and work at a higher frequency with less power consumption. A LNA using an on-chip transformer source degeneration is proposed to realize input impedance matching. The possibility of a dual-band cellular application is studied. Finally, a study on ultra-wide band (UWB) LNA implementation is performed to explore the possibility and capability of CMOS technology on the latest UWB standard for multimedia applications.
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An Electronically Reconfigurable Three Band Low-Noise Amplifier in 0.5 μm GaAs pHEMT TechnologyShatzman, Jeffrey A 01 January 2011 (has links) (PDF)
State-of-the-art RF front-end circuits are typically designed to operate at a single frequency. With an increasing number of available wireless standards, personal mobile communication devices require an increasing number of individually designed RF circuits. To save space and cost, one alternative possibility is to reuse much of the circuitry by utilizing electronically reconfigurable topologies. The ubiquitous low-noise amplifier is one of the many circuits that can be redesigned with the reconfigurable aspect in mind. In this thesis, previous work in reconfigurable LNAs is reviewed as well as a brief comparison of CMOS and GaAs processes used for RF amplifiers. Three new reconfigurable LNA topologies are also presented. The first two topologies, based on the common-gate stage and synchronous filters, are investigated but not manufactured. The third design, based on the cascode topology, was manufactured in a 0.5 µm GaAs process with enhancement-mode and depletion-mode pHEMTs. The LNA features 12.7 dB, 13.6 dB, and 13.9 dB of gain and noise figures of 2.7 dB, 3.5 dB, and 4.2 dB at 2.5, 3.6 and 5.8 GHz, respectively. The LNA draws 41 mA from a 3.3 V supply.
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Silicon Germanium (SiGe) Bipolor Dicke Radiometer Front End Receiver ChipWolf, Randy L 01 January 2008 (has links) (PDF)
Radiometers measures background radiation noise power of a target. The dominant quality factor of the radiometer is determined by how sensitive it is, so the lower the noise figure and the higher the gain, the more sensitive it is. It must also calibrate out any interfering noise such as sky background and system noise. Any change in gain of the radiometer receiver must also be taken into account. A Dicke radiometer compensates system gain and noise variation by switching between the target and a known noise source. To accomplish this, a single pole, double throw (SPDT) switch, switches between the receiving antenna and the noise source. The common terminal of the switch goes to the input of the low noise amplifier (LNA). This switch has a noise figure approximately equivalent to its loss and its noise is amplified by the LNA. To eliminate the loss of the switch, this paper studies a new approach of combining the switch and the LNA to become a “switchable” LNA by designing a two-stage gain block with the first stage capable of switching between the two inputs. Because the first stage is amplifying, there is no signal loss. This thesis investigates the new switching LNA and the design approach used in choosing the technology, the transistor size, biasing, extractions and matching. Two variations of the design were built using IBM’s SiGe 8HP 120nm process. The expected and measured results are compared. Results show a measured gain of 10dB and noise figure of 5dB at 19GHz. These results fall short of expectations for reasons explained in the thesis. The overall performance of this switching LNA is compared to the traditional methods. Performance criteria include gain, noise figure, isolation, matching and linearity vs. frequency and their stability vs. power and temperature variation. Power consumption, physical size and cost are also considered. The degree to which the two inputs track one another is discussed.
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Etude de structures innovantes pour la réalisation d'amplificateur RF faible bruit sans inductance et à très faible consommation / Innovating Structures for Low Power & Inductorless RF Low Noise Amplifier (LNA).Belmas, Francois 22 March 2013 (has links)
La dernière décennie à vu l’explosion des technologies de communication sans fils. Les normes se sont multipliées de sorte que les fonctionnalités GSM, GPS, WIFI, Bluetooth et autres cohabitent parfois au sein du même terminal. Les réseaux de capteurs (Wireless area network WSN) incluant les réseaux de capteur WPAN (Wireless Personnel Area Network) seront amenés à jouer un rôle important dans l’environnement de demain au même titre que les normes sans fils grand public que nous venons de mentionner. Le déploiement de ces capteurs à grande échelle a été rendu possible par la réduction du coût de leur fabrication via la miniaturisation des procédés de fabrication propres à la technologie CMOS. Cependant, la consommation énergétique de ces circuits doit être très réduite permettant ainsi de fonctionner dans le cas où ces mêmes capteurs sont associés à une batterie compacte embarquée de durée de vie réduite. A défaut il serait nécessaire de pouvoir se contenter de l’énergie récupérable - en quantité limité - disponible dans l'environnement direct de ces capteurs. Cette contrainte de consommation électrique réduite ainsi que la nécessité de profiter au maximum de la miniaturisation du procédé CMOS amène à considérer la conception de circuits radio sous l'angle du faible encombrement surfacique et de la consommation statique la plus faible possible. Ces contraintes sont parfois contradictoires avec les architectures classiques connues de ces circuits radio constituants les capteurs déployés.es travaux présentés dans le cadre de cette thèse s’attachent à proposer des solutions afin de répondre à ces critères de consommation et de coût. Nous nous sommes intéressés au cas des amplificateurs faible bruit (Low Noise Amplifier – LNA) et à la possibilité de réaliser ce composant critique pour le lien RF sans utiliser d’inductance intégrées tout en limitant au maximum la consommation électrique. Plusieurs solutions innovantes ont été étudiées afin de répondre à cet objectif. Ces travaux nous ont conduit à la réalisation de plusieurs prototypes de circuits en technologie CMOS 65nm et 130nm qui permettent de comprendre les limites et les avantages d’une telle approche. La première partie présentera une première approche consistant à émuler une inductance à l’aide de composants actifs et ainsi à résoudre le problème de l’encombrement propre au inductance passives. Nous verrons en quoi cette approche peut présenter des limites pratiques pour une application radio. La seconde partie présentera la réalisation d’un LNA très basse consommation et large bande qui n’utilise pas d’inductance et présentant des performances améliorées vis à vis des topologies connues de LNA à faible consommation. Nous conclurons ensuite par les perspectives ouvertes suite à ces travaux et les autres approches possibles pour répondre aux contraintes de la basse consommation et du faible coût. / During the past decade the intense development of wireless technologies standard such as WIFI, GSM or Bluetooth reshaped the connectivity environment of any technology customers Among those standards, Wireless Sensor Networks (WSN) and Wireless Personal Area Network (WPAN) are expected to play a key role in our future environments. The large scale spreading of such sensors has been enabled through the strong cost optimization of modern CMOS technologies. The autonomy improvement of such sensor is however a primary concern to allow any kind of remote operation within the limitation of battery life. Even though the emerging energy harvesting domain offer energy friendly environments for such sensor, the electrical autonomy remain as a tight challenge to address. Those requirements of autonomy along with the context of CMOS technology development pushes sometimes fundamental contradictions between circuit's miniaturization and decreased power consumption. In this work, we propose solutions to address simultaneously those autonomy-miniaturization requirements. The study presented here is focused on Low Noise Amplifiers (LNA) and more precisely on the specific case of inductorless design of LNA. Several innovative solutions has been proposed and realized in 65nm & 130nm CMOS technologies in order to highlight the pros and the cons of such design approach. First part of this work is focused on the design of an active inductance to address the area occupation of narrow band system using inductors. We'll explain why such approach rises fundamental limits for radio application. Second part details the design of an ultra low power broadband LNA without inductors. The proposed circuits enable significant improvement in performance tradeoffs for such low power consumption in comparison with known design techniques. We will conclude with general perspectives and other possible design approaches.
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Étude expérimentale de la stabilité, sélectivité d'appariement et dynamique d'oligonucléotides DNA-DNA et LNA-DNABoccongelli, Marina 20 March 2008 (has links)
Le traitement et le diagnostic de maladies d'origine génétique suscite un grand intérêt à l'heure actuelle. De par leur spécificité d'appariement avec les acides nucléiques, les oligonucléotides possèdent un grand potentiel dans ce domaine. Ils se heurtent toutefois à des limitations majeures, dont leur faible stabilité en milieu physiologique et la difficulté qu'ils ont à franchir les membranes biologiques. De nombreuses équipes de recherche s'intéressent, afin de pallier ces limitations, à la conception et à la synthèse d'oligonucléotides chimiquement modifiés. Parmi ceux-ci, les Locked Nucleic Acids (LNA), présentant une modification qui consiste en l'insertion d'un pont −O−CH2− entre l'atome C2' et l'atome C4' du sucre, constituent une famille qui semble posséder les propriétés requises. Ils sont considérés comme des candidats très prometteurs en tant qu’agents thérapeutiques et qu’outils de diagnostic du génome. La caractérisation de la stabilité et de la sélectivité d'appariement entre les LNA et les acides nucléiques naturels est, dans ce contexte, important.
Dans ce travail, nous avons étudié la stabilité, la sélectivité d'appariement ainsi que la dynamique de la structure double brin d'un oligonucléotide hybride LNA-DNA, et nous avons comparé ces propriétés à celles d'un oligonucléotide DNA-DNA de même séquence. Ce dernier est constitué de 11 paires de bases formées par l'appariement du brin 5'-GCGTGTGTGCG-3' avec le brin 3'-CGCACACACGC-5'. Dans le cas de l'hybride, les nucléotides du second brin sont tous remplacés par des LNA.
La stabilité a été étudiée expérimentalement par différentes techniques : spectroscopie d'absorption UV, calorimétrie différentielle à balayage, résonance magnétique nucléaire et calorimétrie à titrage isotherme. Ces études montrent que la stabilité du duplexe hybride est plus importante que celle du naturel, et que ce phénomène s'explique par un terme entropique plus favorable pour la formation du duplexe LNA-DNA que pour la formation du duplexe DNA-DNA.
La sélectivité d'appariement a été étudiée en comparant la stabilité des deux oligonucléotides étudiés avec celle d'oligonucléotides présentant un mésappariement dans la séquence. Nos résultats montrent que la sélectivité d'appariement du brin LNA n'est pas significativement différente de celle du brin DNA. Ce résultat ne doit cependant pas être généralisé car nous n'avons testé qu'une position centrale pour le mésappariement.
L'étude de la dynamique de la structure des oligonucléotides a été effectuée par RMN et porte sur la caractérisation de la cinétique de l'ouverture individuelle des paires de bases. Nous observons que la durée de vie de l'état fermé des paires de bases G-C est supérieure dans l'oligonucléotide LNA-DNA, tandis que l'état fermé des paires A-T semble posséder une durée de vie supérieure dans l'oligonucléotide DNA-DNA.
Au cours de ce travail de thèse nous avons pu caractériser les facteurs énergétiques à la base de la stabilité accrue des oligonucléotides chimiquement modifiés de type LNA. Nous avons montré que leur sélectivité d’appariement n’est pas toujours supérieure à celle des oligonucléotides naturels et dépend des séquences impliquées. Enfin, nous avons mis en évidence les différences entre la dynamique de la structure d’un oligonucléotide possédant des LNA et celle d’un duplexe DNA.
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Parameter Estimation of a High Frequency Cascode Low Noise Amplifier ModelWang, Kefei 05 October 2012 (has links)
"A Low Noise Amplifier (LNA) is an important building block in the RF receiver chain. Typically the LNA should provide acceptable gain and high linearity while maintaining low noise and power consumption. To optimize these conflicting goals the so-called Cascode topology is widely used in industry. Here the gain cell is comprised of two transistors, one in common-source and the other in common gate configuration. Cascode has a number of competitive advantages over other topologies such as high output impedance that shields the input device from voltage variations at the output, good reverse isolation resulting in improved stability, and acceptable input matching. Moreover, the topology features excellent frequency characteristics. Unfortunately, a Cascode design is expensive to deploy in RF systems and it requires more careful tuning and matching. Since the design relies on many circuit components, optimization methods are generally difficult to implement and often inaccurate in their predictions. To overcome these problems, this thesis proposes a modeling environment within the Advanced Design Systems (ADS) simulator that utilized DC and RF measurements in an effort to characterize each transistor separately. The model creates an easy-to-apply design approach capable of predicting the most important circuit components of the Cascode topology. The validity of the method is tested in ADS with a realistic p-HEMT library device. The comparison between model prediction and the realistic device involves both standard transistor parameters and high-frequency parasitic effects. "
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Systematic Analysis and Optimization of Broadband Noise and Linearity in SiGe HBTsLiang, Qingqing 06 January 2005 (has links)
Noise and linearity are the two key concerns in RF transceiver systems. However, the impact of circuit topology and device technology on systems noise and linearity behaviors is poorly understood because of the complexity and diversity involved. There are two general questions that are addressed by the RF device and circuit designers: for a given device technology, how best to optimize the circuit topology; and for a given circuit topology, how best to optimize the device technology to improve the noise and linearity performance.
In this dissertation, a systematic noise and linearity calculation method is proposed. This approach offers simple and analytical solutions to optimize the noise and linearity characteristics of integrated circuits. Supported by this approach, the physics of state-of-the-art SiGe HBT technology devices can be decoupled and studied. The corresponding impact on noise and linearity is investigated. New optimization methodologies for noise and linearity at both the device and circuit level are presented.
In addition, this thesis demonstrates a technique that accurately extracts ac and noise parameters of devices/circuits in the millimeter-wave range. The extraction technique supports and verifies the device/circuit noise analysis from a measurement standpoint.
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A 3.1~10.6 GHz UWB Low Noise AmplifierHsieh, Yi-Lung 27 July 2011 (has links)
The main contents of this thesis are improving a UWB LNA, and analyze the input-matching, the noise, and the gain.
First we increase the width of the input transistor, and remove source-degeneration inductor. Those ways can increase the gain and reduce the noise of the circuit. In the input matching, we use a shunt capacitor, a series inductor, and the impedance of the transistor itself to achieve high frequency matching. The lower frequency matching is achieved by negative feedback resistor.
The UWB LNA dissipates 10.14 mW power and achieves input return loss (S11) below -11.5 dB, output return loss (S22) below -11.9 dB, forward gain (S21) of 14.4¡Ó0.4 dB, reverse isolation (S12) below -26.7 dB, and noise figure (NF) of 2.6~3.5 dB over the 3.1~10.6 GHz band of interest. 1-dB compression point (P1dB) of -16.8 dBm and input third-order inter-modulation point (IIP3) of -8.1 dBm are achieved at 6.85 GHz.
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