The objective of manufacturing test is to separate the faulty circuits from the good circuits after they have been manufactured. Three problems encompassed by this task will be mentioned here. First, the reduction of the power consumed during test. The behavior of the circuit during test is modified due to scan insertion and other testing techniques. Due to this, the power consumed during test can be abnormally large, up to several times the power consumed during functional mode. This can result in a good circuit to fail the test or to be damaged due to heating. Second, how to modify the design so that it is easily testable. Since not every possible digital circuit can be tested properly it is necessary to modify the design to alter its behavior during test. This modification should not alter the functional behavior of the circuit. An example of this is test point insertion, a technique aimed at reducing test time and decreasing the number of faulty circuits that pass the test. Third, the creation of a test set for a given design that will both properly accomplish the task and require the least amount of time possible to be applied. The precision in separation of faulty circuits from good circuits depends on the application for which the circuit is intended and, if possible, must be maximized. The test application time is should be as low as possible to reduce test cost. This dissertation contributes to the discipline of manufacturing test and will encompass advances in the afore mentioned areas. First, a method to reduce the power consumed during test is proposed. Second, in the design modification area, a new algorithm to compute test points is proposed. Third, in the test set creation area, a new algorithm to reduce test set application time is introduced. The three algorithms are scalable to current industrial design sizes. Experimental results for the three methods show their effectiveness.

The growing market of portable devices and smart wearables has contributed to innovation and development of systems with longer battery-life. While Near Threshold Computing (NTC) systems address the need for longer battery-life, they have certain limitations. NTC systems are prone to be significantly affected by variations in the fabrication process, commonly called process variation (PV). This dissertation explores an intriguing effect of PV, called choke points. Choke points are especially important due to their multifarious influence on the functional correctness of an NTC system. This work shows why novel research is required in this direction and proposes two techniques to resolve the problems created by choke points, while maintaining the reduced power needs.

<p>In wireless communication there is commonly much unnecessarycommunication made in directions not pointing towards the recipient. Normallyomni directional antennas are being used which sends the same amount ofenergy in all directions equally. This waste of energy reduces the lifetime ofbattery powered units and causes more traffic collisions than necessary. Oneway of minimizing this wasted energy and traffic collisions, is to use anothertype of antenna called “smart antenna”. These antennas can use selectableradiation patterns depending on the situation and thus drastically minimize theunnecessary energy waste. Smart antennas also provide the ability to sense thedirection of incoming signals which is favorable for physical layout mappingsuch as orientation.This thesis presents the prototyping of a new type of smart antenna called theSPIDA smart antenna. This antenna is a cheap to produce smart antennadesigned for the 2.4 GHz frequency band. The SPIDA smart antenna can usesixty-four different signal patterns with the control of six separate directionalmodes, amongst these patterns are six single direction patterns, an omnidirectionalsignal pattern and fifty-six combi-direction patterns. The thesispresents complete building instructions, evaluation data and functional driversfor the SPIDA smart antenna.</p>

<p>Since their rediscovery in 1995, low-density parity-check (LDPC) codes have received wide-spread attention as practical capacity-approaching code candidates. It has been shown that the class of codes can perform arbitrarily close to the channel capacity, and LDPC codes are also used or suggested for a number of important current and future communication standards. However, the problem of implementing an energy-efficient decoder has not yet been solved. Whereas the decoding algorithm is computationally simple, withuncomplicated arithmetic operations and low accuracy requirements, the random structure and irregularity of a theoretically well-defined code does not easily allow efficient VLSI implementations. Thus the LDPC decoding algorithm can be said to be communication-bound rather than computation-bound.</p><p>In this thesis, a modification to the sum-product decoding algorithm called early-decision decoding is suggested. The modification is based on the idea that the values of the bits in a block can be decided individually during decoding. As the sum-product decoding algorithm is a soft-decision decoder, a reliability can be defined for each bit. When the reliability of a bit is above a certain threshold, the bit can be removed from the rest of the decoding process, and thus the internal communication associated with the bit can be removed in subsequent iterations. However, with the early decision modification, an increased error probability is associated. Thus, bounds on the achievable performance as well as methods to detect graph inconsistencies resulting from erroneous decisions are presented. Also, a hybrid decoder achieving a negligible performance penalty compared to the sum-product decoder is presented. With the hybrid decoder, the internal communication is reduced with up to 40% for a rate-1/2 code with a length of 1152 bits, whereas increasing the rate allows significantly higher gains.</p><p>The algorithms have been implemented in a Xilinx Virtex 5 FPGA, and the resulting slice utilization andenergy dissipation have been estimated. However, due to increased logic overhead of the early decision decoder, the slice utilization increases from 14.5% to 21.0%, whereas the logic energy dissipation reduction from 499 pJ to 291 pJ per iteration and bit is offset by the clock distribution power, increased from 141 pJ to 191 pJ per iteration and bit. Still, the early decision decoder shows a net 16% estimated decrease of energy dissipation.</p>

<p>In recent years, the drive for ever increasing energy efficiency has intensified. The main driving forces behind this development are the increased innovation and adoption of mobile battery powered devices, increasing energy costs, environmental concerns, and strive for denser systems.</p><p>This work is meant to serve as a foundation for exploration of energy conscious software. We present an overview of previous work and a background to energy concerns from a software perspective. In addition, we describe and test a few methods for decreasing energy consumption with emphasis on using software parallelism. The experiments are conducted using both a simulation environment and real hardware. Finally, a method for measuring energy consumption on a hardware platform is described.</p><p>We conclude that energy conscious software is very dependent on what hardware energy saving features, such as frequency scaling and power management, are available. If the software has a lot of unnecessary, or overcomplicated, work, the energy consumption can be lowered to some extent by optimizing the software and reducing the overhead. If the hardware provides software-controllable energy features, the energy consumption can be lowered dramatically.</p><p>For suitable workloads, using parallelism and multi-core technologies seem very promising for producing low power software. Realizing this potential requires a very flexible hardware platform. Most important is to have fine grained control over power management, and voltage and frequency scaling, preferably on a per core basis.</p>

<p>Multiplication is an important part of real-time system applications. Various hardware parallel multipliers used in such applications have been proposed. However, when the operand sizes of the multipliers and the process technology need to be changed, the existing multipliers have to be redesigned. </p><p>From the point of library cell reuse, this master thesis work aims at developing a module generator for parallel multipliers with the help of software programs. This generator can be used to create the gate-level schematic for fixed point two's complement number multipliers. Based on the generated schematic, the entire multiplier can be implemented by small manual intervention. This feature can reduce the time of chip design. </p><p>The design phases consist of the logic, circuit and physical designs. The logic design includes gate-level schematic generation with C and SKILL programs and structural VHDL-code descriptions as well as validation. The circuit and physical design are custom in Cadence and the routing uses automatic place and route tools. </p><p>To demonstrate the design method, an 18 by 18-bit modified Booth recoded multiplier was implemented in 0.18 µm CMOS process with a supply voltage of 1.2 V and simulated using simulator (Spectre). The number of integrated transistors is 13000 and the active area is 85000 µm². The postlayout simulation shows the critical path with a delay of 17 ns.</p>

<p>In order to convert the analog information in the digital domain, pipelined analog-to-digital converter (ADC) offers an optimum balance of resolution, speed, power consumption, size and design effort.</p><p>In this thesis work we design and optimize a 8-bit pipelined ADC for low-power. The ADC has stage resolution of 1.5-bit and employ current mode multiplying analog-to-digital converter (MDAC). The main focus is to design and optimize the MDAC. Based on the analysis of "On current mode circuits" discussed in chapter 2, we design and optimize the MDAC circuit for the best possible effective number of bits (ENOB), speed and power consumption. Each of the first six stages consisting of Sample-and-Hold, 1.5-bit flash ADC and MDAC is realized at the circuit level. The last stage consisting of 2-bit flash ADC is also realized at circuit level. The delay logic for synchronization is implemented in Verilog-A and MATLAB. A first order digital error-correction algorithm is implemented in MATLAB.</p><p>The design is simulated in UMC 0.18um technology in Cadence environment. The choice of technology is made as the target application for the ADC, 'X-ray Detector System' is designed in the same technology. The simulation results obtained in-term of ENOB and power consumption are satisfactory for the target application.</p>

<p>This thesis explores the energy-delay space of eight widely referred flip-flops in a 0.13µm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on the comparison results, transmission gate-based flip-flops show the best powerperformance trade-offs with a total delay (clock-to-output + setup time) down to 105ps. For higher performance, the pulse-triggered flip-flops are the fastest (80ps) alternatives suitable to be included in a flip-flop cell library. However, pulse-triggered flip-flops consume significantly larger power (about 2.5x) compared to other fast but fully dynamic flip-flops such as TSPC and dynamic TG-based flip-flops.</p>

<p>In this work, an existing generator for layout of Static Random Access Memory (SRAM) is improved. The tool is completed with a block decoder, which was missing when the thesis started. A feature of generating schematic files is also added. The schematics are important to get a better overview, to test parts properly, and enable Layout versus Schematics (LVS) checks.</p><p>The main focus of this thesis work is to implement and evaluate a new SRAM cell, called Zero Aware Asymmetric SRAM cell. This cell saves major power when zeros are stored. Furthermore the pull-up circuit is modified to be less power consuming. Other parts are also modified to fit the new memory cell.</p><p>Several minor flaws are corrected in the layout generator. It does still not produce a complete memory without manual interventions, but it does at least create all parts with one command. Several tests, including Design Rule Checks (DRC) and LVS checks, are carried out both on minor and larger parts. Development of documentation that makes it easier for users and developers to use and understand the tool is initiated.</p>

<p>The development of integrated circuit technology seen in the last decades has enabled a large variety of battery operated equipment to emerge, such as smallsensors and medical implants. These applications often has low requirements on sampling frequency but require a very low power consumption to achieve a longbattery life.</p><p>This thesis investigates one aspect of implementing a low power and low frequency analog to digital converter (ADC) using a technique called Sigma Delta-modulation.The Sigma Delta-ADC uses few analog components but instead it requires a digital filter to extract the wanted resolution. It is this filter which is under investigation in this work.</p><p>To investigate the power consumption under the presumption that the filter would be a custom circuit implemented on-chip, a simplistic approach has been taken. Based on a high-level algorithmic investigation and the fact that it is popularly used together with Sigma Delta-modulators the Cascaded Integrator Comb (CIC) filter was chosen for implementation.</p><p>The CIC-filter uses only adders and delay elements which is a great advantage when aiming at a low power consumption. The drawback is that this filter has a poor passband which can introduce distortion within the signal band. Using the Spectre simulator provided in the Cadence Virtuoso suite the lowest power consumption achieved was 16 nW, extracting 80 % of the theoretically available resolution.</p>