Real world is analog but the processing of signals can best be done in digital domain. So the need for Analog to Digital Converters(ADCs) is ever rising as more and more applications set in. With the advent of mobile technology, power in electronic equipment is being driven down to get more battery life. Because of their ubiquitous nature, ADCs are prime blocks in the signal chain in which power is intended to be reduced. In this thesis, four techniques to reduce power in high speed pipelined ADCs have been proposed. The first is a capacitor and opamp sharing technique that reduces the load on the first stage opamp by three fold. The second is a capacitor reset technique that aids removing the sample and hold block to reduce power. The third is a modified MDAC which can take rail-to-rail input swing to get an extra bit thus getting rid of a power hungry opamp. The fourth is a hybrid architecture which makes use of an asynchronous SAR ADC as the backend of a pipelined ADC to save power. Measurement and simulation results that prove the efficiency of the proposed techniques are presented. / Graduation date: 2009

University of Macau / Faculty of Business Administration / Department of Management and Marketing

CDMA channel selection requires sharp as well as wide-band Filtering. SAW Filters which have been used for this purpose are only available in IF range. In direct conversion receivers this has to be done at low frequencies. Switched Capacitor technique has been employed to design a low power, highly selective low-pass channel select Filter for CDMA wireless receivers. The topology which has been chosen ensures the low sensitivity of the Filter response. The circuit has been designed in a mixed-mode 0. 18u CMOS technology working with a single supply of 1. 8 V while its current consumption is less than 10 mA.

CDMA channel selection requires sharp as well as wide-band Filtering. SAW Filters which have been used for this purpose are only available in IF range. In direct conversion receivers this has to be done at low frequencies. Switched Capacitor technique has been employed to design a low power, highly selective low-pass channel select Filter for CDMA wireless receivers. The topology which has been chosen ensures the low sensitivity of the Filter response. The circuit has been designed in a mixed-mode 0. 18u CMOS technology working with a single supply of 1. 8 V while its current consumption is less than 10 mA.

Bandgap reference circuits are used in a host of analog, digital, and mixed-signal systems to establish an accurate voltage standard for the entire IC. The accuracy of the bandgap reference voltage under steady-state (dc) and transient (ac) conditions is critical to obtain high system performance. In this work, the impact of process, power-supply, load, and temperature variations and package stresses on the dc and ac accuracy of bandgap reference circuits has been analyzed. Based on this analysis, the a bandgap reference that 1. has high dc accuracy despite process and temperature variations and package stresses, without resorting to expensive trimming or noisy switching schemes, 2. has high dc and ac accuracy despite power-supply variations, without using large off-chip capacitors that increase bill-of-material costs, 3. has high dc and ac accuracy despite load variations, without resorting to error-inducing buffers, 4. is capable of producing a sub-bandgap reference voltage with a low power-supply, to enable it to operate in modern, battery-operated portable applications, 5. utilizes a standard CMOS process, to lower manufacturing costs, and 6. is integrated, to consume less board space has been proposed. The functionality of critical components of the system has been verified through prototypes after which the performance of the complete system has been evaluated by integrating all the individual components on an IC. The proposed CMOS bandgap reference can withstand 5mA of load variations while generating a reference voltage of 890mV that is accurate with respect to temperature to the first order. It exhibits a trimless, dc 3-sigma accuracy performance of 0.84% over a temperature range of -40°C to 125°C and has a worst case ac power-supply ripple rejection (PSRR) performance of 30dB up to 50MHz using 60pF of on-chip capacitance. All the proposed techniques lead to the development of a CMOS bandgap reference that meets the low-cost, high-accuracy demands of state-of-the-art System-on-Chip environments.

This work consists of two main parts: i) Design and implementation of a compact current-reusing 2.4GHz direct-modulation transmitter with on-chip automatic tuning; ii) Design and implementation of a novel highly-reconfigurable, continuously tunable, power-adjustable Active-RC filter for multiple standards. The design, analysis, and experimental verification of a proposed self-calibrating, current reused 2.4GHz, direct-modulation transmitter are introduced. A stacked arrangement of the power amplifier/voltage-controlled oscillator is presented along with a novel LC-tank-tuning algorithm with a simple, low-cost, on-chip implementation. To transmit maximum power, the tuning loop ensures the PA's resonant tank is centered around the operating frequency, and the loop requires no ADC, DSP, or external signal generator. This work also details the proposed tuning-loop algorithm and examines the frequency-dependent nonlinear power-detector. The system was implemented in TSMC 0.18[mu]m CMOS, occupies 0.7 mm² (TX) + 0.1 mm² (self tuning), and was measured in a QFN48 package on FR4 PCB. Automatically adjusting the tank-tuning bits within their tuning range results in >4dB increase in output power. With the self-tuning circuit active, the transmitter delivers a measured output power of > 0dBm to a 100-[omega] differential load, and the system consumes 22.9 mA from a 2.2-V supply. A biquad design methodology and a baseband low-pass filter is presented for wireless and wireline applications with reconfigurable frequency response, selectable order (1st/3rd/5th), continuously tunable cutoff frequency (1MHz-20MHz) and adjustable power consumption (3mW-7.5mW). A discrete capacitor array coarsely tunes the low-pass filter, and a novel Continuous Impedance Multiplier (CIM) then finely tunes the filter. Resistive/capacitive networks select between the Chebyshev and Inverse Chebyshev approximation types. Also, a new stability metric for biquads, Minimum Acceptable Phase Margin (MAPM), is presented and discussed in the context of filter compensation and passband ripple considerations. Experimental results yield an IIP3 of 31.3dBm, a THD of -40dB at 447mV[subscript pk, diff] input signal amplitude, and a DR of 71.4dB. The filters tunable range covers frequencies from 1MHz to 20MHz. In Inverse Chebyshev mode, the filter achieves a passband group delay variation less than ±2:5%. The design is fabricated in 0.13[mu]m CMOS, occupies 1.53mm², and operates from a 1-V supply.

In this thesis, the conventional low voltage power line communication methods is investigated in the axis of automated meter reading applications and the classification and experimental verification of common noise types for low voltage power line communication network. The investigated system provides the real time transmission of electricity consumption data recorded by electricity meters, initially to a local computer via a low voltage line through a low speed PLC (Power Line Carrier) environment and subsequently to a corporate network through a high speed data transmission medium. The automated meter system provides a more effective tracking and data acquisition, a more detailed and vigorous knowledge about consumer behavior for subscriber assessment in electricity distribution in association with a brand new management and system supervision concept in electricity distribution control and management technology. The theoretical studies are experimentally verified for the Turkish low voltage power infrastructure through laboratory experiments performed in METU Electrical and Electronics Engineering Department, Electrical Machines and Drives Laboratory and R&amp / D Laboratories of MAKEL facilities in Hadimk&ouml / y. The single phase voltage of the mains line between the phase and neutral is monitored to exhibit the disturbing effects of various noise sources. The resulting voltage spectrum is logged by using digital data acquisition devices in time and frequency domain. The waveforms are converted to frequency domain using the Fast Fourier Transform (FFT) functions of the MATLAB. The experimental results are compared to the theoretical findings obtained through literature survey.

For many years batteries have been used as the main power sources for portable electronic devices. However, the rate of scaling in integrated circuits and micro-electro-mechanical systems (MEMS) has been much higher than that of the batteries technology. Therefore, a need to replace these temporary energy reservoirs with small sized continuously charged energy supply units has emerged. These units, named as energy harvesters, use several types of ambient energy sources such as heat, light, and vibration to provide energy to intelligent systems such as sensor nodes. Among the available types, vibration based electromagnetic (EM) energy harvesters are particularly interesting because of their simple structure and suitability for operation at low frequency values (&lt / 10 Hz), where most vibrations exits. However, since the generated EM power and voltage is relatively low at low frequencies, high performance interface electronics is required for efficiently transferring the generated power from the harvester to the load to be supplied. The aim of this study is to design low power and efficient interface electronics to convert the low voltage and low power generated signals of the EM energy harvesters to DC to be usable by a real application. The most critical part of such interface electronics is the AC/DC converter, since all the other blocks such as DC/DC converters, power managements units, etc. rely on the rectified voltage generated by this block. Due to this, several state-of-the-art rectifier structures suitable for energy harvesting applications have been studied. Most of the previously proposed rectifiers have low conversion efficiency due to the high voltage drop across the utilized diodes. In this study, two rectifier structures are proposed: one is a new passive rectifier using the Boot Strapping technique for reducing the diode turn-on voltage values / the other structure is a comparator-based ultra low power active rectifier. The proposed structures and some of the previously reported designs have been implemented in X-FAB 0.35 &micro / m standard CMOS process. The autonomous energy harvesting systems are then realized by integrating the developed ASICs and the previously proposed EM energy harvester modules developed in our research group, and these systems have been characterized under different electromechanical excitation conditions. In this thesis, five different systems utilizing different circuits and energy harvesting modules have been presented. Among these, the system utilizing the novel Boot Strap Rectifier is implemented within a volume of 21 cm3, and delivers 1.6 V, 80 &micro / A (128 &micro / W) DC power to a load at a vibration frequency of only 2 Hz and 72 mg peak acceleration. The maximum overall power density of the system operating at 2 Hz is 6.1 &micro / W/cm3, which is the highest reported value in the literature at this operation frequency. Also, the operation of a commercially available temperature sensor using the provided power of the energy harvester has been shown. Another system utilizing the comparator-based active rectifier implemented with a volume of 16 cm3, has a dual rail output and is able to drive a 1.46 V, 37 &micro / A load with a maximum power density of 6.03 &micro / W/cm3, operating at 8 Hz. Furthermore, a signal conditioning system for EM energy harvesting has also been designed and simulated in TSMC 90 nm CMOS process. The proposed ASIC includes a highly efficient AC-DC converter as well as a power processing unit which steps up and regulates the converted DC voltages using an on-chip DC/DC converter and a sub-threshold voltage regulator with an ultra low power management unit. The total power consumption on the totally passive IC is less than 5 &micro / W, which makes it suitable for next generation MEMS-based EM energy harvesters. In the frame of this study, high efficiency CMOS rectifier ICs have been designed and tested together with several vibration based EM energy harvester modules. The results show that the best efficiency and power density values have been achieved with the proposed energy harvesting systems, within the low frequency range, to the best of our knowledge. It is also shown that further improvement of the results is possible with the utilization of a more advanced CMOS technology.

This thesis presents circuit-level techniques for soft error mitigation, low-power design with performance trade-off, and variation-tolerant low-power design. The proposed techniques are divided into two broad categories. First, error compensation techniques, which are used for soft error mitigation and also for low-power operation of linear and non-linear filters. Second, a framework for variation tolerant low-power operation of wireless devices is presented. This framework analyzes the effects of circuit "tuning knobs" such as voltage, frequency, wordlength precision, etc. on system performance, and power efficiency. Process variations are considered as well, and the best operating tuning knob levels are determined, which results in maximum system wide power savings while keeping the system performance within acceptable limits. Different methods are presented for variation-tolerant and power-efficient wireless communication. Techniques are also proposed for application driven low-power operation of the OFDM baseband receiver.

ABSTRACT Federal regulations have recognized that arc flash hazards are a critical source of potential injury. As a consequence, in order to work on some electrical equipment, the energy source must be completely shut-down. However, power distribution systems in mission critical facilities such as hospitals and data centers must sometimes remain energized while being maintained. In recent years the Arc Flash Hazard Analysis has emerged as a power system tool that informs the qualified technician of the incident energy at the equipment to be maintained and recommends the proper protective equipment to wear. Due to codes, standards and historically acceptable design methods, the Arc Flash Hazard is often higher and more dangerous than necessary. This dissertation presents detailed methodology and proposes alternative strategies to be implemented at the design stage of 600 volt facility power distribution systems which will decrease the Arc Flash Hazard Exposure when compared to widely used code acceptable design strategies. Software models have been developed for different locations throughout a power system. These software model simulations will analyze the Arc Flash Hazard in a system designed with typical mainstream code acceptable methods. The model will be changed to show implementation of arc flash mitigation techniques at the system design level. The computer simulations after the mitigation techniques will show significant lowering of the Arc Flash Hazard Exposure.