This thesis presents a study of impedance optimisation of active microstrip patch antennas to multiple frequency points. A single layered aperture coupled microstrip patch antenna has been optimised to match the source reflection coefficient of a transistor in designing an active antenna. The active aperture coupled microstrip patch antenna was optimised to satisfy Global Positioning System (GPS) frequency specifications. A rudimentary aperture coupled microstrip patch antenna consists of a rectangular antenna element etched on the top surface of two dielectric substrates. The substrates are separated by a ground plane and a microstrip feed is etched on the bottom surface. A rectangular aperture in the ground plane provides coupling between the feed and the antenna element. This type of antenna, which conveniently isolates any circuit at the feed from the antenna element, is suitable for integrated circuit design and is simple to fabricate. An active antenna design directly couples an antenna to an active device, therefore saving real estate and power. This thesis focuses on designing an aperture coupled patch antenna directly coupled to a low noise amplifier as part of the front end of a GPS receiver. In this work an in-house software package, dubbed ACP by its creator Dr Rod Waterhouse, for calculating aperture coupled microstrip patch antenna performance parameters was linked to HP-EEsof, a microwave computer aided design and simulation package by Hewlett-Packard. An ANSI C module in HP-EEsof was written to bind the two packages. This process affords the client the benefit of powerful analysis tools offered in HP-EEsof and the fast analysis of ACP for seamless system design. Moreover, the optimisation algorithms in HP-EEsof were employed to investigate which algorithms are best suited for optimising patch antennas. The active antenna design presented in this study evades an input matching network, which is accomplished by designing the antenna to represent the desired source termination of a transistor. It has been demonstrated that a dual-band microstrip patch antenna can be successfully designed to match the source reflection coefficient, avoiding the need to insert a matching network. Maximum power transfer in electrical circuits is accomplished by matching the impedance between entities, which is generally acheived with the use of a matching network. Passive matching networks employed in amplifier design generally consist of discrete components up to the low GHz frequency range or distributed elements at greater frequencies. The source termination for a low noise amplifier will greatly influence its noise, gain and linearity which is controlled by designing a suitable input matching network. Ten diverse search methods offered in HP-EEsof were used to optimise an active aperture coupled microstrip patch antenna. This study has shown that the algorithms based on the randomised search techniques and the Genetic algorithm provide the most robust performance. The optimisation results were used to design an active dual-band antenna.

Future wireless communication devices must support multiple standards and features on a single-chip. The trend towards software-defined radio requires flexible and efficient RF building blocks which justifies the adoption of broadband receiver front-ends in modern and future communication systems. The broadband receiver front-end significantly reduces cost, area, pins, and power, and can process several signal channels simultaneously. This research is mainly focused on the analysis and realization of the broadband receiver architecture and its various building blocks (LNA, Active Balun-LNA, Mixer, and trans-impedance amplifier) for multi-standard applications. In the design of the mobile DTV tuner, a direct-conversion receiver architecture is adopted achieving low power, low cost, and high dynamic-range for DVB-H standard. The tuner integrates a single-ended RF variable gain amplifier (RFVGA), a current-mode passive mixer, and a combination of continuous and discrete-time baseband filter with built-in anti-aliasing. The proposed RFVGA achieves high dynamic-range and gain-insensitive input impedance matching performance. The current-mode passive mixer achieves high gain, low noise, and high linearity with low power supplies. A wideband common-gate LNA is presented that overcomes the fundamental trade-off between power and noise match without compromising its stability. The proposed architecture can achieve the minimum noise figure over the previously reported feedback amplifiers in common-gate configuration. The proposed architecture achieves broadband impedance matching, low noise, large gain, enhanced linearity, and wide bandwidth concurrently by employing an efficient and reliable dual negative-feedback. For the wideband Inductorless Balun-LNA, active single-to-differential architecture has been proposed without using any passive inductor on-chip which occupies a lot of silicon area. The proposed Balun-LNA features lower power, wider bandwidth, and better gain and phase balance than previously reported architectures of the same kind. A surface acoustic wave (SAW)-less direct conversion receiver targeted for multistandard applications is proposed and fabricated with TSMC 0.13?m complementary metal-oxide-semiconductor (CMOS) technology. The target is to design a wideband SAW-less direct coversion receiver with a single low noise transconductor and current-mode passive mixer with trans-impedance amplifier utilizing feed-forward compensation. The innovations in the circuit and architecture improves the receiver dynamic range enabling highly linear direct-conversion CMOS front-end for a multi-standard receiver.

L’objectif de ce travail est de concevoir et de caractériser un front-end millimétriqueutilisant des lignes de propagation à ondes lentes S-CPW optimisées en technologies CMOS avancées.Ces lignes présentant des facteurs de qualité 2 à 3 fois supérieurs à ceux des lignes classiques de typemicroruban ou CPW.Dans le premier chapitre, l’impact de l’évolution des noeuds technologiques CMOS sur lesperformances des transistors MOS aux fréquences millimétriques et sur les lignes de propagation ainsiqu’un état de l’art concernant les performances des front-end sont présentés. Le deuxième chapitreconcerne la réalisation des lignes S-CPW dans différentes technologies CMOS et la validation d’unmodèle phénoménologique électrique équivalent. Le troisième chapitre est dédié à la conceptiond’amplificateurs de puissance à 60 GHz utilisant ces lignes S-CPW en technologies CMOS 45 et65 nm. Cette étude a permis de mettre en évidence l’apport des lignes à ondes lentes aux performancesdes amplificateurs de puissance fonctionnant dans la gamme des fréquences millimétriques. Uneméthode de conception basée sur les règles d’électro-migration et permettant une optimisation desperformances a été développée. Finalement, un amplificateur faible bruit et un commutateur d’antennetravaillant à 60 GHz et à base de lignes S-CPW ont été conçus en technologie CMOS 65 nm afin degénéraliser l’impact de ce type de lignes sur les performances des front-end millimétriques. / The objective of this work is to design and characterize a millimeter-wave front-end usingthe optimized slow-wave transmission lines S-CPW in advanced CMOS technologies. The qualityfactor of these transmission lines is twice to three times higher than that of the conventionaltransmission lines such as microstrip lines and coplanar waveguides.In the first chapter, the influence of CMOS scaling-down on the performance of transistors atmillimeter-wave frequencies and on the transmission lines was studied. In addition, a state of the artwith regard to the performance of the front-end was presented. The second chapter concerns about therealization of the S-CPW lines in different CMOS technologies and the validation of an electricalequivalent model. The third chapter is dedicated to the design of 60-GHz power amplifiers using theseS-CPW lines in CMOS 45 and 65 nm technologies. This study highlighted the performanceenhancement of power amplifiers operating at millimeter-wave frequencies by using the slow-wavetransmission lines. A design method based on the electro-migration rules was also developed. Finally,a low noise amplifier and an antenna switch operating at 60 GHz were designed in CMOS 65 nm inorder to generalize the impact of such transmission lines on the performance of the millimeter-wavefront-end.

The Square Kilometre Array (SKA) is a multibillion and a multinational science project to build the world’s largest and most sensitive radio telescope. For a very large field of view, the combined collecting area would be one square kilometre (or 1, 000, 000 square metre) and spread over more than 3,000 km wide which will require a massive count of antennas (thousands). Each of the antennas contains hundreds of low noise amplifier (LNA) circuits. The antenna arrays are divided into low, medium and high operational frequencies and located at different positions to boost up the telescope’s scanning sensitivity.The objective of this work was to develop and fabricate fully on-chip LNA circuits to meet the stringent requirements for the mid-frequency array from 0.4 GHz to 1.4 GHz of the SKA radio astronomy telescope using Monolithic Microwave Integrated Circuit technology (MMIC). Due to the number of LNA reaching figures of millions, the fabricated circuits were designed with the consideration for low cost fabrication and high reliability in the receiver chain. Therefore, a relaxed optical lithography with Lg = 1 µm was adopted for a high yield fabrication process.Towards the fulfilment of the device’s low noise characteristics, a large number of device designs, fabrication and characterisation of InGaAs/InAlAs/InP pHEMTs were undertaken. These include optimisations at each critical fabrication steps. The device’s high breakdown and very low gate leakage characteristics were further improved by a combination of judicious epitaxial growth and manipulation of materials’ energy gaps. An attempt to increase the device breakdown voltage was also employed by incorporating Field Plate structure at the gate terminal. This yielded the devices with improvements in the breakdown voltage up to 15 V and very low gate leakage of 1 µA/mm, in addition to high transconductance (gm) characteristic. Fully integrated double stage LNA had measured NF varying from 1.2 dB to 1.6 dB from 0.4 GHz to 1.4 GHz, compared with a slightly lower NF obtained from simulation (0.8 dB to 1.1 dB) across the same frequency band.These are amongst the attractive device properties for the implementation of a fully on-chip MMIC LNA circuits demonstrated in this work. The lower circuit’s low noise characteristic has been demonstrated using large gate width geometry pHEMTs, where the system’s noise resistance (Rn) has successfully reduced to a few ohms. The work reported here should facilitate the successful implementation of rugged low noise amplifiers as required by SKA receivers.

This master's thesis presents the design and the realization of a low noise amplifier (LNA) for the S band of radio frequency spectrum from 2.3 GHz to 2.4 GHz. This thesis is mainly focused on stability and impedance matching networks study. Ansoft Designer and ANSYS HFSS programs are used for this design to simulate the LNA. Different low noise devices are simulated in order to find the best results for the final design. Moreover, a coaxial cavity resonator is designed in the input of the LNA and works as a band pass filter. Finally, the LNA is fabricated and its properties compared with the simulation results.

This work deals with design, simulation and realisation of a receiving systém of an S-band front end for satellite communication. The first part of the project is designed the low noise amplifier (LNA) with high associated gain. The basic point of the design is choice of the active device. In the present time are available the ultra low noise transistors based on the GaAs with high mobility electron. The two-stage LNA has been designed with Agilent ATF-55143. It is pseudomorphic HEMTs ,which work in an enhancement mode.These transistor do not require a negative bias voltage and have extremely good typical noise figure. The design includes an interdigital tuned band pass filter between stages. The second part of the project is search another way design circuit. There are designed two LNA with paralel coupled line filter. The first has been applied on a PTFE substrate Duroid 5880 with relative permitivity 2,2 and tg d = 0,009. The substrate FR-4 (r = 4.34) with the thickness 0.06” was used for the realization.

Dans un monde où l’information va de plus en plus vite, il est important de pouvoir rester connecté en permanence. De nouvelles solutions émergent pour connecter les passagers à bord d’un avion grâce aux communications par satellite. Parmi elles, on retrouve les antennes à pointage électronique dans lesquelles cette thèse de doctorat s’intègre. Une étude sur les différentes antennes existantes ou en projet est présentée. Les puces électroniques MMIC AsGa permettent d’appliquer des lois d’amplitude et de phase pour chaque élément rayonnant d’une antenne réseau. Cette thèse de doctorat porte sur la conception d’un déphaseur, après avoir étudié les technologies et les topologies de celui-ci. Ensuite, la conception d’un amplificateur faible bruit à gain variable est proposée à partir d’un état de l’art. Les résultats de simulation et de mesures de ces deux fonctions sont exposés. / In a world where the information is moving faster and faster, it is important to be able to stay connected continuously. Some new solutions for air transport connectivity are in development thanks to the rise of satellite communications. This thesis work is part of an electronically steerable antenna array project, developed as a solution to achieve In-Flight Connectivity in Ka-band. A state- of-the art review on electronically steerable antenna arrays is also presented. In these arrays, each radiating element needs a specific amplitude and phase to obtain a scanning beam by adding their contribution. This thesis focus on the design of a GaAs MMIC chip inclusion two functions: a phase shifter and a variable-gain low-noise amplifier. The simulation and measurement results are presented for these two functions.

Avec le contexte actuel des défis sécuritaires, la détection de petits objets devient un enjeu majeur pour lutter contre les actes malveillants. Mais les évolutions des technologies en bandes millimétriques et le potentiel de ces bandes, notamment autour de 60 GHz peuvent faciliter la conception de systèmes de plus en plus performants, permettant de répondre à ces enjeux. Cette thèse s’inscrit dans ce contexte pour proposer un système de détection ultra-large bande (ULB) millimétrique pour des applications de courte portée. Après un état de l'art détaillé des fondamentaux de la détection, nous présentons une validation de l'estimation de la surface équivalente radar (SER) par simulation avec le logiciel HFSS et par mesures en chambre anéchoïque. Ces deux études nous ont permis d'identifier les éléments essentiels à l'analyse système et les paramètres critiques de la détection d'objets canoniques cylindres et plaques. Une fois l'analyse système cernée, nous avons proposé une approche de détection multi-bande basée sur le radar monostatique pour améliorer la couverture de détection des systèmes, mais aussi et surtout pour pallier la limitation de la détection des objets en fonction de leur orientation par rapport à l'axe de viser de l'antenne. Nous avons également proposé une architecture (émetteur-récepteur) simple pouvant être associée au principe de détection. Le dimensionnement du système nous a permis d'identifier les amplificateurs faible bruit (LNAs) comme éléments critiques du récepteur et ainsi d'établir leurs spécifications pour atteindre les performances visées. Une comparaison des technologies SG13S de IHP et D007IH de OMMIC est menée dans la dernière partie de ce travail. Le choix de la technologie est justifié et la conception des LNAs sous ADS Keysight est détaillée. Une simulation de l'ensemble du système basée sur les performances des LNAs conçus et sur les simulations de SER est présentée pour illustrer la mise en œuvre de la détection. Enfin, les performances de la détection sont évaluées pour des cibles cylindriques et les apports du système proposé sont illustrés en comparaison avec une détection classique mono-bande / With the current context of security challenges, small objects detection is becoming a major issue in the fight against malicious acts. However, developments in millimeter-band technologies and the potential of these bands, particularly around 60 GHz, can facilitate the design of increasingly efficient systems to meet these challenges. This thesis is part of this context to propose an ultra-wideband (UWB) millimeter-wave detection system for short-range applications.After a detailed state-of-the-art of the fundamentals of detection, we present a validation of the radar cross-section (RCS) estimation by simulations with HFSS software and by measurements in anechoic chamber. These two studies allowed us to identify the essential elements for system analysis and the critical parameters for the detection of canonical objects such as cylinders and plates.Once the system analysis was identified, we proposed a multi-band detection approach based on monostatic radar to improve the detection coverage of the systems, but also and especially to overcome the limitation of objects detection according to their orientation in relation to the antenna boresight. We also proposed a simple architecture (transceiver) that could be associated with the detection principle. The system design allowed us to identify low noise amplifiers (LNAs) as critical elements of the receiver and thus establish their specifications to achieve the targeted performances.A comparison of IHP's SG13S and OMMIC's D007IH technologies is conducted in the last part of this work. The choice of technology is justified and the design of LNAs under ADS Keysight is detailed. A simulation of the entire system based on the performance of the designed LNAs and RCS simulations is presented to illustrate the implementation of detection. Finally, detection performances are evaluated for cylindrical targets and the contributions of the proposed system are illustrated in comparison with conventional single-band detection

This letter presents a low-noise amplifier with a 3 dB-bandwidth, from 55 to 74 GHz, excellent noise performance and low power consumption based on a three-stage common-source topology. For the first time to the authors’ best knowledge, an analytical equation that also considers the gate–drain capacitance is derived for the employed shunt–series transformer feedback input matching network. To enable shunt–series transformer feedback matching without significant gain reduction a highly asymmetric transformer is designed. Furthermore, a compact transformer-implemented T-shaped output matching network is investigated to minimize the required area. To prove these concepts, the circuit has been fabricated in a 22 nm fully depleted silicon-on-insulator technology. Thanks to the transformer-based matching, an ultra-compact active footprint of 0.039 mm² is achieved. At a power consumption of 8.4 mW from a 0.41 V supply an average noise figure of 4.8 dB and a peak gain of 14.2 dB has been measured. In- and output matching better than −10 dB over the 19 GHz wide 3 dB-bandwidth are demonstrated.

Разработан прототип приемника-декодера сигналов стандарта ADS-B. В ходе разработки предложена структурная схема выполнения устройства, а так же проведено комплексное исследование элементов устройства. Предложены принципиальные схемы и прототипы печатных плат для таких устройств как усилитель, инжектор питания, малошумящий усилитель, логарифмический детектор, а так же рассмотрена топология фильтра с двойной комплементарной спиралью. Приводятся результаты моделирования в различных пакетах программного обеспечения перечисленных выше устройств, а так же результаты их экспериментального исследования. Для обеспечения симуляции сигналов стандарта, а так же для обработки создано программное обеспечение. / A prototype of the receiver-decoder for the ADS-B system. During the development the block diagram of the device was proposed and a comprehensive study of elements of the device was done. Circuit schematics and layouts of printed circuit boards for devices such as amplifier, power injector, low noise amplifier, logarithmic detector and filter with a double complementary spiral were proposed. The results of the simulation of the listed above devices in a variety of software packages, as well as the results of an experimental study are presented. In order to simulate the signals, as well as for processing them special software was created.