Cette thèse vise à réaliser des développements théoriques et numériques portant sur le comportement en cyclage thermomécanique de nouveaux alliages de brasure. L’objectif est de proposer une méthodologie de simulation de la fatigue des assemblages électroniques intégrant ce type de brasures. De nombreux modèles semi-empiriques de fatigue existent déjà mais ont montré leurs limites pour une prédiction suffisamment précise de la fiabilité. Il existe donc un besoin d’enrichir les approches existantes par une description des mécanismes de défaillance à l’échelle mésoscopique, en prenant en compte la microstructure fine de l’alliage d’étain. Une formulation décrivant la plasticité cristalline de l’étain et l’endommagement aux joints de grains a donc été développée et intégrée dans un code de calcul pour simuler les mécanismes de déformation dans le joint de brasure. / This thesis aims to carry out theoretical and numerical developments on the thermo-mechanical cyclic behavior of new solder alloys. The objective is to propose a methodology for modeling the fatigue of electronic packages including this type of solders. Several semi-empirical fatigue models already exist, but have shown their limitations for an accurate sufficiently prediction of reliability. Therefore, it requires to enrich the existing approaches by a description of failure mechanisms in the mesoscopic scale, taking into account the fine microstructure of the alloy of tin. A formulation describing the crystal plasticity of tin and the damage of grain boundaries has therefore been developed and integrated in the finite element code for simulating the fracture mechanisms of solder joint.

Although high-level synthesis has been researched for many years, synthesizing minimum hardware implementations under a throughput constraint for computationally intensive algorithms remains a challenge. In this thesis, three important techniques are studied carefully and applied in an integrated way to meet this challenging synthesis requirement. The first is pipeline scheduling, which generates a pipelined schedule that meets the throughput requirement. The second is module selection, which decides the most appropriate circuit module for each operation. The third is resource sharing, which reuses a circuit module by sharing it between multiple operations. This work shows that combining module selection and resource sharing while performing pipeline scheduling can significantly reduce the hardware area, by either using slower, more area-efficient circuit modules or by time-multiplexing faster, larger circuit modules, while meeting the throughput constraint. The results of this work show that the combined approach can generate on average 43% smaller hardware than possible when a single technique (resource sharing or module selection) is applied. There are four major contributions of this work. First, given a fixed throughput constraint, it explores all feasible frequency and data introduction interval design points that meet this throughput constraint. This enlarged pipelining design space exploration results in superior hardware architectures than previous pipeline synthesis work because of the larger sapce. Second, the module selection algorithm in this work considers different module architectures, as well as different pipelining options for each architecture. This not only addresses the unique architecture of most FPGA circuit modules, it also performs retiming at the high-level synthesis level. Third, this work proposes a novel approach that integrates the three inter-related synthesis techniques of pipeline scheduling, module selection and resource sharing. To the author's best knowledge, this is the first attempt to do this. The integrated approach is able to identify more efficient hardware implementations than when only one or two of the three techniques are applied. Fourth, this work proposes and implements several algorithms that explore the combined pipeline scheduling, module selection and resource sharing design space, and identifies the most efficient hardware architecture under the synthesis constraint. These algorithms explore the combined design space in different ways which represents the trade off between algorithm execution time and the size of the explored design space.

Modulare Prozessanlagen bestehen aus einfach austauschbaren Prozess- und Funktionseinheiten, deren Konfiguration (Aufbau) und Rekonfiguration (Umbau) neue Möglichkeiten der flexiblen Prozessrealisierung eröffnen. Die Wandelbarkeit der Anlagen stellt aus Perspektive der funktionalen Sicherheit eine Herausforderung dar, da bestehende Methoden und Vorgehensweisen auf den verhältnismäßig statischen Betrieb von konventionellen Anlagen optimiert sind. Um den Zielkonflikt zwischen Flexibilität und Sicherheit abzumildern wurde ein Konzept zur Orchestrierung von verteilten Sicherheitssystemen entwickelt und in einer Demonstrationsanlage erfolgreich erprobt. Der Konzeptentwurf integriert sowohl technische als auch menschliche Anforderungen, mit dem Ziel, Operateure durch eine geschickte Systemgestaltung zur Beherrschung der Re-Konfiguration zu befähigen. / Modular process plants consist of easily exchangeable process and functional units whose configuration (assembly) and reconfiguration (modification) open up new possibilities for flexible process implementation. The changeability of the plants poses a challenge from the perspective of functional safety, since existing methods and procedures are optimized for the relatively static operation of conventional plants. To mitigate the trade-off between flexibility and safety, a concept for orchestrating distributed safety systems was developed and successfully tested in a demonstration plant. The concept design integrates both technical and human requirements, with the goal of enabling operators to master reconfiguration through smart system design.

Double-sided module exhibits electrical and thermal characteristics that are superior to wire-bonded counterpart. Such structure, however, induces more than twice the thermo-mechanical stress in a single-layer structure. Compressive posts have been developed and integrated into the double-sided module to reduce the stress to a level acceptable by silicon dice. For a 14 mm x 21 mm module carrying 6.6 mm x 6.6 mm die, finite-element simulation suggested an optimal design having four posts located 1 mm from the die; the z-direction stress at the chip was reduced from 17 MPa to 0.6 MPa. / Ph. D.

ITC/USA 2005 Conference Proceedings / The Forty-First Annual International Telemetering Conference and Technical Exhibition / October 24-27, 2005 / Riviera Hotel & Convention Center, Las Vegas, Nevada / As requirements for the amount of test data continues to increase, instrumentation engineers are under pressure to deploy data acquisition systems that reduce the amount of associated wiring and overall system complexity. Smart sensor buses have been long considered as one approach to address this issue by placing the appropriate signal conditioners close to their respective sensors and providing data back over a common bus. However, the inability to adequately synchronize the operation of the sensor bus to the system master, which is required to correlate analog data measurements, has precluded their use. The ongoing development and deployment of smart sensor buses has reached the phase in which integration into a larger data acquisition system environment must be considered. Smart sensor buses, such as IntelliBus™, have their own unique mode of operation based on a pre-determined sampling schedule, which however, is typically asynchronous to the operation of the (master or controller) data acquisition system and must be accounted for when attempting to synchronize the two systems. IRIG Chapter 4 type methods for inserting data into a format, as exemplified by the handling of MIL-STD-1553 data, could be employed, with the disadvantage of eliminating any knowledge as to when a particular measurement was sampled, unless it is time stamped (similar to the time stamping function that is provided to mark receipt of 1553 command words). This can result in excessive time data as each sensor bus can manage a large number of analog sensor inputs and multiple sensor buses must be accommodated by the data acquisition system. The paper provides an example, using the Boeing developed IntelliBus system and the L3 Communications - Telemetry East NetDAS system, of how correlated data can be acquired from a smart sensor bus as a major subsystem component of a larger integrated data acquisition system. The focus will be specifically on how the IntelliBus schedule can be synchronized to that of the NetDAS formatter. Sample formats will be provided along with a description of how a standalone NetDAS stack and an integrated NetDAS-IntelliBus system would be programmed to create the required output, taking into account the unique sampling characteristics of the sensor bus.

International Telemetering Conference Proceedings / October 18-21, 2004 / Town & Country Resort, San Diego, California / M/A-COM, Inc. has developed a miniature Tactical Telemetry Module (TTM) for medium power (500 mW and 1 W) telemetry applications. The TTM demonstrates system integration of a multi-channel PCM encoder, lower S-band transmitter, and power regulation onto a single printed wiring board (PWB). The module is smaller than a standard business card and utilizes both COTS and M/A-COM proprietary technologies. The PCM encoder is designed for eight (8) analog inputs, eight (8) discrete inputs, and one (1) synchronous RS-422 serial interface. Data rates of 300 kbps to 6 Mbps are supported. The module incorporates a frequency programmable, phase-locked FM S-band transmitter. The transmitter utilizes M/A-COM’s new dual port VCO and high efficiency 500 mW and 1 W power amplifier MMIC’s. Additionally, switching power regulation circuits were implemented within the module to provide maximum operating efficiency. This paper reviews the design and manufacturing of the Tactical Telemetry Module (TTM) and its major components, and presents system performance data.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / In the past, typical telemetry systems for munitions and small missiles have often comprised adaptations of monolithic components originally conceived for aircraft or large missile applications. Programs have developed expensive monolithic systems to meet the needs of specific programs, but they often require extensive redesign for use by other potential users. The tri-service HSTSS Integrated Product Team (IPT) determined that a monolithic “one size fits all” approach has technical and fiscal risks. Thus, a modular approach to system development has been adopted. The HSTSS IPT is flight qualifying commercial microelectronic products designed for environments similar to that of munition interiors, and is developing microelectronic components required to complete a subminiature system. HSTSS components can then be integrated to support the form factor and measurement needs of any given user. In addition to offering a flexible system to the user, the HSTSS lends itself to upgradability (modernization through spares).

International Telemetering Conference Proceedings / October 26-29, 1992 / Town and Country Hotel and Convention Center, San Diego, California / An orbiting sensor module, designed by The Johns Hopkins University Applied Physics Laboratory (JHU/APL), performed a number of significant Strategic Defense Initiative (SDI) Delta 181 program experiments. These experiments required on-orbit command and monitor operations involving a worldwide network of ground facilities. A major component was the sensor module command center (SMCC), which was designed and integrated by JHU/APL. The SMCC, located at Cape Canaveral Air Force Station (CCAFS), connected to a network of Eastern Test Range, Air Force Satellite Control Network (AFSCN), Kennedy Space Center, and Western Test Range assets. The complex nature of the mission presented numerous challenges to the design, integration, and operation of the SMCC. This paper presents a functional overview of SMCC design as well as unique aspects of supporting ground network telemetry and command operation.

In this thesis a design for a smart high efficiency voltage regulating module capable of supplying the core of modern microprocessors incorporating dynamic voltage and frequency scaling (DVS) capability is accomplished using a RISC based microcontroller to facilitate all the functions required to control, protect, and supply the core with the required variable operating voltage as set by the DVS management system. Normally voltage regulating modules provide maximum power efficiency at designed peak load, and the efficiency falls off as the load moves towards lesser values. A mathematical model has been derived for the main converter and small signal analysis has been performed in order to determine system operation stability and select a control scheme that would improve converter operation response to transients and not requiring intense computational power to realize. A Simulation model was built using Matlab/Simulink and after experimenting with tuned PID controller and fuzzy logic controllers, a simple fuzzy logic control scheme was selected to control the pulse width modulated converter and several methods were devised to reduce the requirements for computational power making the whole system operation realizable using a low power RISC based microcontroller. The same microcontroller provides circuit adaptations operation in addition to providing protection to load in terms of over voltage and over current protection. A novel circuit technique and operation control scheme enables the designed module to selectively change some of the circuit elements in the main pulse width modulated buck converter so as to improve efficiency over a wider range of loads. In case of very light loads as the case when the device goes into standby, sleep or hibernation mode, a secondary converter starts operating and the main converter stops. The secondary converter adapts a different operation scheme using switched capacitor technique which provides high efficiency at low load currents. A fuzzy logic control scheme was chosen for the main converter for its lighter computational power requirement promoting implementation using ultra low power embedded controllers. Passive and active components were carefully selected to augment operational efficiency. These aspects enabled the designed voltage regulating module to operate with efficiency improvement in off peak load region in the range of 3% to 5%. At low loads as the case when the computer system goes to standby or sleep mode, the efficiency improvent is better than 13% which will have noticeable contribution in extending battery run time thus contributing to lowering the carbon footprint of human consumption.

Development and optimisation of a robust energy yield prediction methodology is the ultimate aim of this research. Outdoor performance of the PV module is determined by the influences of a variety of interlinked factors related to the environment and device technologies. There are two basic measurement data sets required for any energy yield prediction model. Firstly, characterisation of specific PV module technology under different operating conditions and secondly site specific meteorological data. Based on these two datasets a calculation procedure is required in any specific location energy yield estimation. This research established a matrix based multi-dimensional measurement set points for module characterisation which is independent of PV technologies. This novel approach has been established by demonstrating an extended correlation of different environmental factors (irradiance, temperature and spectral irradiance) and their influences on the commercial PV device technologies. Utilisation of the site specific meteorological data is the common approach applied in this yield prediction method. A series of modelling approach, including a tri-linear interpolation method is then applied for energy yield calculation. A novel Monte Carlo simulation is demonstrated for uncertainty analysis of irradiance (pyranometer CM 11) & temperature (PT 1000) measurements and ultimately the yield prediction of c-Si and CIGS modules. The degree of uncertainties of irradiance is varies from ??2% to ??6.2% depending on the level of monthly irradiation. The temperature measurement uncertainty is calculated in the range of ??0.18??C to ??0.46%??C in different months of the year. The calculated uncertainty of the energy yield prediction of c-Si and CIGS module are ??2.78% and ??15.45%. This research validated different irradiance translation models to identify the best matched model for UK climate for horizontal to in-plane irradiance. Ultimately, the validation results of the proposed Fast Energy Yield Calculation (FEnYCs), shows a good agreement against measured values i.e. 5.48%, 6.97% and 3.1% for c-Si, a-Si and CIGS module respectively.