The effects of direct plasma chemistries on carbon removal from silicon nitride (SiNx) and oxynitride (SiOxNy ) surfaces and Cu have been studied by x-photoelectron spectroscopy (XPS) and ex-situ contact angle measurements. The data indicate that O2,NH3 and He capacitively coupled plasmas are effective at removing adventitious carbon from silicon nitride (SiNx) and Silicon oxynitride (SiOxNy ) surfaces. O2plasma and He plasma treatment results in the formation of silica overlayer. In contrast, the exposure to NH3 plasma results in negligible additional oxidation of the SiNx and SiOxNy surface. Ex-situ contact angle measurements show that SiNx and SiOxNy surfaces when exposed to oxygen plasma are initially more hydrophilic than surfaces exposed to NH3 plasma and He plasma, indicating that the O2 plasma-induced SiO2 overlayer is highly reactive towards ambient corresponding to increased roughness measured by AFM. At longer ambient exposures (>~10 hours), however surfaces treated by either O2, He or NH3 plasma exhibit similar steady state contact angles, correlated with rapid uptake of adventitious carbon, as determined by XPS. Surface passivation by exposure to molecular hydrogen prior to ambient exposure significantly retards the increase in the contact angle upon the exposure to ambient. The results suggest a practical route to enhancing the time available for effective bonding to surfaces in microelectronics packaging applications.

No description available.

As the microelectronic industry moves toward stacking of dies to achieve greater performance and smaller footprint, there are several reliability concerns when assembling the stacked dies on current organic substrates. These concerns include excessive warpage, interconnect cracking, die cracking, and others. Silicon interposers are being developed to assemble the stacked dies, and then the silicon interposers are assembled on organic substrates. Although such an approach could address stacked-die to interposer reliability concerns, there are still reliability concerns between the silicon interposer and the organic substrate. This work examines the use of diced glass panel as an interposer, as glass provides intermediate coefficient of thermal expansion between silicon and organics, good mechanical rigidity, large-area panel processing for low cost, planarity, and better electrical properties. However, glass is brittle and low in thermal conductivity, and there is very little work in existing literature to examine glass as a potential interposer material. Starting with a 150 x 150 mm glass panel with a thickness of 100 µm, this work has built alternating layers of dielectric and copper on both sides of the panel. The panels have gone through typical cleanroom processes such as lithography, electroplating, etc. Upon fabrication, the panels are diced into individual substrates of 25 x 25 mm and a 10 x 10 mm flip chip with a solder bump pitch of 75 um is then reflow attached to the glass substrate followed by underfill dispensing and curing. The warpage of the flip-chip assembly is measured. In parallel to the experiments, numerical models have been developed. These models account for viscoplastic behavior of the solder. The models also mimic material addition and etching through element “birth-and-death” approach. The warpage from the models has been compared against experimental measurements for glass substrates with flip chip assembly. It is seen that the glass substrates provide significantly lower warpage compared to organic substrates, and thus could be a potential candidate for future 3D systems.

L'intégration de diélectriques High-k dans les empilements de grille des transistors a fait naître des problèmes de fiabilité complexes. A cela vient s'ajouter, en vue des technologies sub-32nm planaires, de nouvelles problématiques liées à l'utilisation de substrats silicium sur isolant complètement désertés FDSOI. En effet, l'intégration d'un oxyde enterré sous le film de silicium non seulement va modifier l'électrostatique de la structure mais aussi introduire une nouvelle interface Si/SiO2 sujette à d'éventuelles dégradations. Ce manuscrit présente différentes méthodes de caractérisation électrique ainsi que différentes études de fiabilité des dispositifs FDSOI intégrants des empilements High-κ/ grille métallique. Dans un premier temps, une étude complète du couplage électrostatique dans des structures FDSOI est réalisée, permettant de mieux appréhender l'effet d'une tension en face arrière sur les caractéristiques électriques des dispositifs. Différentes méthodes de caractérisation des pièges d'interface sont ensuite présentées et adaptées, quand cela est possible, au cas spécifique du FDSOI, où les défauts entre le film de silicium et l'oxyde enterré doivent être pris en compte. Enfin, différentes études de fiabilité sont présentées, des phénomènes de PBTI et de NBTI sur des dispositifs à canaux longs aux phénomènes propres aux dispositifs de petite dimension, tels que l'impact des porteurs chauds dans des structures FDSOI à film ultra fins et les effets parasites d'augmentation de la tension de seuil lorsque les largeurs des transistors diminuent. / The integration of High-k dielectrics in recent CMOS technologies lead to new complex reliability issues. Furthermore new concerns appear with the use of fully depleted silicon on insulator (FDSOI) substrates for future sub-32nm planar technologies. Indeed, the integration of a buried oxide underneath the silicon film changes the electrostatic of the structure and create a new Si/SiO2 interface which may be degraded. This thesis presents different electrical characterization techniques and reliability studies on High-κ/metal gate FDSOI transistors. First, a complete electrostatic study of FDSOI structures is done allowing a better understanding of the effects of backgate biases. Different techniques to characterize interface traps are then presented and adapted to FDSOI devices, where traps at the silicon film/buried oxide interface must be considered. Finally, different reliability studies are presented; from NBTI and PBTI issues on long channel devices to specific concerns related to small gate length transistors such as hot carriers degradation on ultra-thin film FDSOI devices and threshold voltage increase with gate width scaling.

Technological advancement has thrust MEMS design and fabrication into the forefront of modern technologies. It has become sufficiently self-sustained to allow mass production. The limiting factor which is stalling commercialization of MEMS is the packaging and device reliability. The challenging issues with MEMS packaging are application specific. The function of the package is to give the MEMS device mechanical support, protection from the environment, and electrical connection to other devices in the system. The current state of the art in MEMS packaging transcends the various packaging techniques available in the integrated circuit (IC) industry. At present the packaging of MEMS includes hermetic ceramic packaging and metal packaging with hermetic seals. For example the ADXL202 accelerometer from the Analog Devices. Study of the packaging methods and costs show that both of these methods of packaging are expensive and not needed for majority of MEMS applications. Due to this the cost of current MEMS packaging is relatively high, as much as 90% of the finished product. Reducing the cost is therefore of the prime concern. This Thesis explores the possibility of an inexpensive plastic package for MEMS sensors like accelerometers, optical MEMS, blood pressure sensors etc. Due to their cost effective techniques, plastic packaging already dominates the IC industry. They cost less, weigh less, and their size is small. However, porous nature of molding materials allows penetration of moisture into the package. The Thesis includes an extensive study of the plastic packaging and characterization of three different plastic package samples. Polymeric materials warp upon absorbing moisture, generating hygroscopic stresses. Hygroscopic stresses in the package add to the thermal stress due to high reflow temperature. Despite this, hygroscopic characteristics of the plastic package have been largely ignored. To facilitate understanding of the moisture absorption, an analytical model is presented in this Thesis. Also, an empirical model presents, in this Thesis, the parameters affecting moisture ingress. This information is important to determine the moisture content at a specific time, which would help in assessing reliability of the package. Moisture absorption is modeled using the single phase absorption theory, which assumes that moisture diffusion occurs freely without any bonding with the resin. This theory is based on the Fick's Law of diffusion, which considers that the driving force of diffusion is the water concentration gradient. A finite difference simulation of one-dimensional moisture diffusion using the Crank-Nicolson implicit formula is presented. Moisture retention causes swelling of compounds which, in turn, leads to warpage. The warpage induces hygroscopic stresses. These stresses can further limit the performance of the MEMS sensors. This Thesis also presents a non invasive methodology to characterize a plastic package. The warpage deformations of the package are measured using Optoelectronic holography (OEH) methodology. The OEH methodology is noninvasive, remote, and provides results in full-field-of-view. Using the quantitative results of OEH measurements of deformations of a plastic package, pressure build up can be calculated and employed to assess the reliability of the package.

This thesis consists of three main parts, starting with the use of improved nitridation processes to grow acceptable quality gate oxides on silicon carbide (SiC)[1]–[7], to the comprehensive investigation of basic electron-hole generation process in 4H SiC-based metal–oxide–semiconductor (MOS) capacitors [8], [9], and concluding with the experimental demonstration and analysis of nonvolatile characteristics of 4H SiC-based memory devices [10]–[15]. In the first part of the thesis, two improved versions of nitridation techniques have been introduced to alleviate oxide-growth rate and toxicity problems. Using a combination of nitridation and oxidation processes, a sandwich technique (nitridation–oxidation–nitridation) has been proposed and verified to solve the lengthy and expensive oxide-growing process in direct nitric oxide (NO) gas [1]. The nitrogen source from the toxic-NO gas has been replaced by using a nontoxic nitrous oxide (N2O) gas. The best combination of process parameters in this gas is oxide-growing temperature at 1300oC with 10% N2O [2], [3]. The quality of nitrided gate oxides obtained by this technique is lower than the sandwich technique [6], [13]. Using 4H SiC-based MOS with nitrided gate oxides grown by either of the abovementioned nitridation techniques, the fundamentals of electron-hole generation have been investigated using high-temperature capacitance–transient measurements. The contributions of carrier generation, occurring at room temperature, in the bulk and at the SiC–SiO2 interface are evaluated and compared using a newly developed method [8], [9]. The effective bulk-generation rates are approximately equal for both types of nitrided oxides, whereas the effective surface-generation rates have been shown to exhibit very strong dependencies on the methods of producing the nitrided gate oxide. Based on analysis, the prevailing generation component in a SiC-based MOS capacitor with nitrided gate oxide is at SiC–SiO2 interface located below the gate. Utilizing the understanding of electron-hole generation in SiC, the nonvolatile characteristics of memory device fabricated on SiC have been explored. The potential of developing a SiC-based one-transistor one-capacitor (1T/1C) nonvolatile-dynamic memory (NDM) has been analyzed using SiC-based MOS capacitors as storage elements or test structures. Three possible leakage mechanisms have been evaluated [10]–[16]: (1) leakage via MOS capacitor dielectric, (2) leakage due to electron-hole generation in a depleted MOS capacitor, and (3) junction leakage due to generation current occurred at a reverse-biased pn junction surrounding the drain region of a select metal–oxide– semiconductor field–effect–transistor (MOSFET). Among them, leakage through capacitor oxide remains an important factor that could affect the nonvolatile property in the proposed device, whereas others leakage mechanisms are insignificant. Based on the overall results, the potential of developing a SiC-based 1T/1C NDM is encouraging.

With continued push toward 3D integrated packaging, Through-Silicon Vias (TSVs) play an increasingly important role in interconnecting stacked silicon dies. Although progress is being made in the fabrication of TSVs, experimental and theoretical assessment of their thermomechanical reliability is still in infancy. This work explores the thermomechanical reliability of TSVs through numerical models and innovative experimental characterization techniques. Starting with free-standing wafers, this work examines failure mechanisms such as Si and SiO₂ cohesive cracking as well as SiO₂/Cu interfacial cracking. Such cohesive crack propagation and interfacial crack propagation are studied using fracture mechanics finite-element modeling, and the energy available for crack propagation is determined through crack extension using the proposed centered finite-difference approach (CFDA). In parallel to the simulations, silicon wafers with TSVs are designed and fabricated and subjected to thermal shock test. Cross-sectional SEM failure analysis is carried out to study cohesive and interfacial crack initiation and propagation under thermal excursions. In addition, local micro-strain fields under thermal excursions are mapped through synchrotron X-ray diffraction. To understand the 3D to 2D strain measurement data projection process, a new data interpretation method based on beam intensity averaging is proposed and validated with measurements. Building upon the work on free-standing wafers, this research studies the package assembly issues and failure mechanisms in multi-die stacks. Comprehensive design-of-simulations study is carried out to assess the effect of various material and geometry parameters on the reliability of 3D microelectronic packages. Through experimentally-measured strain fields, thermal cycling tests, and simulations, design guidelines are developed to enhance the thermomechanical reliability of TSVs used in future 3D microelectronic packages.

Conventional solder balls used in microelectronic packaging suffer from thermo- mechanical damage due to difference in coefficient of thermal expansion between the die and the substrate or the substrate and the board. Compliant interconnects are replacements for solder balls which accommodate this differential displacement by mechanically decoupling the die from the substrate or the substrate from the board and aim to improve overall reliability and life of the microelectronic component. Research is being conducted to develop compliant interconnect structures which offer good mechanical compliance without adversely affecting electrical performance, thus obtaining good thermo-mechanical reliability. However, little information is available regarding the behavior of compliant interconnects under shock and impact loads. The objective of this thesis is to study the response of a proposed multi-path compliant interconnect structure when subjected to shock and impact loading. As part of this work, scaled-up substrate-compliant interconnect-die assemblies will be fabricated through stereolithography techniques. These scaled-up prototypes will be subjected to experimental drop testing. Accelerometers will be placed on the board, and strain gauges will be attached to the board and the die at various locations. The samples will be dropped from different heights to different shock levels in the components, according to Joint Electron Devices Engineering Council (JEDEC) standards. In parallel to such experiments with compliant interconnects, similar experiments with scaled-up solder bump interconnects will also be conducted. The strain and acceleration response of the compliant interconnect assemblies will be compared against the results from solder bump interconnects. Simulations will also be carried out to mimic the experimental conditions and to gain a better understanding of the overall response of the compliant interconnects under shock and impact loading. The findings from this study will be helpful for improving the reliability of compliant interconnects under dynamic mechanical loading.

This research reports for the first time conductive anodic filament reliability of copper plated-through-vias with spacing of 75 – 200 µm in thin glass fiber reinforced organic packaging substrates with advanced epoxy-based and cyclo-olefin polymer resin systems. Reliability studies were conducted in halogenated and halogen-free substrates with improved test structure designs including different conductor spacing and geometry. Accelerated test condition (temperature, humidity and DC bias voltage) was used to investigate the effect of conductor spacing and substrate material influence on insulation reliability behavior. Characterization studies included gravimetric measurement of moisture sorption, extractable ion content analysis, electrical resistance measurement, impedance spectroscopy measurement, optical microscopy and scanning electron microscopy analysis and elemental characterization using energy dispersive x-ray spectroscopy. The accelerated test results and characterization studies indicated a strong dependence of insulation failures on substrate material system, conductor spacing and geometry. This study presents advancements in the understanding of failure processes and chemical nature of failures in fine-pitch copper plated-through-vias in newly developed organic substrates and demonstrates potential methods to mitigate failures for high density organic packages.

Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law at IC level and system miniaturization with System-On-Package (SOP) paradigm at system level, have resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. However, system miniaturization poses several electrical and thermal challenges that demand innovative solutions including advanced materials, bonding and assembly techniques. Heterogeneous material and device integration for thermal structures and IC assembly are limited by the bonding technology and the electrical and thermal impedance of the bonding interfaces. Solder - based bonding technology that is prevalent today is a major limitation to future systems. The trend towards miniaturized systems is expected to drive downscaling of IC I/O pad pitches from 40µm to 1- 5µm in future. Solder technology imposes several pitch, processability and cost restrictions at such fine pitches. Furthermore, according to International Technology Roadmap for Semiconductors (ITRS-2006), the supply current in high performance microprocessors is expected to increase to 220 A by 2012. At such supply current, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer sized technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Similarly, thermal power dissipation is growing to unprecedented high with a projected power of 198 W by 2008 (ITRS 2006). Present thermal interfaces are not adequate for such high heat dissipation. Recently, copper based thin film bonding has become a promising approach to address the abovementioned challenges. However, copper-copper direct bonding without using solders has not been studied thoroughly. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. Hence, there is a need to develop a novel low temperature copper to copper bonding process. In the present study, nanomaterials - based copper-to-copper bonding is explored and developed as an alternative to solder-based bonding. To demonstrate fine pitch bonding, the patterning of these nanoparticles is crucial. Therefore, two novel self-patterning techniques based on: 1.) Selective wetting and 2.) Selective nanoparticle deposition, are developed to address this challenge. Nanoparticle active layer facilitates diffusion and, thus, a reliable bond can be achieved using less thermal budget. Quantitative characterization of the bonding revealed good metallurgical bonding with very high bond strength. This has been confirmed by several morphological and structural characterizations. A 30-micron pitch IC assembly test vehicle is used to demonstrate fine pitch patternability and bonding. In conclusion, novel nanoparticle synthesis and patterning techniques were developed and demonstrated for low-impedance and low-cost electrical and thermal interfaces.