Ever growing demands for portability and functionality have always governed the electronic technology innovations. IC downscaling with Moore s law and system miniaturization with System-On-Package (SOP) paradigm has resulted and will continue to result in ultraminiaturized systems with unprecedented functionality at reduced cost. The trend towards 3D silicon system integration is expected to downscale IC I/O pad pitches from 40µm to 1- 5 µm in future. Device- to- system board interconnections are typically accomplished today with either wire bonding or solders. Both of these are incremental and run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. As supply currents will increase upto 220 A by 2012, the current density will exceed the maximum allowable current density of solders. The intrinsic delay and electromigration in solders are other daunting issues that become critical at nanometer size technology nodes. In addition, formation of intermetallics is also a bottleneck that poses significant mechanical issues. Recently, many research groups have investigated various techniques for copper-copper direct bonding. Typically, bonding is carried out at 400oC for 30 min followed by annealing for 30 min. High thermal budget in such process makes it less attractive for integrated systems because of the associated process incompatibilities. In the present study, copper-copper bonding at ultra fine-pitch using advanced nano-conductive and non-conductive adhesives is evaluated. The proposed copper-copper based interconnects using advanced conductive and non-conductive adhesives will be a new fundamental and comprehensive paradigm to solve all the four barriers: 1) I/O pitch 2) Electrical performance 3) Reliability and 4) Cost. This thesis investigates the mechanical integrity and reliability of copper-copper bonding using advanced adhesives through test vehicle fabrication and reliability testing. Test vehicles were fabricated using low cost electro-deposition techniques and assembled onto glass carrier. Experimental results show that proposed copper-copper bonding using advanced adhesives could potentially meet all the system performance requirements for the emerging micro/nano-systems.

The objective of this research work is to develop an efficient methodology for chip-package cosimulation. In the traditional design flow, the integrated circuit (IC) is first designed followed by the package design. The disadvantage of the conventional sequential design flow is that if there are problems with signal and power integrity after the integration of the IC and the package, it is expensive and time consuming to go back and change the IC layout for a different input/output (IO) pad assignment. To overcome this limitation, a concurrent design flow, where both the IC and the package are designed together, has been recommended by researchers to obtain a fast design closure. The techniques from this research work will enable multiscale cosimulation of the chip and the package making the concurrent design flow paradigm possible. Traditional time-domain techniques, such as the finite-difference time-domain method, are limited by the Courant condition and are not suitable for chip-package cosimulation. The Courant condition gives an upper bound on the time step that can be used to obtain stable simulation results. The smaller the mesh dimension the smaller is the Courant time step. In the case of chip-package cosimulation the on-chip structures require a fine mesh, which can make the time step prohibitively small. An unconditionally stable scheme using Laguerre polynomials has been recommended for chip-package cosimulation. Prior limitations in this method have been overcome in this research work. The enhanced transient simulation scheme using Laguerre polynomials has been named SLeEC, which stands for simulation using Laguerre equivalent circuit. A full-wave EM simulator has been developed using the SLeEC methodology. A scheme for efficient use of full-wave solver for chip-package cosimulation has been proposed. Simulation of the entire chip-package structure using a full-wave solver could be a memory and time-intensive operation. A more efficient way is to separate the chip-package structure into the chip, the package signal-delivery network, and the package power-delivery network; use a full-wave solver to simulate each of these smaller subblocks and integrate them together in the following step, before a final simulation is done on the integrated network. Examples have been presented that illustrate the technique.

Thesis (Ph. D.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, Thomas J. Watson School of Engineering and Applied Science, 2008. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department or Systems Science and Industrial Engineering, 2009. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Science, Department of Mechanical Engineering, 2009. / Includes bibliographical references.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. / Madhavan Swaminathan, Committee Chair ; Sung Kyu Lim, Committee Member ; Abhijit Chatterjee, Committee Member ; David C. Keezer, Committee Member ; C. P. Wong, Committee Member. Vita. Includes bibliographical references.

Le récent essor des systèmes de communication sans fil implique le développement de circuits RF performants, à fort taux d’intégration, bas coût, et adaptés à la production de masse. L’intégration monolithique de systèmes RF sur silicium permet de répondre en partie à ces critères. Cependant, le silicium est responsable de pertes dans le substrat dégradant les performances des composants passifs. Pour adresser cette limite, des caissons isolants de silicium poreux peuvent être réalisés au sein du silicium (substrat mixte). Les objectifs de cette thèse sont de montrer la faisabilité de l’intégration monolithique sur substrat mixte et d’étudier son impact sur les performances de circuits RF. Ce manuscrit décrit l’élaboration des substrats mixtes et donne une comparaison des performances de composants passifs intégrés sur silicium poreux et sur substrats standards. Enfin, l’intégration monolithique de circuits RF est menée sur substrat mixte 6’’. La caractérisation de ces démonstrateurs montre une amélioration des performances par rapport au silicium. De plus, la compatibilité du substrat mixte avec un procédé industriel de microélectronique est validée. / The rapid growth of wireless systems involves the development of highly efficient, large-scale, low-cost and radio frequency (RF) systems. Monolithic integration of RF circuits on silicon can enhance the appeal of this technology further. However, in order to fully realize the next generation of system-on-chip on silicon, the losses which results in to degradation in the performances of passive components need to be addressed. This work investigates locally insulating porous silicon regions on silicon substrates, targeting highly efficient passive components. This thesis begins with a detailed description of porous silicon/silicon hybrid substrate fabrication using a novel mask. The influence of the hybrid substrate on fabricated passive device performances was studied and the results were compared to similar devices on conventional silicon substrates. Finally, monolithic integration of passive and active devices was demonstrated on 6” hybrid substrates, with performance improvements when compared with standard silicon. This work has also shown that hybrid substrates can be fully integrated into industrial scale microelectronic processes.

Réalisées au début du processus de fabrication des circuits intégrés, les tranchées d'isolation permettent d'éviter les fuites de courant latérales qui pourraient avoir lieu entre les transistors. Les tranchées sont remplies par un film d'oxyde de silicium réalisé par des procédés de dépôt chimiques en phase vapeur (aussi appelés CVD). Le remplissage des tranchées est couramment réalisé par un procédé CVD à pression sub-atmosphérique (SACVD TEOS/O3). Cependant, la capacité de remplissage de ce procédé pour les nœuds technologiques CMOS 28 nm et inférieurs est dégradée à cause de profils trop verticaux dans les tranchées. Cela induit la formation de cavités dans l'oxyde et entraine des courts-circuits. Afin de pallier ce problème, une nouvelle stratégie de remplissage en trois étapes est proposée pour la technologie CMOS 14 nm. Dans la première étape, un film mince d'oxyde est déposé dans les tranchées. Puis, dans la deuxième étape, les flancs du film sont gravés à l'aide d'un procédé de gravure innovant, basé sur un plasma délocalisé de NF3/NH3, permettant de créer une pente favorable au remplissage final réalisé au cours de la troisième étape. Le développement de cette nouvelle stratégie de remplissage s'est déroulé selon plusieurs axes. Tout d'abord, le procédé de dépôt a été caractérisé afin de sélectionner les conditions optimales pour la première étape de la stratégie. Puis, le procédé de gravure innovant a été caractérisé en détail. L'influence des paramètres de gravure a été étudiée sur pleine plaque et sur plaques avec motifs afin de comprendre les mécanismes de gravure et de changement de pente dans les tranchées. Enfin, dans un troisième temps, la stratégie de remplissage a été développée et intégrée pour la technologie CMOS 14 nm. Nous montrons ainsi qu'il est possible de contrôler le changement de pente avec les conditions de gravure et que cette stratégie permet un remplissage des tranchées d'isolation sans cavités. / Achieved at the beginning of the integrated circuits manufacturing, shallow trench isolation permits to electrically isolate transistors from each other's to avoid current leakage. Trenches are filled with silicon dioxide film deposited by chemical vapor deposition (also called CVD). Trenches gap-filling is usually performed by TEOS/O3 Sub-Atmospheric Chemical Vapor Deposition (TEOS/O3 SACVD). However, trenches gap-filling with SACVD process reveals some limitations for advanced technology nodes (mainly 28 nm & 14 nm) due to quasi-vertical trenches profile and slope sensitivity of SACVD, which can lead to voids formation in gap-filling oxide and consequently to electrical isolation failure. To solve this issue, a new three steps gap-fill strategy is proposed for the CMOS 14 nm technology node. During the first step, a thin oxide liner is deposited into trenches. Then, in the second step, film sidewalls are etched with an innovative process, based on downstream plasma of NF3/NH3, to create tapered profile favorable for final SACVD gap-fill achieved in the third step. The development of this strategy has followed three work leads. First, the deposition process has been characterized to select best conditions for the first step. Then, the innovative etching process has been widely characterized. The influence of etching parameters has been studied on blanket and patterned wafers to understand etching mechanisms and slope modification. Finally, the gap-fill strategy has been developed and integrated for the CMOS 14 nm technology node. We demonstrate that it is possible to control the slope modification by tuning etching conditions and that strategy allows a void-free trenches filling.

Dans le développement des technologies microélectroniques, l’analyse de défaillance permet par l’étude des mécanismes de défaillance potentiels de définir des solutions correctives. La mise en œuvre des techniques de localisation et d’observation des défauts requiert une méthodologie, dont l’étape clé est la préparation d’échantillons. Celle-ci doit continuellement évoluer pour s’adapter aux innovations technologiques qui introduisent de nouveaux matériaux, et augmentent la complexité des composants assemblés. Cette thèse s’est intéressée à la méthodologie de préparation d’échantillons pour l’analyse de défaillance de deux familles de produits : les produits discrets et IPAD, et les micro-batteries. Pour les produits discrets et IPAD, une optimisation de la méthodologie existante a été réalisée en intégrant de nouvelles approches, développées pour résoudre des cas jusqu’alors en échec. Pour les micro-batteries, les matériaux utilisés et leur architecture ont nécessité une remise en question complète de la méthodologie de préparation d’échantillon. / In the development of microelectronic technologies, the failure analysis makes it possible to define corrective actions thanks to the understanding of the failure mechanism. In order to define the most adequate localization and observation techniques to use, a failure analysis flow is required. The sample preparation is a key step of this flow. This flow must continuously evolve to take into account the technological innovations that introduce new materials, and increase the complexity of assembled components. This work concerned the sample preparation flow for the failure analysis of two product families : the discrete products and IPAD, and the micro-batteries. Concerning the discrete products and the IPAD, an optimization of the current flow was performed with the integration of new approaches developed to solve failed cases. For the micro-batteries, the used materials and their architecture required an entire reappraisal of the sample preparation flow.

High-speed digital to analogue converters (DAC), which are optimised for large bandwidth signal synthesis applications, are a fundamental building block and enabling technology in industrial instrumentation, military, communication and medical applications. The spurious free dynamic range (SFDR) is a key specification of high-speed DACs, as unwanted spurious signals generated by the DAC degrades the performance and effectiveness of wideband systems. The focus of this work is to enhance the SFDR performance of high-speed DACs. As bandwidth requirements increase, meeting the desired SFDR performance is further complicated by the increase in dynamic non-linearity. The most widely used architecture in high-speed applications is the current-steering DAC fabricated on CMOS technology. The current source finite output impedance, switch distortion and clock feedthrough are the greatest contributors to dynamic non-linearity and are difficult to improve with the use of MOS devices alone. This research proposes the use of BiCMOS technology that offers high performance, using heterojunction bipolar transistors (HBT) that, when combined with MOS devices, are able to improve on the linearity of the current-steering DAC and hence improve the SFDR. A design methodology is introduced based on BiCMOS fabrication technology to improve SFDR performance and places emphasis on the constraints of modern fabrication processes. A six-bit current-steering application-specific integrated circuit DAC is designed based on the proposed design methodology, which optimises the SFDR performance of high-speed binary weighted architectures by lowering current switch distortion and reducing the clock feedthrough effect to verify the hypothesis experimentally. A novel current source cell is implemented that comprises HBT current switches, negative channel metal-oxide semiconductor (NMOS) cascode and NMOS current source to overcome distortion by specifically enhancing the SFDR for high-speed DACs. A switch driver and low-voltage differential signalling receiver to achieve high-speed DAC performance and their influence on the SFDR performance are designed and discussed. The DAC is implemented using the International Business Machines Corporation (IBM) 8HP silicon germanium (SiGe) BiCMOS 130 nm technology. The DAC achieves a better than 21.96 dBc SFDR across the Nyquist band for a sampling rate of 500 MS/s with a core size of 0.1 mm2 and dissipates just 4 mW compared to other BiCMOS DACs that achieve similar SFDR performance with higher output voltages, resulting in much larger power dissipation. / Dissertation (MEng)--University of Pretoria, 2015. / Electrical, Electronic and Computer Engineering / MEng / Unrestricted