Recent developments in the area of microfabrication technologies, has enabled the fabrication of many radio frequency/microwave components with better performance and lower cost than possible with semiconductor based fabrication technology. Many of these microfabricated RF components such as switches and phase shifters, popularly known as RF MEMS, are aimed at reducing the insertion loss and improving other performance parameters such as linearity. For these devices size miniaturization is not necessarily important, as in practical subsystems, these components are integrated with RF front-ends on a laminate. This thesis deals with concepts of a low cost passive phase shifter fabricated in-situ on a microwave laminate. The operation of this Mesoscale Electrostatically actuated Phase shifter on microwave Laminate (MEPL) is similar to that of a micromachined distributed MEMS transmission line (DMTL) phase shifter. In spite of advantages of low losses, wide bandwidth, low DC power consumption and high linearity over semiconductor/MMIC technology, microfabricated phase shifters are often not used in field because of issues related to fabrication reliability, packaging and integration. On the other hand, the proposed MEPL will have all the advantages of conventional MEMS phase shifters with additional benefit of lower cost. Furthermore, these are integrable to form a monolithic phased array. A MEPL phase shifter of 50-bridges periodically distributed on the co-planar waveguide (CPW) transmission line is demonstrated in this thesis. MEMS air bridges are electrostatically actuated to vary the capacitance of the transmission line, which changes the phase velocity of the propagation RF signal, consequently phase at the output port. The realized MEPL is characterized for electromagnetic as well as electromechanical performance. The electromechanical characterization of this device is performed using a Laser Doppler Vibrometer (LDV). The measured data showed good agreement with the analytical data.. Major application of a phase shifter is in a phased array antenna system. MEPL is particularly suited for a monolithic phase array antenna. The proposed monolithic phased array antenna system fabrication approach utilizes extremely simple and economical modern printed circuit board technology to pattern the conventional microwave laminate and copper foil. A complete monolithic phased array antenna system is fabricated on a microwave laminate using an embedded phase shifter operating with electrostatic principles. Other components such as DC block and bias tee are integrated into the CPW-microstrip transitions to optimize the space and performance. Integrated phased array antenna is fabricated and tested to demonstrate the beam steering capability. Measured S11 is better than -15dB at the operating frequency of 9.8GHz. The beam steering capability is shown as proof of concept by showing the beam scan angle of 10deg with bias voltage of 125V. The mesoscale phase shifter demonstrated in this thesis has several advantages compared to micromachined phase shifters. The proposed fabrication approach does not use metal deposition/patterning process, which removes the need of high cost clean room and sophisticated films deposition equipments. Secondly, as there are no thin films used, stiction is not expected on phase shifters fabricated with this approach. Since this approach uses thicker metal films, the power handling capability is expected to be significantly higher than micromachined phase shifters. Since conventional phased array antenna system components are fabricated on a microwave laminate, micro machined phase shifters realized on semiconductor substrates are required to be packaged separately before integrating with such phased array circuits. Packaging of the micro-machined RF-MEMS/MEMS devices is still a major issue and contributes to a substantial part of the total cost. Unlike micromachined phase shifters which are required to be packaged and then embedded in phased array applications, device presented in this thesis is packaged in-situ. Compared to similar monolithic phased array antenna reported on silicon substrate which are limited by wafer size, these arrays can be easily extended for larger arrays on microwave laminate as these are available in large size. To summarize, the proposed fabrication approach for phase shifters overcomes many limitations of micromachined components for microwave applications while retaining most of their advantages compared to other existing approaches based on ferrites or semiconductor technologies.

Mixed signal system-on-package (SoP) technology is a key enabler for increasing functional integration, especially in mobile and wireless systems. Due to the presence of multiple dissimilar modules, each having unique power supply requirements, the design of the power distribution network (PDN) becomes critical. Typically, this PDN is designed as alternating layers of power and ground planes with signal interconnects routed in between or on top of the planes. The goal for the simulation of multi-layer power/ground planes, is the following: Given a stack-up and other geometrical information, it is required to find the network parameters (S/Y/Z) between port locations. Commercial packages have extremely complicated stack-ups, and the trend to increasing integration at the package level only points to increasing complexity. It is computationally intractable to solve these problems using these existing methods. The approach proposed in this thesis for obtaining the response of the PDN is the multi-layer finite difference method (M-FDM). A surface mesh / finite difference based approach is developed, which leads to a system matrix that is sparse and banded, and can be solved efficiently. The contributions of this research are the following: 1. The development of a PDN modeler for multi-layer packages and boards called the the multi-layer finite difference method. 2. The enhancement of M-FDM using multi-port connection networks to include the effect of fringe fields and gap coupling. 3. An adaptive triangular mesh based scheme called the multi-layer finite element method (MFEM) to address the limitations of M-FDM 4. The use of modal decomposition for the co-simulation of signal nets with the PDN. 5. The use of a robust GA-based optimizer for the selection and placement of decoupling capacitors in multi-layer geometries. 6. Implementation of these methods in a tool called MSDT 1.

Cette étude constitue une contribution dans un grand projet européen dénommé : 3DICE (3D Integration of Chips using Embedding technologies). La fiabilité mécanique et thermomécanique des composants 3D a été étudiée par des essais normalisés et des simulations numériques. L’essai de chute et le cyclage thermique ont été sélectionnés pour la présente étude. Des analyses de défaillance sont menées pour compléter les approches expérimentales. Les propriétés mécaniques des éléments constituant les composants ont fait l’objet d’une compagne de caractérisation complétée par des recherches bibliographiques. Les simulations numériques, dynamiques transitoires pour l’essai de chute et thermomécanique pour l’essai de cyclage thermique, ont été réalisées pour une estimation numérique de la tenue mécanique des composants. Les modèles numériques sont utilisés pour optimiser le design des composants et prédire les durées de vie en utilisant un modèle de fatigue. / This work establishes a contribution in an important European project mentioned 3DICE (3D Integration of Chips using Embedding technologies). The mechanical and thermomechanical reliability of 3D microelectronic components are studied by employing standardized tests and numerical modeling. The board level drop test and thermal cycling reliability tests are selected for this study. Failures analysis has been used to complete the experimental study. The mechanical properties of elements constituting the microelectronic components were characterized using DMA, tensile test and nanoindentation. Bibliographical researches have been done in order to complete the materials properties data. Numerical simulations using submodeling technique were carried out using a transient dynamic model to simulate the drop test and a thermomechanical model for the thermal cycling test. Numerical results were employing in the design optimization of 3D components and the life prediction using a fatigue model.

La miniaturisation et la complexification croissante des composants microélectroniques induit une sensibilisation et une fragilisation accrue des composants vis-à-vis des contaminations présentes dans les zones de productions appelées “salles blanches”. Dans ces espaces, le contrôle actuel de la contamination organique n’est pas suffisant puisqu’il ne permet pas d’éviter la contamination de surface des plaquettes de silicium et des optiques des robots de production utilisés pour la photolithographie. Un contrôle accru des concentrations des contaminants organiques dans les atmosphères des salles blanches devient donc nécessaire et de nouvelles méthodes analytiques doivent être développées et validées. Dans le cadre de ce travail, des méthodes d’analyse ont été développées et validées afin de disposer d’une gamme d’outils permettant un suivi rigoureux des contaminations. Ces outils permettent d’identifier et de quantifier les contaminations surfaciques des plaquettes de silicium par des composés organiques semi-volatils (phtalates et organophosphorés) mais aussi de déterminer les concentrations de composés organiques volatils présents dans l’atmosphère des salles blanches. Ces méthodes font appel aux technologies du WOS/ATD-GC-MS « Wafer Outgassing System/Automated Thermal Desorber–Gas Chromatography–Mass Spectrometry » et de la DART-ToF-MS « Direct Analysis in Real Time-Time of Flight–Mass Spectrometry » pour les analyses de surfaces et au PTR-ToF-MS « Proton Transfer Reaction – Time of Flight - Mass Spectrometry » pour l’analyse de l’atmosphère. / The recent advances in the miniaturization and complexification of microelectronic components induce an increase in the sensitivity of these components regarding the organic contamination present in the production zone called “clean room”. Although, the control of organic contamination in the clean room is very rigorous it does not avoid the contamination of silicon wafer surfaces and robot lenses used in the photolithography process. The later implies that new analytical methodologies should be developed and validated. In this work, analytical methods were developed and validated in order to have a panel of tools which allows careful monitoring of organic contaminants. These tools allow the identification and quantitation of the contamination of silicon wafer surface by semi-volatiles organic compounds (phthalates and organophosphates) and the determination of volatile organic compounds concentrations in the clean room atmosphere. These methods uses the WOS/ATD-GC-MS « Wafer Outgassing System/Automated Thermal Desorber–Gas Chromatography–Mass Spectrometry » technology and the DART-ToF-MS « Direct Analysis in Real Time-Time of Flight–Mass Spectrometry » technology for wafer surface analysis and the PTR-ToF-MS « Proton Transfer Reaction – Time of Flight - Mass Spectrometry » technology for gas-phase analysis.

Le travail présenté dans ce manuscrit de thèse s’inscrit dans le cadre d’une coopération scientifique notamment à travers le projet Région Centre « Connectic » en partenariat avec la société STMicroelectronics de Tours, les laboratoires LMR et CEMHTI. Il concerne les interconnexions des générations futures de circuits intégrés. Par rapport aux technologies d’interconnexion à base d’alliage métallique l’intégration de nanotubes de carbone (NTC) comme connecteur en microélectronique de puissance limiterait les effets d’échauffement dans les empilements de puces grâce à leurs propriétés de transport intéressantes. Les NTC peuvent assurer simultanément une bonne conduction électrique et un maintien mécanique des assemblages de puces. Les objectifs de ce travail étaient d’établir dans un premier temps un procédé reproductible d’élaboration de NTC verticalement alignés sur des substrats de nature multiple, et de réaliser dans un deuxième temps un véhicule test qui permet de caractériser leurs propriétés électrique, thermique et mécanique. Le dispositif expérimental d’élaboration présenté dans cette étude utilise le dépôt de catalyseur (Ni, Fe), la structuration par plasma d’hydrogène simultanément à un recuit thermique, ainsi que la méthode de CVD assistée par plasma radiofréquence d’éthylène et d’hydrogène pour la croissance des NTC. Des conditions optimales reproductibles d’obtention des NTC ont été établies à la suite d’une étude paramétrée utilisant notamment un diagnostic original de suivi in situ par spectroscopie Raman développé en collaboration avec le CEMHTI. Dans le cas d’un tapis de NTC de 10 µm de haut, des performances électrique (⍴ = 10⁻⁵ Ω.m), thermique (λth = 40-60 W.m⁻¹.K⁻¹), et mécanique (E = 480 GPa) comparables aux alliages métalliques ont été établies. Enfin, nous avons été capables d’assembler les substrats de la microélectronique et les NTC par un procédé de thermocompression. / The work presented in this thesis was a scientific cooperation between the society ST Microelectronics in Tours, the laboratories of LMR and CEMHTI within the framework of the project Région Centre “ConnectiC”. The main issue of that project concerns the interconnections for the future generation of integrated circuits. In comparison with the current interconnection technologies on metallic alloys as connectors; the integration of carbon nanotubes (CNT) as connector in power microelectronics would limit effects of overheating in the chip-structure due to their interesting transport properties. CNT can provide at the same time good electrical, thermal conduction characteristics and can be a mechanical support of chip packages. The aims of this work were: firstly, obtain a reproducible growth process of vertically aligned CNT on different kinds of substrate; secondly: to elaborate a test vehicle with CNT interconnects allowing the electrical, thermal and mechanical characterization. The experimental method used herein for synthesis of CNT interconnects combines the catalyst deposition (Ni, Fe), the structuration by both means of hydrogen plasma treatment and thermal annealing, and a RF PECVD method using ethylene and hydrogen for the CNT growth. Optimal reproducible conditions were found using a novel in situ Raman spectroscopy diagnostic developed in collaboration with the CEMHTI. The carpet of CNT (height of 10 µm) produced presents the electrical (⍴ = 10⁻⁵ Ω.m), thermal (λth = 40-60 W.m⁻¹.K⁻¹), and mechanical (E = 480 GPa) performances comparable with the metallic. Finally, by means of thermocompression, we assembled CNT on substrates from the microelectronics.

The thesis is focused on the research and development of a new hybrid one-wire bus with special use enabling microelectronic integration. The bus, its physical layer and protocol have been developed based on applied research to meet the complex requirements of a new application group. These requirements are especially laid on the bus robustness and its immunity to interference and to work under real operating conditions. Part of the thesis is a description of existing solutions of one-wire buses, definition of current solutions and setting of goals for research of the new bus. Further are made the design of protocol and operating parameters of the bus operating in low power and power mode. In conclusion, the thesis deals with the practical verification of the proposed solution and there is also suggested a perspective of follow-up research in this area.

With continued feature size reduction in microelectronics and with more than a billion transistors on a single integrated circuit (IC), on-chip interconnection has become a challenge in terms of processing-, electrical-, thermal-, and mechanical perspective. Today’s high-performance ICs have on-chip back-end-of-line (BEOL) layers that consist of copper traces and vias interspersed with low-k dielectric materials. These layers have thicknesses in the range of 100 nm near the transistors and 1000 nm away from the transistors close to the solder bumps. In such BEOL layered stacks, cracking and/or delamination is a common failure mode due to the low mechanical and adhesive strength of the dielectric materials as well as due to high thermally-induced stresses. However, there are no available cohesive zone models and parameters to study such interfacial cracks in sub-micron thick microelectronic layers. This work focuses on developing framework based on cohesive zone modeling approach to study interfacial delamination in sub-micron thick layers. Such a framework is then successfully applied to predict microelectronic device reliability. As intentionally creating pre-fabricated cracks in such interfaces is difficult, this work examines a combination of four-point bend and double-cantilever beam tests to create initial cracks and to develop cohesive zone parameters over a range of mode-mixity. Similarly, a combination of four-point bend and end-notch flexure tests is used to cover additional range of mode-mixity. In these tests, silicon wafers obtained from wafer foundry are used for experimental characterization. The developed parameters are then used in actual microelectronic device to predict the onset and propagation of crack, and the results from such predictions are successfully validated with experimental data. In addition, nanoindenter-based shear test technique designed specifically for this study is demonstrated. The new test technique can address different mode mixities compared to the other interfacial fracture characterization tests, is sensitive to capture the change in fracture parameter due to changes in local trace pattern variations around the vicinity of bump and the test mimics the forces experienced by the bump during flip-chip assembly reflow process. Through this experimental and theoretical modeling research, guidelines are also developed for the reliable design of BEOL stacks for current and next-generation microelectronic devices.

Although it has been well established that abnormal group delay is a real physical phenomenon and is not in violation of Einstein causality, there has been little investigation into whether or not such abnormal behaviour can be used to reduce signal latency in practical communication systems in the presence of noise. In this thesis, we use time-varying probability of error to determine if abnormal group delay “channels” can offer reduced signal latency. Since the detection system plays a critical role in the analysis, three important detection systems are considered: the correlation, matched filter and envelope detection systems. Our analysis shows that for both spatially negligible microelectronic systems and spatially extended microwave systems, negative group delay “channels” offer reduced signal latency as compared to conventional “channels”. The results presented in the thesis can be used to design a new generation of electronic and microwave interconnects with reduced or eliminated signal latency.

Although it has been well established that abnormal group delay is a real physical phenomenon and is not in violation of Einstein causality, there has been little investigation into whether or not such abnormal behaviour can be used to reduce signal latency in practical communication systems in the presence of noise. In this thesis, we use time-varying probability of error to determine if abnormal group delay “channels” can offer reduced signal latency. Since the detection system plays a critical role in the analysis, three important detection systems are considered: the correlation, matched filter and envelope detection systems. Our analysis shows that for both spatially negligible microelectronic systems and spatially extended microwave systems, negative group delay “channels” offer reduced signal latency as compared to conventional “channels”. The results presented in the thesis can be used to design a new generation of electronic and microwave interconnects with reduced or eliminated signal latency.

L’industrie microélectronique est un domaine compétitif, confronté de manière permanente à plusieurs défis. Pour évaluer les étapes de fabrication, des tests de qualité sont appliqués. Ces tests étant discontinus, une défaillance des équipements peut causer une dégradation de la qualité du produit. Des alarmes peuvent être déclenchées pour indiquer des problèmes. D’autre part, on dispose d’une grande quantité de données des équipements obtenues à partir de capteurs. Une gestion des alarmes, une interpolation de mesures de qualité et une réduction de données équipements sont nécessaires. Il s’agit dans notre travail à développer des méthodes génériques d’analyse multi-variée permettant d’agréger toutes les informations disponibles sur les équipements pour prédire la qualité de produit en prenant en compte la qualité des différentes étapes de fabrication. En se basant sur le principe de reconnaissance de formes, nous avons proposé une approche pour prédire le nombre de produits restant à produire avant les pertes de performance liée aux spécifications clients en fonction des indices de santé des équipement. Notre approche permet aussi d'isoler les équipements responsables de dégradation. En plus, une méthodologie à base de régression régularisée est développée pour prédire la qualité du produit tout en prenant en compte les relations de corrélations et de dépendance existantes dans le processus. Un modèle pour la gestion des alarmes est construit où des indices de criticité et de similarité sont proposés. Les données alarmes sont ensuite utilisées pour prédire le rejet de produits. Une application sur des données industrielles provenant de STMicroelectronics est fournie. / The microelectronics industry is a highly competitive field, constantly confronted with several challenges. To evaluate the manufacturing steps, quality tests are applied during and at the end of production. As these tests are discontinuous, a defect or failure of the equipment can cause a deterioration in the product quality and a loss in the manufacturing Yield. Alarms are setting off to indicate problems, but periodic alarms can be triggered resulting in alarm flows. On the other hand, a large quantity of data of the equipment obtained from sensors is available. Alarm management, interpolation of quality measurements and reduction of correlated equipment data are required. We aim in our work to develop generic methods of multi-variate analysis allowing to aggregate all the available information (equipment health indicators, alarms) to predict the product quality taking into account the quality of the various manufacturing steps. Based on the pattern recognition principle, data of the degradation trajectory are compared with health indices for failing equipment. The objective is to predict the remaining number of products before loss of the performance related to customer specifications, and the isolation of equipment responsible for degradation. In addition, regression- ased methods are used to predict the product quality while taking into account the existing correlation and the dependency relationships in the process. A model for the alarm management is constructed where criticality and similarity indices are proposed. Then, alarm data are used to predict the product scrap. An application to industrial data from STMicroelectronics is provided.