Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009. / Committee Chair: Dr. Swaminathan, Madhavan; Committee Member: Dr. Chatterjee, Abhijit; Committee Member: Dr. Lim, Sungkyu. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Thesis (Ph. D.)--University of Texas at Austin, 1999. / Vita. Includes bibliographical references (leaves 110-112). Available also in a digital version from Dissertation Abstracts.

Thesis (M.S.)--State University of New York at Binghamton, Department of Physics, Applied Physics and Astronomy, 2009. / Includes bibliographical references.

Thesis (Ph.D.)--Hong Kong University of Science and Technology, 2005. / Includes bibliographical references. Also available in electronic version.

Microelectronic fabrication of Si typically involves high-temperature or high-energy processes. For instance, wafer fabrication, transistor fabrication, and silicidation are all above 500°C. Contrary to that tradition, we believe low-energy processes constitute a better alternative to enable the industrial application of single-molecule devices based on 2D materials. The present work addresses the postsynthesis processing of graphene at unconventional low temperature, low energy, and low pressure in the poly methyl-methacrylate- (PMMA-) assisted transfer of graphene to oxide wafer, in the electron-beam lithography with PMMA, and in the plasma patterning of graphene with a PMMA ribbon mask. During the exposure to the oxygen plasma, unprotected areas of graphene are converted to graphene oxide. The exposure time required to produce the ribbon patterns on graphene is 2 minutes. We produce graphene ribbon patterns with ∼50 nm width and integrate them into solid state and liquid gated transistor devices. / )e submitted manuscript has been created by UChicago Argonne, LLC, Operator of Argonne National Laboratory (“Argonne”). Argonne, a U.S. Department of Energy Office of Science laboratory, is operated under Contract DE-AC02-06CH11357. )e U.S. Government retains for itself, and others acting on its behalf, a paid-up nonexclusive, irrevocable worldwide license in said article to reproduce, prepare derivative works, distribute copies to the public, and perform publicly and display publicly, by or on behalf of the government. Funding text #2 )e Center for Nanoscale Materials was supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract DE-AC02-06CH11357. )e authors also acknowledge financial support from Argonne National Laboratory’s Laboratory-Directed Research and Development Strategic Initiative. / Revisión por pares

En combinant l’expertise du Cermav dans la conception de films minces de très haute résolution obtenus par auto-assemblage de glycopolymères biosourcés et le savoir-faire du LETI sur les procédés de lithographie innovante, l’objectif de ce projet de thèse est d’évaluer ces nouveaux copolymères biosourcés -associant des oligosaccharides- comme solution alternative pour la nano lithographie de demain. En effet, ces dernières années l’équipe de « Physico-chimie des glycopolymères » du Cermav dirigée par R. Borsali a développé une nouvelle classe de glycopolymères (type PS-Maltoheptaose, PCL-Maltoheptaose, Xyloglycan-PSSI) pouvant s’auto-organisér avec une résolution de 5nm, dépassant ainsi largement la résolution atteinte aujourd’hui par les seuls copolymères à blocs issus du pétrole type PS-PMMA (20nm). En parallèle, durant les deux dernières années, le Cea/Leti a validé le potentiel des procédés basés sur l’auto assemblage des copolymères à bloc type PS-b-PMMA (résolution 20nm) comme solution alternative aux techniques de lithographie actuelles. Ces résultats positionnent le Cea/Leti dans l’état de l’art international et constituent une bonne base pour intégrer, dans le domaine de la nano-electronique, de nouveau systèmes à plus forte résolution (<10nm), tels que ceux développés par le Cermav. Le travail de thèse proposé se déroulera en trois temps : – Dans un premier temps le candidat adressera la synthèse et la caractérisation de nouveaux copolymères à blocks hybrides associant des oligosaccharides. – Ensuite il va d’intéressé à l’élaboration de glycofilms nano-organisés ainsi que à l’identification des facteurs importants jouant sur la nano-organisation. – Et finalement le contrôle de l’organisation à l’échelle nanométrique par grapho-épitaxie pour des applications lithographiques sera adressé. Deux applications seront visées : le contact et la ligne (phases cylindriques et lamellaires). La compatibilité du procès avec les contraintes de la micro-électronique sera également détaillée. / Combining the Cermav expertise in the thin films design with very high resolution obtained by self-assembly of glycopolymers biobased and the know-how of LETI on innovative lithography processes, the objective of this thesis is to evaluate these new bio-based copolymers, combining-oligosaccharides as an alternative for nano lithography tomorrow. Indeed, in recent years the team of "Physical Chemistry of glycopolymers" of Cermav directed by R. Borsali has developed a new class of glycopolymers (PS-maltoheptaose, PCL-maltoheptaose, Xyloglycan-PSSI) can self-organize with a resolution of 5 nm, far surpassing the resolution reached today only by block copolymers from Oil PS-PMMA (20 nm). In parallel, during the last two years, Cea / Leti has validated the potential methods based on self-assembly of block copolymers PS-b-PMMA (20 nm resolution) as an alternative to the current lithography techniques. These results position the Cea / Leti in the international state of the art and provide a good basis for integration in the field of nano-electronics, new systems with higher resolution (<10 nm) as those developed by the Cermav. The proposed thesis work will take place in three stages: - First time candidate address the synthesis and characterization of new copolymers blocks combining hybrid oligosaccharides. - Then he's going to be interested in the development of nano-glycofilms organized as well as to identify important factors playing on the nano-organization. - And finally the control of the organization at the nanoscale by grapho-epitaxy for lithographic applications will be addressed. Two applications are described: the contact line (cylindrical and lamellar phases). Compatibility constraints trial microelectronics will also be detailed.

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados. / Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power consumption since the buffer size and the mesh capacitance are not changed.

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados. / Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power consumption since the buffer size and the mesh capacitance are not changed.

Malhas de relógio são arquiteturas de rede de relógio adequadas para distribuir confiavelmente o sinal de relógio na presença de variações de processo e ambientais. Tal propriedade se torna muito importante nas tecnologias submicrônicas onde variações têm um papel importante. A confiabilidade da malha de relógio é devido aos caminhos redundantes conectando o sinal de relógio até os receptores de forma que variações afetando um caminho possam ser compensadas pelos outros caminhos. A confiabilidade vem ao custo de mais consumo de potência e fiação. Desta forma fica claro o balanceamento necessário entre distribuir confiavelmente o sinal de relógio (mais redundância) e o consumo de potência e aumento de fiação. O clock skew é definido como a diferença entre os tempos de chegada do sinal de clock nos seus receptores. Quanto maior é o clock skew, mais lento o circuito precisa operar. Além de diminuir a velocidade do circuito, um valor alto de clock skew aumenta a probabilidade de o circuito não funcionar devido às variações. Neste trabalho, nos focamos no problema de clock skew. Inicialmente extraímos informações úteis de como o comprimento da fiação e a capacitância variam a medida que o tamanho da malha varia. São apresentadas fórmulas analíticas que encontram o tamanho ótimo para ambos objetivos e é apresentado um estudo de como o clock skew varia a medida que nos afastamos do tamanho ótimo da malha de relógio. Um método para a redução de clock skew através do deslocamento dos buffers também é apresentado. Tal melhoria no clock skew não afeta o consumo de potência já que o tamanho dos buffers e a malha não são alterados. / Clock meshes are a suitable clock network architecture for reliably distributing the clock signal under process and environmental variations. This property becomes very important in the deep sub-micron technology where variations play a main role. The clock mesh reliability is due to redundant paths connecting clock buffers to clock sinks, so that variations affecting one path can be compensated by other paths. This comes at cost of more power consumption and wiring resources. Therefore it is clear the tradeoff between reliably distributing the clock signal (more redundancy) and the power and resource consumption. The clock skew is defined as the difference in the arrival time of clock signal at clock sinks. The higher is the clock skew, the slower is the circuit. Besides slowing down the circuit operation, a high clock skew increases the probability of circuit malfunction due to variations. In this work we focus on the clock skew problem. We first extract some useful information on how the clock wirelength and capacitance change as the mesh size changes. We present analytical formulas to find the optimum mesh size for both goals and study how the clock skew varies as we move further away from the optimum mesh size. We also present a method for reducing the clock mesh skew by sliding buffers from the position where they are traditionally placed. This improvement comes at no increasing cost of power consumption since the buffer size and the mesh capacitance are not changed.

Les systèmes de télécommunications optiques sont au coeur de la révolution Internet depuis son origine. Le transport optique est la technologie incontournable pour pouvoir véhiculer le trafic de données à l’échelle mondiale. Depuis quelques années, l’explosion de la quantité de données nécessite de disposer de systèmes pouvant fonctionner à des débits plus élevés. Par ailleurs, la bande passante de la fibre optique, longtemps considérée comme infinie, est désormais repoussée à ses limites. De plus, les composants électro-optiques aux différentes interfaces ne progressent plus à un rythme suffisant pour permettre d’augmenter significativement le débit binaire. La problématique de l’égalisation est un sujet bien connu dans le domaine des télécommunications optiques. Cependant, pour augmenter le débit des systèmes, vers 100 Gb/s et au-delà, des formats de modulation principalement multi-niveaux sont aujourd’hui nécessaires. Dans ce nouveau contexte, l’égalisation devient indispensable même si elle est plus complexe à mettre en oeuvre à ce niveau de rapidité. Ce travail de thèse s’intéresse à l’étude et à la réalisation des égaliseurs analogiques pour les formats de modulation multi-niveaux à des débits binaires de 100 Gb/s. Les différentes réalisations sont basées sur la technologie de transistor bipolaire à double hétérojonction (TBDH) en phosphure d’indium (InP), développée au sein du laboratoire III-V Lab et présentant un couple fT/fmax aux alentours de 400 GHz, avec une tension de claquage supérieure à 4V. Plusieurs égaliseurs analogiques ont été conçus et mesurés au cours de cette thèse. Des circuits d’égalisation comportant peu de transistors ont été développés, afin de démontrer des meilleures performances en terme de peaking fréquentiel comparées à l’état de l’art international. À partir de ces briques de base, nous avons conçu des égaliseur sanalogiques linéaires de type feed-forward, répondant parfaitement à la problématique d’égalisation des systèmes de télécommunications optiques actuels utilisant des formats de modulation multi-niveaux. Les mesures de ces égaliseurs analogiques réalisés ont démontré l’égalisation de signaux numériques sévèrement filtrés à un débit binaire de 100 Gb/s. / Optical communication systems are the core of the current Internet revolution. Indeed, optical network is the main technology in order to spread global IP traffic. The growing demand of data bandwidth all over the world are pushing optical communication systems beyond their limits. Thus it requires systems which are higher data rate compliant. Besides, the fiber optic has been historically considered as having an infinite bandwidth, but its physical limits are being gradually reached. Moreover, electro-optical components are no more keeping pace with the current increasing data rate.Equalization is a well-known subject in the optical communication field. In order to increase system data rates beyond 100 Gb/s, multilevel format modulation are required. In this context, equalization is still mandatory but more complex to implement.The goal of this thesis is to study and design analog equalizers for complex modulation format with a 100-Gb/s bit rate. All of these circuits are based on indium-phosphide (InP) double heterojunction bipolar transistor (DHBT) technology from III-V Lab. Its fT/fmax couple almost reaches 400 GHz, and the breakdown voltage is higher than4V. Many analog equalizers have been designed and measured over this thesis. First of all, equalization circuits with few transistors have been designed in order to demonstrate state-of-the-art analog equalizer performances, mainly regarding peaking frequency parameter. From these building blocks, feed-forward analog equalizers have been studied and designed, thus answering to the initial requirement of current optical communication systems using complex modulation format. Measurements demonstrated a remarkable equalization performance on strongly filtered 100-Gb/s digital signals.