In this dissertation, we study properties of quantum interaction phenomena in two-dimensional (2D) and one-dimensional (1D) electronic systems in p-GaAs micro- and nano-scale devices. We present low-temperature magneto-transport data from three forms of low-dimensional systems 1) 2D hole systems: in order to study interaction contributions to the metallic behavior of 2D systems 2) Bilayer hole systems: in order to study the many body, bilayer quantum Hall state at nu = 1 3) 1D hole systems: for the study of the anomalous conductance plateau G = 0.7 ???? 2e2/h The work is divided into five experimental studies aimed at either directly exploring the properties of the above three interaction phenomena or the development of novel device structures that exploit the strong particle-particle interactions found in p-GaAs for the study of many body phenomena. Firstly, we demonstrate a novel semiconductor-insulator-semiconductor field effect transistor (SISFET), designed specifically to induced 2D hole systems at a ????normal???? AlGaAs-on-GaAs heterojunction. The novel SISFETs feature in our studies of the metallic behavior in 2D systems in which we examine temperature corrections to ????xx(T) and ????xy(T) in short- and long-range disorder potentials. Next, we shift focus to bilayer hole systems and the many body quantum Hall states that form a nu = 1 in the presence of strong interlayer interactions. We explore the evolution of this quantum Hall state as the relative densities in the layers is imbalanced while the total density is kept constant. Finally, we demonstrate a novel p-type quantum point contact device that produce the most stable and robust current quantization in a p-type 1D systems to date, allowing us to observed for the first time the 0.7 structure in a p-type device.

Microelectronic interconnections require advanced joining techniques. Direct metal bonding methods, which include thercomsonic and thermocompression bonding, offer remarkable advantages over soldering and adhesives joining. These processes are reviewed in this paper. The progress made in this area is outlined. Some work concerned with the bonding modeling is also presented. This model is based on the joint interface mechanics resulting from compression. Both bump and substrate deformation are taken into account. The improved understanding of the relationship between the deformation and bonding formation may provide more accurate joint evaluation criterion. / Singapore-MIT Alliance (SMA)

A new inverse analysis method is presented to identify parameters of heat convection in microelectronic packages. This approach adopts a modified Micro Genetic Algorithm (µGA) in finding the global optimum of parameters. A reduced-basis approach is introduced in the forward heat transfer analysis so as to significantly improve the efficiency in the calculation. Different identification procedures are employed to identify heat convection coefficients of a typical microelectronic package. Comparisons between different algorithms are performed. Results show that the use of the reduced-basis method together with the modified µGA outperforms the conventional GAs significantly. The presented method of coefficient identification is ideal for practical applications. It is efficient enough even for online analysis of both forward and inverse problem. / Singapore-MIT Alliance (SMA)

Hydrogen is added to Graphene in various compositions and configurations to modify the band structure to produce a suitable band gap for microelectronic applications. Optical and vibrational spectra are calculated as a means of characterization. Calculations performed using DFT and Quantum Espresso. / UOIT

"More Than Moore's Law" is the driving principle for the electronic packaging industry. This principle focuses on system integration instead of transistor density in order to achieve faster, thinner, and smarter electronic devices at a low cost. A core area of electronics packaging is interconnection technology, which enables ultra-miniaturization and high functional density. Solder bump technology is one of the original, and most common interconnection methods for flip chips. With growing demand for finer pitch and higher number of I/Os, solder bumps have been forced to smaller dimensions and therefore, are subjected to higher current densities. However, the technology is now reaching its fundamental limitations in terms of pitch, processability, and current-handling due to electromigration. Electromigration in solder bumps is one of the major causes of device failures. It is accelerated by many factors, one of which is current crowding. Current crowding is the non-uniform distribution of current at the interface of the solder bump and under-bump metallurgy, resulting in an increase in local current density and temperature. These factors, along with the formation of intermetallic compounds, can lead to voiding and ultimately failure. Electromigration in solder bumps has prevented pitch-scaling below 180-210 microns, producing a shift in the packaging industry to other interconnection approaches, specifically copper pillars with solder. This research aims to explore the electromigration resistance of an adhesive-based copper-to-copper (Cu-Cu) interconnection method without solder, which is thermo-compression bonded at a low temperature of 180C. While solder bumps are more susceptible to electromigration, Cu is capable of handling two orders of magnitude higher current density. This makes it an ideal candidate for next generation flip chip interconnections. Using finite element analysis, the current crowding and joule heating effects were evaluated for a 30 micron diameter Cu-Cu interconnection in comparison with two existing flip chip interconnection techniques, Cu pillar with solder and Pb-free solder. A test vehicle (TV) was fabricated for experimental analysis with 760 bumps arranged in an area-array format with a bump diameter of 30 micron. Thermo-mechanical reliability of the test vehicle was validated under thermal cycling from -55C to 125C. The Cu-Cu interconnections were then subjected to high current and temperature stress from 1E4 to 1E6 amps per square centimeter at a temperature of 130C. The results establish the high thermo-mechanical reliability and high electromigration resistance of the proposed Cu-Cu interconnection technology.

Avatrel 8000P's excellent photo-definition properties and mechanical strength make it an ideal polymer collar material. Avatrel 8000P is a high contrast, I-line sensitive mixture that can be developed in traditional aqueous-base developers. The great photolithographical performance of this photopolymer can be partly contributed to the minimal amount of light absorbed by the base norbornene polymer. The processing conditions noted in this work are an optimized version, which have been shown to give superior photolithographical performance. The simple baking procedures make Avatrel 8000P easier to process than SU-8. The ability to develop Avatrel 8000P in aqueous base can reduce chemical waste. As shown by SEM images, high fidelity structures with aspect ratios of 7:1 can be fabricated in thick films with vertical sidewalls. Bonding between two copper surfaces over various gap sizes was achieved by electroless deposition without the addition of surfactants or inhibitors in the bath. The effect of anneal temperature on the electroless bond formed was analyzed. The electroless bond strength increased with anneal temperature. However, the bond strength estimation for samples annealed at 80°C to 120°C is a minimum value due to the failure location of most of the pillars and the resulting area used in the calculation of bond strength. Grain growth from copper recrystallization and removal of small defects improve the bond strength. Large voids at the interface of the two pillars were related to rough starting surfaces for the electroplated pillars.

Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC chip/package modules on a single platform gives rise to geometrically complex structures with strong electromagnetic phenomena. This motivates our work on a fast full-wave solution for the analysis of such modules, thus contributing to the reduction in design cycle time without loss of accuracy. Traditionally, fast design approaches consider only approximate electromagnetic effects, giving rise to lumped-circuit models, and therefore may fail to accurately capture the signal integrity, power integrity, and electromagnetic interference effects. As part of this research, a second order frequency domain full-wave susceptance element equivalent circuit (SEEC) model will be extracted from a given structural layout. The model so obtained is suitably reduced using model order reduction techniques. As part of this effort, algorithms are developed to produce stable and passive reduced models of the original system, enabling fast frequency sweep analysis. Two distinct projection-based second order model reduction approaches will be considered: 1) matching moments, and 2) matching Laguerre coefficients, of the original system's transfer function. Further, the selection of multiple frequency shifts in these schemes to produce a globally representative model is also studied. Use of a second level preconditioned Krylov subspace process allows for a memory-efficient way to address large size problems.

L’industrie microélectronique arrive aujourd’hui à concevoir des transistors atteignant quelquesdizaines de nanomètres. A de telles dimensions, les problématiques de fiabilité et de variabilité des dispositifsprennent une ampleur toujours plus importante. Notamment, le couplage de ces deux difficultés nécessite uneétude approfondie pour garantir des estimations correctes de la durée de vie des dispositifs. Aujourd’hui, ladégradation BTI (pour Bias Temperature Instability), due principalement aux mécanismes de piégeage dansl’oxyde de grille, apparait comme étant la principale source de dégradation responsable du vieillissement destransistors. Ce manuscrit présente une étude complète de la dégradation BTI intervenant sur des transistors depetites et grandes dimensions et sur des cellules mémoires SRAM (pour Static Random Access Memory). Dansun premier temps, une présentation des différentes méthodes de caractérisations rapides permettant demesurer correctement cette dégradation est faite. L’importance de l’utilisation de techniques de mesuresrapides afin de limiter les effets de relaxation qui succèdent à la dégradation BTI est clairement exposée. Puis, àl’aide de ces techniques de mesures, une étude exclusivement consacrée à la caractérisation et la modélisationde la dégradation NBTI (pour Negative BTI) sur des dispositifs de grandes dimensions est réalisée. Ensuite, lemanuscrit se focalise sur la dégradation intervenant dans des dispositifs de petites dimensions : transistors etcellules mémoires. Tout d’abord, une modélisation des phénomènes de piégeages dans l’oxyde de grille depetits transistors est effectuée. En particulier, des simulations 3D électrostatiques ont permis d’expliquerl’influence des pièges d’oxyde sur la tension de seuil (VT) dans des transistors décananométriques. Enfin, uneétude de la fiabilité de cellules SRAM est présentée. Notamment, nous montrons comment évoluent lesperformances et le fonctionnement des cellules lorsque les transistors qui les constituent sont affectés par unedégradation BTI. / Nowadays, microelectronic industry is able to manufacture transistors with gate length down to 30nm.At such scales, the variability and reliability issues are a growing concern. Hence, understanding the interplaybetween these two concerns is essential to guarantee good lifetime estimation of the devices. Currently, theBias Temperature Instability (BTI), which is mostly due to the carrier trapping occurring in the gate oxide,appears to be the principal source of degradation responsible for the ageing of transistor device. Thismanuscript presents a complete study of the BTI degradation occurring on small and big transistors and onStatic Random Access Memory (SRAM) cells. Thus, as a first step, several electrical characterization techniquesto evaluate the BTI degradation are presented. The necessity of fast measurement in order to avoid most of therelaxation effect occurring after the BTI stress is emphasized. Then, using these fast measurement techniques,a complete study of the Negative BTI (NBTI) on large devices is presented. Then, the manuscript focuses on thesmall devices: transistors and memory cells. First, a modeling of the trapping mechanism in the gate oxide ofsmall transistor is presented. In particular, 3D electrostatic simulations allowed us to understand the particularinfluence of the traps over the threshold voltage (VT) of the small transistors. Finally, the case of the SRAM isstudied. Finally, the impact of the degradation occurring at transistor level and impacting the functioning of theSRAM bitcells is investigated.

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