Afin d’améliorer la durée de vie des micro-relais MEMS ohmiques, plusieurs traitements de surface de films minces d’or sont réalisés pour augmenter leur dureté tout en conservant une résistance électrique de contact faible.Les revêtements ultrafins de ruthénium (20 à 100 nm) déposés sur l’or augmentent la dureté des surfaces de contact d’un facteur 15. L’implantation ionique de bore ou d’azote (3,5 ppm à 10 % atomique) à une profondeur de 100 nm dans le film mince d’or permet d’atteindre un gain en dureté de 75%. Le contrôle (AFM, EBSD et DRX) de la microstructure induite met en évidence le durcissement par solution solide par insertion. Mais au-delà de 1% atomique, les atomes d’azote quittent le réseau cristallin de l’or pour former des précipités de nitrure d’or.L’analyse AFM (rugosité et diamètre) des empreintes résiduelles (quelques μm²) réalisées par nano-indentation sphérique, imitant le cyclage et le fluage des surfaces de contact de ces MEMS, démontre l’apport de ces traitements de surface. De plus, leurs résistances électriques de contact, mesurées par nano-indentation instrumentée reproduisant un micro-contact identique à un dispositif réel, sont similaires à celle de l’or pur.La modélisation discrète mécanique du contact rugueux est ajustée à la mesure de la déformation mécanique de nano-rugosités en comparant les relevés topographiques réalisés par AFM avant et après nano-indentation sphérique. La comparaison entre la modélisation et la mesure de la résistance électrique de contact indique que pour les gammes de force utilisées dans les micro-relais MEMS (inférieure au mN), seule une fraction allant de 2% à 9% de la surface de contact réelle est conductrice. / Ohmic MEMS switches made by gold thin films are promising devices but their mechanical contacts are one of the critical concerns for enhancing reliability. For this reason, surface processes are investigated in this work to improve both mechanical and electrical contact resistance (ECR) of MEMS gold contacts. Ruthenium ultra-thin films (20 to 100 nm) deposited on a top of gold layer increase surface hardness by a factor of fifteen. In parallel, surface implantations of both boron (<10% atomic) or nitrogen (<0.1% atomic) into gold reveals a solid solution hardening by insertion, thus increasing the hardness of initial film by about 75% and 25%, respectively. Notably, above 0.1% atomic of nitrogen, atoms precipitate from the tetra or octahedral sites of gold inducing a decrease of hardness.Static and multi load/unload spherical nano-indentation are performed on treated gold thin films to simulate the mechanical actuation of ohmic MEMS switches. Analysis of residual imprints (about few µm²) from treated surface exhibits both minimal local deformation and adhesion forces that reduce stiction probability. In-situ measurement of ECR for treated gold by instrumented nano-indentation, reproducing the design of MEMS, is in the same range of pure gold-to-gold configuration.A new mechanical discrete model of rough contact is introduced, confronted and validated to the experimental mechanical surface deformation obtained by comparison of AFM images before and after spherical nano-indentation. An electrical discrete model is added and fitted to the ECR measurements. In ohmic MEMS switch load range (< 1 mN), the conductive area is found to be about 2% to 9% of the real contact area.

The electrical properties of ZnO and contacts to ZnO have been investigated using different techniques. Temperature dependent Hall (TDH) effect measurements have been used to characterize the as-received melt grown ZnO samples in the 20 – 330 K temperature range. The effect of argon annealing on hydrogen peroxide treated ZnO samples has been investigated in the 200 – 800oC temperature range by the TDH effect measurement technique. The experimental data has been analysed by fitting a theoretical model written in Matlab to the data. Donor concentrations and acceptor concentrations together with the associated energy levels have been extracted by fitting the models to the experimentally obtained carrier concentration data by assuming a multi-donor and single charged acceptor in solving the charge balance equation. TDH measurements have revealed the dominance of surface conduction in melt grown ZnO in the 20 – 40 K temperature range. Surface conduction effects have proved to increase with the increase in annealing temperature. Surface donor volume concentrations have been determined in the 200 – 800oC by use of theory developed by D. C. Look. Good rectifying Schottky contacts have been fabricated on ZnO after treating the samples with boiling hydrogen peroxide. Electrical properties of these Schottky contacts have been investigated using current-voltage (IV) and capacitance-voltage (CV) measurements in the 60 – 300 K temperature range. The Schottky contacts have revealed the dominance of predominantly thermionic emission at room temperature and the existence of other current transport mechanisms at temperatures below room temperature. Polarity effects on the Schottky contacts deposited on the O-polar and Zn-polar faces of ZnO have been demonstrated by the IV technique on the Pd and Au Schottky contacts at room temperature. Results obtained indicate a strong dependence of the Schottky contact quality on the polarity of the samples at room temperature. The quality of the Schottky contacts have also indicated their dependence on the type of metal used with the Pd producing contacts with the better quality as compared to the Au. Schottky barrier heights determined using temperature dependent IV measurements have been observed to increase with increasing temperature and this has been explained as an effect of barrier inhomogeneities, while the ones obtained from CV measurements have proved to follow the negative temperature coefficient of the II – VI semiconductor material, i.e. a decrease in barrier height with increasing temperature. However, the values have proved to be larger than the energy gap of ZnO, an effect that has been explained as caused by an inversion layer. Copyright / Dissertation (MSc)--University of Pretoria, 2010. / Physics / unrestricted

<div>The work discussed in this document seeks to integrate conductive additives with energetic material systems to offer an alternative source of ignition for the energetic material. By utilizing the conductive properties of the additives, ohmic heating may serve as a method for preheating and igniting an energetic material. This would allow for controlled ignition of the energetic material without the use of a traditional ignition source, and could also result in easier system fabrication.</div><div>For ohmic heating to be a viable method of preheating or igniting these conductive energetic materials, there cannot be significant impact on the energetic properties of the energetic materials. Various mass solids loadings of graphene nanoplatelets (GNPs) were mixed with a reactive mixture of aluminum (Al)/polyvinylidene fluoride (PVDF) to test if ohmic heating ignition was feasible and to inspect the impact that these loadings had on the energetic properties of the Al/PVDF. Results showed that while ohmic heating was a plausible method for igniting the conductive energetic samples, the addition of GNPs degraded the energetic properties of the Al/PVDF. The severity of this degradation was minimized at lower solids loadings of GNPs, but this consequently resulted in larger voltage input requirements to ignite the conductive energetic material. This was attributable to the decreased conductivities of the samples at lower solids loading of GNPs.</div><div>In hopes of conserving the energetic properties of the Al/PVDF while integrating the conductive additives, additive manufacturing techniques, more specifically fused filament fabrication, was used to print two distinct materials, Al/PVDF and a conductive composite, into singular parts. A CraftBot 3 was used to selectively deposit Conductive Graphene PLA (Black Magic) filament with a reactive filament comprised of a PVDF binder with 20% mass solids loadings of aluminum. Various amounts of voltage were applied to these conductive energetic samples to quantify the time to ignition of the Al/PVDF as the applied voltage increased. A negative correlation was discovered between the applied voltage and time to ignition. This result was imperative for demonstrating that the reaction rate could be influenced with the application of higher applied voltages.</div><div>Fused filament fabrication was also used to demonstrate the scalability of the dual printed conductive energetic materials. A flexural test specimen made of the Al/PVDF was printed with an embedded strain gauge made of the Black Magic filament. This printed strain gauge was tested for dual purposes: as an igniter and as a strain sensor, demonstrating the multi-functional use of integrating conductive additives with energetic materials.</div><div>In all, the experiments in this document lay a foundation for utilizing conductive additives with energetic materials to offer an alternative form of ignition. Going forward, ohmic heating ignition may serve as a replacement to current, outdated methods of ignition for heat sensitive energetic materials.</div>

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Le carbure de silicium (SiC) est un semi-conducteur à large bande d’énergie interdite, remarquable par ses propriétés physiques situées à mi-chemin entre le silicium et le diamant. Ceci suscite actuellement un fort intérêt industriel pour son utilisation dans la fabrication de composants susceptibles de fonctionner dans des conditions extrêmes : forte puissance et haute température. Les travaux de thèse se sont focalisés sur la levée de verrous technologiques pour réaliser des composants latéraux de type JFET (Junction Field Effect Transistor) et les intégrer monolithiquement dans des substrats SiC-4H. L’objectif est de réaliser un bras d’onduleur intégré en SiC avec deux étages commande et puissance. Dans un premier temps, nous avons entamé cette thèse par une caractérisation de deux lots de composants JFET latéraux à canaux N et P réalisés dans le cadre de deux projets ANR précédents cette thèse. De cette étude nous avons extrait plusieurs points positifs, comme celui qui concerne la tenue en tension des JFET de puissance et l’intégration monolithique des JFET basse tension. Mais, nous avons aussi mis en évidence, la nécessité d’optimiser la structure de composants et d’améliorer certaines étapes technologiques, principalement, la définition des canaux par implantation ionique, le contact ohmique et la gravure profonde. Des études approfondies pour réaliser le contact ohmique sur SiC type P et des procédés pour réaliser une gravure profonde dans le SiC ont été développés. Ces études ont permis d’obtenir une faible résistance de contact comparable à l’état de l’art mondial, d’avoir des calibres en courant plus élevés et par conséquent une meilleure modulation. Pour la gravure, un masque dur à base de silicium et nickel (NiSi), nous a permis de mettre en place un procédé original qui permet des gravures profondes du SiC et réaliser les structures intégrés des JFET. L’ensemble de ces améliorations technologiques nous a permis d’obtenir des nouveaux lots de composants JFET P et N intégrés sur la même puce, avec des meilleures performances par rapport aux précédentes réalisations, notamment avec une conduction dans les canaux 10 à 100 fois plus importante. Nous avons également obtenu une modulation du courant Ids en fonction de la tension Vgs sur un nombre très important de JFET en augmentant significativement le rendement par rapport aux lots précédents. / Silicon carbide (SiC) a semiconductor is as wide band gap, notable for its physical properties located between silicon and diamond. The inherent properties of silicon carbide (SiC) high thermal conductivity, and high breakdown voltage make it a very promising material for high power, high temperature and high-frequency device applications. The thesis focused on the removal of technological barriers to achieve lateral components JFET (Junction Field Effect Transistor) and monolithically integrated in SiC-4H substrates. The objective is to realize an arm of inverter integrated there SIC with two floors command and power. Initially, we started this thesis by a characterization of two lots of components JFET with channels N and P realized during two previous ANR this thesis. In this study, we extracted several positive points, such, the breakdown voltage of the JFET power and monolithic integration of low voltage JFET. But we have also highlighted the need to optimize the structure of components and improve some technological steps, mainly the definition channels by ion implantation, the ohmic contact and deep etching. Extensive to achieve ohmic contact on SiC P type and methods for performing deep etching in SiC studies have been developed. These studies have resulted in a low resistance comparable to the state of the art world contact, having sizes in higher current and therefore a better modulation. For etching, a hard mask to silicon and nickel (NiSi) has enabled us to develop a novel method that allows deep etching of SiC JFETs achieve integrated structures. All these technological improvements allowed us to get new batches of P and N JFET integrated on the same chip components with better performance compared to previous achievements, especially with conduction channels 10 to 100 times important. We also got a modulation current Ids as a function of the voltage Vgs on a large number of JFET significantly increasing the performance compared to previous batches.

Designs for deep ultraviolet (DUV) edge emitting laser diodes (LDs) based on the wurtzite III-nitride (III-N) material system are presented. A combination of proprietary and commercial advanced semiconductor LD simulation software is used to study the operation of III-N based DUV LDs theoretically. Critical factors limiting device performance are identified based on an extensive literature survey. A comprehensive design parameter space is investigated thoroughly with the help of advanced scripting capabilities. Several design strategies are proposed to eliminate the critical problems completely or partially. A DUV LD design is proposed based exclusively on AlInN active layers grown epitaxially on bulk AlN substrates because AlInN offers a promising alternative to AlGaN for the realization of LDs and LEDs operating in the DUV regime. The proposed AlInN-based design also features a tapered electron blocking layer (EBL) instead of a homogeneous one. Tapered EBLs redistribute the interfacial polarization charge volumetrically throughout the entire EBL thickness via compositional grading, and eliminate the parasitic inversion layer charge. AlGaN based DUV LD designs are explored also because at present, it may be difficult to grow AlInN epitaxially with superior crystalline quality. Polarization charge matching is proposed to improve electron and hole wavefunction overlap within the active region. Although the strategy of polarization charge matching has already been proposed in the literature to enhance performance of visible wavelength LEDs and LDs, the proposed design presents the first demonstration that polarization charge matching is also feasible for DUV LDs operating at sub-300 nm wavelengths. A lateral current injection (LCI) LD design is proposed featuring polarization-charge-matched barriers and regrown Ohmic contacts to avoid a group of issues related to the highly inefficient p-type doping of wide bandgap III-N materials in vertical injection designs. The proposed design partially decouples the problem of electrical injection from that of optical confinement. Although the idea of an LCI LD design has been proposed in the literature in the 90s to be used as longer wavelength active sources in optoelectronic integrated circuits using GaInAsP/InP and related material systems, the proposed design is the first theoretical demonstration that this concept can be applied to DUV LDs based on III-N material system. To solve the problem of hole transport in vertical injection designs, a DUV LD design based exclusively on AlGaN material system is presented, featuring an inverse-tapered p-waveguide layer instead of an EBL. Several EBL designs are investigated, and compared with conventionally-tapered EBL design. Through judicious volumetric redistribution of fixed negative polarization charge, inverse tapering may be exploited to achieve nearly flat valence band profiles free from barriers to hole injection into the active region, in contrast to conventional designs. Numerical simulations demonstrate that the inverse tapered strategy is a viable solution for efficient hole injection in vertical injection DUV LDs operating at shorter wavelengths (< 290 nm).

The task of the thesis was studding of tantalum capacitors with solid electrolytes properties. Ta – Ta2O5 – MnO2 capacitor by its construction represents MIS structure, where tantalum anode has metal conductivity and MnO2 cathode is semiconductor. Isolation layer consists of tantalum pentoxide Ta2O5 with relative permitivity r = 27. Dielectric thickness is typically in range from 30 to 150nm. The capacitor charge is not only stored and accumulated on electrodes but also in localised states (oxide vacancies) in isolation layer. The capacitor connected in normal mode represents MIS structure polarized in reveres direction when the applied voltage higher potential barrier between semiconductor - MnO2 cathode and isolation of Ta2O5. The transport of charge carriers via isolation layer is determined by Poole-Frenkel mechanisms and tunnelling. Poole-Frenkel mechanism of charge transport is dominant in low intensity of electric field. Tunnelling determines current at higher electric field intensity. During low intensity of electric field ohmic component is also presented which is determined by volume of resistance of impurities in isolation layer due to donor states of oxygen vacancies. Based on the modelling of measured VA characteristics is possible to estimate determine dielectric thickness of Ta2O5 and determine share of Poole-Frenkelov and tunnel current and charge transportation. The thesis is described charge transport and charge concentration on tantalum capacitor in low frequency area and analysis of capacitor behaviour at frequency band. The first impulse for the thesis was an effort to create equivalent circuit diagram of tantalum capacitor in respect of its physical and electrical behaviour. There is an opportunity to study and determine electric charge transport and its accumulation based on the equivalent circuit diagram structure. There is also a chance to define and trace potential barriers and charge distribution in the capacitor structure based on an measurement and carried out experiments. This methodology and analysis consists of electrical characteristic determination to create physical model of the capacitor describing it function, properties and behaviour.

Un modèle de commutation de mémoires résistives (ReRAM) est présenté. Celui-ci est basé sur deux hypothèses : (1) la commutation résistive est causée par des changements qui se produisent dans la zone étroite (région active) du filament conducteur sous l'influence du champ électrique et (2) la commutation résistive est un processus stochastique, donc régi par une probabilité. La région active est représentée par un réseau de connexions verticales, chacune composée de trois éléments électriques : deux d'entre eux sont de faible résistance tandis que le troisième agit comme un disjoncteur et peut être soit de résistance faible (LR) ou élevée (HR). Dans ce modèle, le changement d'état du disjoncteur est régi par une probabilité de commutation (P$_{s}$) qui est comparée à un nombre aléatoire « p ». P$_{s}$ dépend de la chute de tension le long du disjoncteur et de la tension de seuil, V$_{set}$ ou V$_{reset}$, pour définir les processus de « set » (HR à LR) et « reset » (LR à HR). Deux mécanismes de conduction ont été envisagés : ohmique pour un état LR et pour un état de résistance élevée l'effet tunnel facilité par un piège (TAT). Le modèle a été implémenté avec le langage de programmation Python et fonctionne avec une bibliothèque C externe qui optimise les calculs et le temps de traitement. Les résultats de la simulation ont été validés avec succès en les comparant avec des courbes courant-tension (IV) mesurées sur dispositifs ReRAM réels dont l'oxyde était fait de HfO$_{2}$ et pour neuf aires différentes. La flexibilité et la facilité de mise en œuvre de ce modèle de commutation résistive en font un outil puissant pour l'étude des ReRAM / A model for the switching of resistive random-access memories (ReRAM) is presented. This model is based on two hypotheses: (1) the resistive switching is caused by changes that occur in the narrow zone (active region) of the conductive filament under the influence of the electric field and (2) the resistive switching is a stochastic process governed by a switching probability. The active region is represented by a net of vertical connections, each one composed of three electrical elements: two of them are always low resistive (LR) while the third one acts as a breaker and can be low or high resistive (HR). In the model, the change of the breaker's state is governed by a switching probability (P$_{s}$) that is compared with a random number $p$. P$_{s}$ depend on the voltage drop along the breaker and the threshold voltage, V$_{set}$ or V$_{reset}$ for set (HR to LR) or reset (LR to HR) processes. Two conduction mechanism has been proposed: ohmic for the low resistive state and trap-assisted tunneling (TAT) for the high resistive state. The model has been implemented in Python and works with an external C-library that optimizes calculations and processing time. The simulation results have been successfully validated by comparing measured and modeled IV curves of HfO$_{2}$-based ReRAM devices of nine different areas. It is important to note that the flexibility and easy implementation of this resistive switching model allow it to be a powerful tool for the design and study of ReRAM memories

Ohmic contacts are crucial components in semiconductor devices such as transistors and diodes, and lowering their contact resistance is an important factor in device performance enhancement. This is especially important for low-noise amplifiers (LNAs) where device noise temperature decreases both directly and indirectly with decreasing contact resistance. This becomes relevant in quantum computers operated at cryogenic temperatures as LNAs constitutes the 4 K quantum bit (qubit) readout signal amplification chain. The goal of this project is to investigated the superconducting element niobium (Nb) as contact material for indium phosphide (InP) high-electron-mobility transistors (HEMTs), being the active component in cryogenic high-frequency LNAs. For contact and barrier resistance determination, test structures were fabricated and utilized according to the transfer length method(TLM) and the recess TLM respectively. Measurements were performed in room temperature as well as in cryogenic temperatures below and above Nb’s bulk transition temperature of 9.25 K. The results show low-resistance Nb-based ohmic contacts for n-In0.65Ga0.35As, with the non-alloyed Nb(50 nm)/Au(100 nm) stack yielding a room temperature contact resistivity of (9.4 ± 0.5) × 10−8 Ωcm2. For all contacts the contact resistivity increased moving to cryogenic temperatures, as expected when electron occupation of high-energy states decreases. At cryogenic temperatures nosuperconducting transition was observed, attributed to the Nb layer thickness being roughly equal to its coherence length. Considering the effective barrier resistance, the Ni/Ge/Au/Nb/Au alloyed contact had the lowest room temperature resistance, reporting 143 Ω µm. In cryogenic temperatures the effective barrier resistance unexpectedly decreased in all contacts. The Nb/Au contact showed the best cryogenic performance, with a barrier resistance of 28 − 37 Ω µm. This indicates great potential for non-alloyed Nb/Au contacts in cryogenic InP HEMTs. / Alla halvledarkomponenter, som dioder och transistorer, har ohmska kontakter. Att sänka kontaktresistansen hos de ohmska kontakterna är ett sätt att höja prestandan hos en komponent. Särskilt gäller detta för lågbrusförstärkare, som har en brustemperatur som minskar både direkt och indirekt med avtagande kontaktresistans. För kvantdatorer som måste kylas till kryogena temperaturer för att fungera är detta relevant eftersom förstärkningen av utläsningssignalen från kvantbitar sker via lågbrusförstärkare vid 4 K. Målet för detta examensprojekt är att undersöka ohmska kontakter baserade på det supraledande materialet niobium (Nb) i indiumfosfidbaserade högelektronmobilitetstransistorer, som är den aktivakomponenten i kryogena högfrekvens-lågbrusförstärkare. För bestämning av kontaktoch barriärresistans producerades teststrukturer enligt Transfer Length-metoden (TLM) respektive etsad TLM. Mätningar genomfördes i rumstemperatur samt vid kryogena temperaturer både över och under niobiumets kritiska temperatur på 9.25 K. Resultatet visar låg kontaktresistans för Nb-baserade ohmska kontakter på n-In0.65Ga0.35As. Den icke-legerade Nb(50 nm)/Au(100 nm)-kontakten hade en kontaktresistivitet på (9.4 ± 0.5) × 10−8 Ωcm2 . Vid kryogena temperaturer ökade kontaktresistansen för samtliga Nb-baserade kontakter, vilket är förväntat då färre elektroner fyller högenergitillstånd. Inget supraledande tillstånd observerades vid kryogena temperaturer, vilket kan förklaras av att tjockleken på niobiumlagret var ungefär lika med dess koherenslängd. Lägst barriärresistans vid rumstemperatur hade den legerade Ni/Ge/Au/Nb/Au-kontakten, med ett värde på 143 Ω µm. Vid kryogena temperaturer skedde en oväntad minskning hos barriärsresistansen hos samtliga kontakter, där den lägst barriärsresistans uppmättes på den icke-legerade Nb/Au-kontakten, 28 − 37 Ω µm. Slutsatsen som dras är att det finns stor potential för användning av icke-legerade Nb/Au-kontakter för kryogena lågbrusförstärkare baserade på indiumfosfid.