User-programmable, integrated circuits (ICs) e.g. Field Programmable Gate Arrays (FPGAs) are increasingly popular for embedded, high-performance data exploitation. They combine the parallelization capability and processing power of application specific integrated circuits (ASICs) with the exibility, scalability and adaptability of software-based processing solutions. FPGAs provide powerful processing resources due to an optimal adaptation to the target application and a well-balanced ratio of performance, efficiency and parallelization. One drawback of FPGA-based data exploitation is the limited memory capacity of reconfigurable integrated circuits. Large-scale Digital Signal Processor (DSP) FPGAs provide approximately 4MB on-board random access memory (RAM) which is not sufficient to buffer the broadband sensor and result data. Hence, additional external memory is connected to the FPGA to increase on-board storage capacities. External memory devices like double data rate three synchronous dynamic random access memories (DDR3-SDRAM) provide very fast and wide bandwidth interfaces that represent a bottleneck when used in highly parallelized processing architectures. Independent processing modules are demanding concurrent read and write access. Within the master thesis, a concept for the integration of an external DDR3- SDRAM into an FPGA-based parallelized processing architecture is developed and implemented. The solution realizes time division multiple access (TDMA) to the external memory and virtual, low-latency memory extension to the on-board buffer capabilities. The integration of the external RAM does not change the way how on-board buffers are used (control, data-fow).

Reconfigurable hardware architectures have been available now for several years. Yet the application development for such architectures is still a challenging and error-prone task, since the methods, languages, and tools being used for development are inappropriate to handle the complexity of the problem. This thesis introduces a novel approach that tackles the complexity challenge by raising the level of abstraction to system-level and increasing the degree of automation. The approach is centered around the paradigms of object-orientation, platforms, and modeling. An application and all platforms being used for its design, implementation, and deployment are modeled with objects using UML and an action language. The application model is then transformed into an implementation, whereby the transformation is steered by the platform models. In this thesis solutions for the relevant problems behind this approach are discussed. It is shown how UML can be used for complete and precise modeling of applications and platforms. Application development is done at the system-level using a set of well-defined, orthogonal platform models. Thereby the core features of object-orientation - data abstraction, encapsulation, inheritance, and polymorphism - are fully supported. Novel algorithms are presented, that allow for an automatic mapping of such application models to the target architecture. Thereby the problems of platform mapping, estimation of implementation characteristics, and synthesis of UML models are discussed. The thesis explores the utilization of platform models for generation of highly optimized implementations in an automatic yet adaptable way. The approach is evaluated by a number of relevant applications. The execution of the generated implementations is supported by a run-time service. This service manages the hardware configurations and objects comprising the application. Moreover, it serves as broker for hardware objects. The efficient management of configurations and objects at run-time is discussed and optimized life cycles for these entities are proposed. Mechanisms are presented that make the approach portable among different physical hardware architectures. Further, this thesis presents UML profiles and example platforms that support system-level design. These extensions are embodied in a novel type of model compiler. The compiler is accompanied by an implementation of the run-time service. Both have been used to evaluate and improve the presented concepts and algorithms.

No description available.

A fault injection tool has been created to emulate single event upset (SEU) behavior within the configuration memory of an FPGA. This tool is able to rapidly and accurately determine the dynamic sensitive cross section of the configuration memory for a given FPGA design. This tool enables the reliability of FPGA designs and fault tolerance schemes to be quickly and accurately tested. The validity of testing performed with this fault injection tool has been confirmed through radiation testing. A radiation test was conducted at Crocker Nuclear Laboratory using a proton accelerator in order to determine the actual dynamic sensitive cross section for specific FPGA designs. The results of this radiation testing were then analyzed and compared with similar fault injection tests, with results suggesting that the fault injection tool behavior is indeed accurate and valid. The fault injection tool can be used to determine the sensitivity of an FPGA design to configuration memory upsets. Additionally, fault mitigation techniques designed to increase the reliability of an FPGA design in spite of upsets within the configuration memory, can be thoroughly tested through fault injection. Fault injection testing should help to increase the feasibility of reconfigurable computing in space. FPGAs are well suited to the computational demands of space based signal processing applications; however, without appropriate mitigation or redundancy techniques, FPGAs are unreliable in a radiation environment. Because the fault injection tool has been shown to reliably model the effects of single event upsets within the configuration memory, it can be used to accurately evaluate the effectiveness of fault tolerance techniques in FPGAs.

Multiple Sequence Alignment (MSA) is a fundamental analysis method used in bioinformatics and many comparative genomic applications. The time to compute an optimal MSA grows exponentially with respect to the number of sequences. Consequently, producing timely results on large problems requires more efficient algorithms and the use of parallel computing resources. Reconfigurable computing hardware provides one approach to the acceleration of biological sequence alignment. Other acceleration methods typically encounter scaling problems that arise from the overhead of inter-process communication and from the lack of parallelism. Reconfigurable computing allows a greater scale of parallelism with many custom processing elements that have a low-overhead interconnect. The proposed parallel algorithms and architecture accelerate the most computationally demanding portions of MSA. An overall speedup of up to 150 has been demonstrated on a large data set when compared to a single processor. The reduced runtime for MSA allows researchers to solve the larger problems that confront biologists today.

Due to advances in digital computing much of the baseband signal processing of a communication system has moved into the digital domain from the analog domain. Within the domain of digital communication systems, Software Defined Radios (SDRs) allow for majority of the signal processing tasks to be implemented in reconfigurable digital hardware. However this comes at a cost of higher power and resource requirements. Therefore, highly efficient custom hardware implementations for SDRs are needed to make SDRs feasible for practical use. Efficient custom hardware motivates the use of fixed point arithmetic in the implementation of Digital Signal Processing (DSP) algorithms. This conversion to finite precision arithmetic introduces quantization noise in the system, which significantly affects the performance metrics of the system. As a result, characterizing quantization noise and its effects within a DSP system is an important challenge that needs to be addressed. Current models to do so significantly over-estimate the quantization effects, resulting in an over-allocation of hardware resources to implement a system. Polynomial Chaos Expansion (PCE) is a method that is currently gaining attention in modelling uncertainty in engineering systems. Although it has been used to analyze quantization effects in DSP systems, previous investigations have been limited to simple examples. The purpose of this thesis is to therefore introduce new techniques that allow the application of PCE to be scaled up to larger DSP blocks with many noise sources. Additionally, the thesis introduces design space exploration algorithms that leverage the accuracy of PCE simulations to estimate bitwidths for fixed point implementations of DSP systems. The advantages of using PCE over current modelling techniques will be presented though its application to case studies relevant to practice. These case studies include Sine Generators, Infinite Impulse Response (IIR) filters, Finite Impulse Response (FIR) filters, FM demodulators and Phase Locked Loops (PLLs). / Thesis / Master of Applied Science (MASc)

No description available.

No description available.

The Frequency Disturbance Recorder (FDR) is a specialized data acquisition device designed to monitor fluctuations in the overall power system. The device is designed such that it can be attached by way of a standard wall power outlet to the power system. These devices then transmit their calculated frequency data through the public internet to a centralized data management and storage server. By distributing a number of these identical systems throughout the three major North American power systems, Virginia Tech has created a Frequency Monitoring Network (FNET). The FNET is composed of these distributed FDRs as well as an Information Management Server (IMS). Since frequency information can be used in many areas of power system analysis, operation and control, there are a great number of end uses for the information provided by the FNET system. The data provides researchers and other users with the information to make frequency analyses and comparisons for the overall power system. Prior to the end of 2004, the FNET system was made a reality, and a number of FDRs were placed strategically throughout the United States. The purpose of this thesis is to present the elements of a new generation of FDR hardware design. These elements will enable the design to be more flexible and to lower reliance on some vendor specific components. Additionally, these enhancements will offload most of the computational processing required of the system to a commodity PC rather than an embedded system solution that is costly in both development time and financial cost. These goals will be accomplished by using a Field Programmable Gate Array (FPGA), a commodity off-the-shelf personal computer, and a new overall system design. / Master of Science

In modern communication systems, it’s important to detect and use available radio frequencies effectively. However, current methods face challenges with complexity and noise interference. We’ve developed a new approach using advanced artificial intelligence (AI) based computing techniques to improve efficiency and accuracy in this process. Our method shows promising results, requiring only minimal additional resources in exchange of improved performance compared to older techniques. / Master of Science / In modern communication systems, it’s important to detect and use available radio frequencies effectively. However, current methods face challenges with complexity and noise interference. We’ve developed a new approach using advanced artificial intelligence (AI) based computing techniques to improve efficiency and accuracy in this process. Our method shows promising results, requiring only minimal additional resources in exchange of improved performance compared to older techniques.