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Indiana University-Purdue University Indianapolis (IUPUI) / One of the critical steps in a current Western blot technique is a blotting process, which in general requires one electrophoretic gel for every protein species to be analyzed. In most cases, multiple protein species are analyzed simultaneously and thus it is necessary for a scientist to run multiple gels. In order to make it possible to analyze multiple protein species from a single gel, a novel blotting device, BlotMan, was employed in this study. Designed by Dr. Chien’s group (YC Bioelectric), BlotMan uses pulse width modulation (PWM) for applying a protein size-dependent voltage during a blotting process. In this study, the differential average voltage profile, depending on protein size (e.g. 17 kDa to 140 kDa), was built and enabled BlotMan to transfer all protein species in equal efficiency regardless of the protein size. Furthermore, Blot- Man consists of a user-friendly, custom-made interface box, which can be remotely controlled by a smart phone. BlotMan’s capability was evaluated using standard protein markers, as well as protein samples that were isolated from chondrosarcoma cells (SW1353) and breast cancer cells (MDA-MB-213). The experimental results revealed that BlotMan was capable of generating 5 blotting membranes from a single gel simultaneously. Protein species such as c-Src, eukaryotic translation initiation factor 2 alpha (eIF2α) and its phosphorylated form (p-eIF2α), lamin B, and β-actin were successfully detected. It is also demonstrated that compared to a regular constant voltage, PWM signals improved transfer efficiency and a signal-to-noise ratio. In conclusion, this study demonstrated that BlotMan was able to facilitate Western blotting analysis by generating multiple blotting membranes from a single gel with an improved signal-to-noise ratio. Further analysis is recommended for understanding the mechanism of PWMts action on transfer efficiency and noise reduction.

Three-phase voltage source inverters are increasingly employed in power systems and industrial applications. Various pulse width modulation strategies have been applied to control the voltage source inverters. This dissertation presents a hybrid 2D-3D space vector modulation algorithm for three-phase voltage source inverters with both three-wire and four-wire topologies. The voltage magnitude and phase angle of the inverters fundamental output phase voltage are precisely controlled under either balanced or unbalanced load conditions, and hence, the space vector algorithm offers synchronization controllability over generation control in distributed generation systems. The numerical efficiency and simplicity of the proposed algorithm are validated through conducting MATLAB/Simulink simulations and hardware experiments. Mathematical description and harmonic analyses of output phase voltages of three-phase voltage source inverter which employs a hybrid 2D-3D SVM are presented in this dissertation. Explicit time domain representation of the harmonic components in addition to the total harmonic distortion of the output phase voltages are given in terms of system and switching parameters. The dissertation also investigates the harmonic characteristics and low total harmonic distortion performance against the linearity of modulation region which helps in the harmonic performance and design studies of such inverters employing the hybrid 2D-3D SVM. Experimental results are used to validate these analyses. In addition, the performance and the harmonic contents of the inverter output phase voltage when applying the proposed hybrid 2D-3D SVM are compared to that obtained from conventional 2D SVM and 3D SVM. As a result, the proposed new algorithm shows advantages in terms of low total harmonic distortion and reduced harmonic contents in both three-wire and four-wire systems.

In this episode, we show how a binary signal can be used to give the appearance of an analog output. We then use this understanding to show how to dim an LED on the Arduino open source platform.

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Three novel single-stage electronic ballasts with the advantages of high-power-factor, low current harmonic, high efficiency, and low cost are proposed for rapid-start fluorescent lamps. Included are (1) single-stage high-power-factor electronic ballast with asymmetrical topology, (2) single-stage high- power-factor electronic ballast with symmetrical topology, and (3) single-stage single-switch high-power-factor electronic ballast. The circuit configurations are obtained by integrating the buck-boost power-factor-correction converter into the Class D or the Class E resonant inverter. With simple circuit configuration and less component count, desired circuit performances of high-power-factor and high efficiency are realized. The control methods of pulse-width-modulation (PWM) with asymmetrical and symmetrical approaches are utilized for the three presented ballasts. The buck-boost conversion stage is operated at discontinuous current mode (DCM) to achieve nearly unity power factor at a fixed switching frequency. With carefully designed circuit parameters, the power switches can exhibit either zero-voltage switching-on (ZVS) or zero-current switching-on (ZCS). As a result, high circuit efficiency can be ensured. Design equations are derived and computer analyses are performed based on the lamp¡¦s equivalent resistance model and fundamental approximation. Accordingly, design guidelines for determining circuit parameters are provided. Prototypes of the three proposed circuits designed for a T8-36W lamp, two series-connected T9-40W lamps and a PL-27W lamp are built and tested to verify the computer simulations and analytical predictions.

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Voltage source inverters (VSI) are popular in variable speed induction motor drive applications. Pulse width modulation (PWM) is employed to achieve variable voltage variable frequency output from a fixed DC bus voltage. The modulation method greatly influences the harmonic distortion in line current and the inverter switching loss. This thesis evaluates a few space vectorbased PWM techniques which reduce the harmonic distortion and/or the inverter switching loss, compared to conventional space vector PWM (CSVPWM), at a given average switching frequency. In space vector-based PWM, the average voltage vector applied over a sub-cycle equals the commanded reference vector, thereby maintaining voltsecond balance. The given average vector can be realized by applying the voltage vectors of the inverter in different sequences. CSVPWM employs a switching sequence in which all the phases switch once in a sub-cycle. Sequences, in which a phase is clamped, while the other two phases switch once in a sub-cycle have been reported in literature. Further, certain special switching sequences have also been reported recently. These special sequences involve switching a phase twice, while switching the second phase once and clamping the third phase in a sub-cycle. This work investigates the use of such special switching sequences to reduce line current distortion and inverter switching loss in an induction motor drive. The influence of various switching sequences on line current ripple and inverter switching loss is discussed in the thesis. Comparison of the sequences in terms of switching loss leads to a hybrid PWM technique, which deploys the best sequence to reduce switching loss under a given operating condition. This technique is referred to as minimum switching loss PWM (MSLPWM). Further, a procedure for design of hybrid PWM techniques to achieve reduced line current distortion as well as inverter switching loss is elaborated. Four such specially designed hybrid PWM techniques are discussed. Analytical methods are presented for the evaluation of total RMS harmonic distortion factor of line current and inverter switching loss corresponding to different PWM techniques. The MSLPWM and the hybrid PWM techniques are evaluated analytically in terms of harmonic distortion and switching loss. It is observed that the switching loss corresponding to MSLPWM is considerably less than that with CSVPWM over the entire range of power factor. The reduction in switching loss with MSLPWM is as high as 36% at high power factors close to unity, while it is not less than 22% at power factors close to zero. MSLPWM also reduces the harmonic distortion for power factors close to unity at high modulation indices. Compared to CSVPWM, the hybrid PWM techniques result in a maximum reduction of about 40% in the harmonic distortion at fundamental frequencies close to 50Hz, and about 30% reduction in switching loss at power factors close to unity. The various PWM techniques are tested on a constant V /f induction motor drive with a digital control platform based on ALTERA Cyclone II field programmable gate array (FPGA) device. With a 10kVA IGBT based inverter feeding a 2.2kW, 415V, 50Hz, three-phase induction motor, the total RMS harmonic distortion factor of line current (IT HD) is measured at different fundamental frequencies for the various PWM techniques. The average switching frequency is 2.44kHz. The measured values of IT HD show a reduction in distortion with the hybrid PWM techniques over CSVPWM at high speeds of the drive. The relative values of IT HD corresponding to different PWM techniques agree with the theoretical predictions. With the 10kVA IGBT based inverter feeding a 6kW, 400V, 50Hz, 4pole, three-phase induction motor, the switching losses corresponding to CSVPWM and MSLPWM are evaluated and compared. This is done by measuring the steady state temperature rise of the heat sink over the ambient for the two techniques under different conditions. The thermal measurements are carried out at different loads with power factor ranging from 0.14 to 0.77. The measurements are also carried out at different fundamental frequencies (or modulation indices). Further, to separate conduction (constant) losses and switching (variable) losses, the heat sink temperatures are measured at two different switching frequencies, namely 2.44kHz and 4.88kHz. It is observed that the temperature rise due to MSLPWM is less than that due to CSVPWM consistently under various operating conditions. The thermal measurements confirm the theoretical prediction of reduction in switching loss with MSLPWM. Measurements of heat sink temperature rise corresponding to CSVPWM, MSLPWM and the hybrid PWM techniques are carried out at a higher power factor of 0.98 (lag) with the inverter feeding an RL load (instead of an induction motor). The hybrid PWM and MSLPWM result in lower switching losses as indicated by the reduction in temperature rise.

A voltage source inverter is commonly used to supply a variable frequency variable voltage to a three phase induction motor in a variable speed application. A suitable pulse width modulation (PWM) technique is employed to obtain the required output voltage in the line side of the inverter. Real-time methods for PWM generation can be broadly classified into triangle comparison based PWM (TCPWM) and space vector based PWM (SVPWM). In TCPWM methods such as sine-triangle PWM, three phase reference modulating signals are compared against a common triangular carrier to generate the PWM signals for the three phases. In SVPWM methods, a revolving reference voltage vector is provided as voltage reference instead of three phase modulating waves. The magnitude and frequency of the fundamental component in the line side are controlled by the magnitude and frequency, respectively, of the reference vector. The fundamental line side voltage is proportional to the reference magnitude during linear modulation. With sine-triangle PWM, the highest possible peak phase fundamental voltage is 0.5Vdc, where Vdc is the DC bus voltage, in the linear modulation zone. With techniques such as third harmonic injection PWM and space vector based PWM, the peak phase fundamental voltage can be as high as (formula) (i.e., 0:577Vdc)during linear modulation. To increase the line side voltage further, the operation of the VSI must be extended into the overmodulation region. The overmodulation region extends upto the six-step mode, which gives the highest possible ac voltage for a given (formula). In TCPWM based methods, increasing the reference magnitude beyond a certain level leads to pulse dropping, and gradually leads to six-step operation. However, in SVPWM methods, an overmodulation algorithm is required for controlling the line-side voltage during overmodulation and to achieve a smooth transition from PWM to six-step mode. Numerous overmodulation algorithms have been proposed in the literature for space vector modulated inverter. A well known algorithm among these divides the overmodulation zone into two zones, namely zone-I and zone-II. This is termed as the 'existing overmodulation algorithm' here. This algorithm is modified in the present work to reduce computational burden without much increase in the line current distortion. During overmodulation, the fundamental line side voltage and the reference magnitude are not proportional, which is undesirable from the control point of view. The present work ensures a linear relationship between the two. Apart from the fundamental component, the inverter output voltage mainly consists of harmonic components at high frequencies (around switching frequency and the integral multiples) during linear modulation. However, during overmodulation, low order harmonic components such as 5th, 7th, 11th, 13th etc., are also present in the output voltage. These low order harmonic voltages lead to low order harmonic currents in the motor. The sum of the lower order harmonic currents is termed as 'lower order current ripple'. The present thesis proposes a method for estimation of lower order current ripple in real-time. In closed loop current control, the motor current is fed back to the current controller. During overmodulation, the motor current contains low order harmonics, which appear in the current error fed to the controller. These harmonic currents are amplified by the current error amplifier deteriorating the performance of the drive. It is possible to filter the lower order harmonic currents before being fed back. However, filtering introduces delay in the current loop, and reduces the bandwidth even during linear modulation. In the present work, the estimated lower order current ripple is subtracted from the measured current before the latter is fed back to the controller. The estimation of lower order current ripple and the proposed current control are verified through simulation using MATLAB/SIMULINK and also experimentally on a laboratory prototype. The experimental setup comprises of a field programmable gate arrays (FPGA) based digital controller, an IGBT based inverter and a four-pole squirrel cage induction motor. (Pl refer the original document for formula)

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