<p>This report briefly describes the special requirements for a computer board for use in space. In particular, component selection and ways of mitigating the soft and hard errors are discussed. Furthermore, one implementation for a low-cost, relatively high performance computer that will work in the harsh space environment is presented. The report is primarily intended for those familiar with digital design, who need an introduction to construction of space or other high-reliability hardware. </p><p>As the quality (resolution) of imagers, spectrometers and other data sources in scientific satellite payloads is increasing, there is also an increasing demand for more processing power in order to compress or in other way process the data before transmitting it on the limited bandwidth microwave downlink to Earth. Scientific instruments are usually mission specific and have rather low budget, so there is a need for a powerful computer board that can be used for a number of missions in order to keep the engineering costs down.</p>

The heaviest fragments, recoils, have been studied in proton and deuteron induced 28Si reactions and proton-20Ne reactions at 100-300 MeV per nucleon. Inclusive charge and angular distributions and coincidences between He nuclei and recoils have been compared to two theoretical models, Dubna Cascade Model and JAERI Quantum Molecular Dynamics. The overall agreement was good for the reactions with 28Si, however the angular distributions of He fragments could not be reproduced. For the 20Ne reactions the recoil angular distributions were only reproduced for large angles. There was a significant underestimation at small angles and low recoil charge. α-clustering in the bombarding nucleus is a possible explanation for the deviations. In the 100 MeV per nucleon reactions all assumptions of the models may not be valid and the agreement was worst for these reactions. In proton-natXe reactions intermediate mass fragments have been studied from 200 to 1400 MeV. Slow ramping was used to scan the energy. Charge distributions and a caloric curve have been compared to Cascade Fragmentation Evaporation Model. Charge distributions showed good agreement for fragments with Z&lt;8 but the heavier fragments were underestimated.

Space radiation is significantly harmful to electronic Components. The operating time, duration and orbit of the space mission are affected by the characteristic of the radiation environment. The aging and the performance of the electronic components are modified by radiation. The performance of the space systems such as electronic units, sensors, power and power subsystem units, batteries, payload equipments, communication units, remote sensing instruments, data handling units, externally located units, and propulsion subsystem units is determined by the properly functioning of various electronic systems. Such systems are highly sensitive against space radiation. The space radiation can cause damage to electronic components or functional failure on the electronics. A precisely methodology is needed to ensure that space radiation is not a threat on the functionality and performance of the electronics during their operational lives. This methodology is called as &rdquo / Radiation Hardness Assurance&rdquo / . In this thesis, the hardening of electronics against space radiation is discussed. This thesis describes the space radiation environments, physical mechanisms, effects of space radiation, models of the space radiation environment, simulation of the Total Ionizing Dose, and &rdquo / Radiation Hardness Assurance&rdquo / which covers Total Ionizing Dose and Single Event Effects testing and analyzing of the electronics.

This work investigates the challenges associated with designing silicon-germanium (SiGe) analog and mixed-signal circuits capable of operating reliably in extreme environment conditions. Three extreme environment operational conditions, namely, operation over an extremely wide temperature range, operation at extremely low temperatures, and operation under radiation exposure, are considered. As a representative for critical analog building blocks, bandgap voltage reference (BGR) circuit is chosen. Several architectures of the BGRs are implemented in two SiGe BiCMOS technology platforms. The effects of wide-temperature operation, deep cryogenic operation, and proton and x-ray irradiation on the performance of BGRs are investigated. The impact of Ge profile shape on BGR's wide-temperature performance is also addressed. Single-event transient response of the BGR circuit is studied through microbeam experiments. In addition, proton radiation response of high-voltage transistors, implemented in a low-voltage SiGe platform, is investigated. A platform consisting of a high-speed comparator, digital-to-analog (DAC) converter, and a high-speed flash analog-to-digital (ADC) converter is designed to facilitate the evaluation of the extreme environment capabilities of SiGe data converters. Room temperature measurement results are presented and predictions on how temperature and radiation will impact their key electrical properties are provided.

La miniaturisation des gravures des transistors résulte en une augmentation de la sensibilité aux soft-erreurs des circuits intégrés face aux particules énergétiques présentes dans l'environnement dans lequel ils opèrent. Une expérimentation, présentée au cours de cette thèse, concernant l'étude de la sensibilité face aux soft-erreurs, dans l'environnement réel, des mémoires SRAM provenant de deux générations de technologies successives, a mis en évidence la criticité de cette thématique. Cela pour montrer la nécessité de l'évaluation des circuits faces aux effets des radiations, surtout les circuits commerciaux qui sont de plus en plus utilisés dans les applications spatiales et avioniques et même dans les hautes altitudes, afin de trouver les méthodologies permettant leurs durcissements. Plusieurs méthodes d'injection de fautes, ayant pour but l'évaluation de la sensibilité des circuits intégrés face aux soft-erreurs, ont été le sujet de plusieurs recherches. Les travaux réalisés au cours de cette thèse ont eu pour but le développement d'une méthode automatisable, avec son outil, permettant l'émulation des effets des radiations sur des circuits dont on dispose de leurs codes HDL. Cette méthode, appelée NETFI (NETlist Fault Injection), est basée sur la manipulation de la netlist du circuit synthétisé pour permettre l'injection de fautes de types SEU, SET et Stuck_at. NETFI a été appliquée sur plusieurs architectures pour étudier ses potentialités ainsi que son efficacité. Une étude sur un algorithme tolérant aux fautes, dit self-convergent, exécuté par un processeur LEON3, a été aussi présenté dans le but d'effectuer une comparaison des résultats issus de NETFI avec ceux issus d'une méthode de l'état de l'art appelée CEU (Code Emulated Upset).

Ce travail présente la mise en œuvre du test par faisceau laser TPA pour l'étude de la sensibilité au phénomène SEB dans les diodes schottky en carbure de silicium. Le contexte de l'étude est décrit par un état de l'art du SEB sur les MOSFETs et Diodes en Silicium et en carbure de silicium. Une étude technologique et structurelle des composants en SiC a permis de dégager les avantages du SiC par rapport au Si conventionnel et a permis d'analyser les dégâts causés par le faisceau TPA. L'utilisation du montage expérimental sur la plateforme ATLAS dédié spécifiquement au test de matériaux à grand gap a permis de mettre en place une méthodologie de test sur des diodes schottky en SiC. L'efficacité de cette méthodologie est prouvée par l'obtention de résultats expérimentaux très originaux. La susceptibilité au SEB induit par la technique laser TPA a été démontrée. Les mesures SOA ont permis d'évaluer la robustesse des diodes schottky SiC face aux événements singuliers. Une modélisation analytique a été menée afin de comprendre la cause du mécanisme du SEB et la localisation des défauts induits par le faisceau TPA.

Silicon-germanium (SiGe) BiCMOS technology platforms have proven invaluable for implementing a wide variety of digital, RF, and mixed-signal applications in extreme environments such as space, where maintaining high levels of performance in the presence of low temperatures and background radiation is paramount. This work will focus on the investigation of the total-dose radiation tolerance of a third generation complementary SiGe:C BiCMOS technology platform. Tolerance will be quantified under proton and X-ray radiation sources for both the npn and pnp HBT, as well as for an operational amplifier built with these devices. Furthermore, a technique known as junction isolation radiation hardening will be proposed and tested with the goal of improving the SEE sensitivity of the npn in this platform by reducing the charge collected by the subcollector in the event of a direct ion strike. To the author's knowledge, this work presents the first design and measurement results for this form of RHBD.

L'environnement spatial constitue une contrainte radiative susceptible d'altérer le bon fonctionnement des dispositifs électroniques embarqués à bord des engins spatiaux, engendrant ainsi des défaillances. Dans le cadre de ces travaux, deux types de dysfonctionnements sont répertoriés : les effets cumulatifs dus à une accumulation continue d'énergie déposée tout au long d'une mission et les effets transitoires dus au passage d'une particule unique dans une zone sensible d'un composant ou à un dépôt d'énergie en un temps très court dans le cadre spécifique d'une explosion nucléaire exoatmosphérique. Lors des procédures de qualification des composants électroniques, ces deux effets sont traités séparément et ce, malgré une probabilité non négligeable qu'ils se produisent simultanément en vol. Ces travaux sont dédiés à l'étude de la synergie entre effets cumulatifs et effets transitoires sur différentes technologies bipolaires intégrées. Les résultats obtenus permettent de fournir des éléments de réponse sur l'éventualité d'une évolution des normes de test pour prendre en compte la menace que pourrait représenter ce phénomène. Ces travaux s'attachent également à étendre une méthodologie de simulation, basée sur une analyse circuit approfondie, dans l'optique de reproduire les perturbations transitoires « pire-cas » sur un amplificateur opérationnel à trois étages de plusieurs fabricants, survenues lors des tests sous faisceau laser, ions lourds et flash X. L'influence des effets cumulatifs sur la sensibilité des perturbations transitoires est prise en compte en faisant varier les paramètres internes du modèle en fonction de la dégradation de certains paramètres électriques issue des essais radiatifs des équipementiers. / The space environment is a radiative concern that affects on board electronic systems, leading to failures. It is possible to distinguish two types of effects: the cumulative effects due to continuous deposition of energy throughout the space mission and the transient effects due to the single energetic particle crossing a sensitive area of the component or deposition of energy in a very short time in the specific context of an exo-atmospheric nuclear explosion. During qualification procedures for space mission, these effects are studied separately. However, the probability that they occur simultaneously in flight is significant. As a consequence, this work is about the study of the synergy between both cumulative and transient effects on various integrated bipolar technologies. The present results are used to provide some answers about potential changes of test methods. This work also evaluates the predictive capability of the previously developed model to reproduce accurately both the fast and the long lasting components of transients in circuitry and so to model transients' effects. This simulation methodology is extended to an operational amplifier from different manufacturers and for three different synergistic effects. The comparison between transients obtained experimentally during heavy ions, pulse laser and flash X experiments and the predicted transients validates the investigated methodology. The cumulative effects are taken into account by injecting the internal electrical parameters variations using irradiation exposure.

Este trabalho estuda os efeitos da radiação em dispositivos analógicos programáveis (FPAAs, do inglês, Field Programmable Analog Arrays) e técnicas de proteção que podem ser aplicadas para mitigar tais efeitos. Circuitos operando no espaço ou em altitudes elevadas, como, por exemplo, em satélites e aeronaves, recebem doses de radiação e impacto de íons e outras partículas que, dependendo da altitude e de características do próprio circuito, podem afetar o seu correto funcionamento. Os FPAAs proporcionam características interessantes aos sistemas analógicos e de sinal misto, como a prototipação rápida e a possibilidade de reconfiguração dinâmica (permitindo a implementação de sistemas de instrumentação e controle adaptativos). Assim, os FPAAs podem ser atrativos aos projetistas de sistemas de aplicação espacial, uma vez que a utilização de componentes comerciais, (COTS - do inglês, Commercial Off-The-Shelf), é uma alternativa para redução de custos do sistema final. Por isso, é necessário classificar estes dispositivos segundo o nível de tolerância à radiação e desenvolver técnicas de proteção contra seus efeitos. Essencialmente, é possível dividir os efeitos da radiação em dois principais grupos: efeitos de dose total ionizante ou TID (do inglês, Total Ionizing Dose) e os eventos singulares (Single Event Effects ou SEEs). Os dois principais eventos singulares que podem perturbar os FPAAs são investigados: os SETs (Single Event Transients) e os SEUs (Single Event Upsets). Os SETs podem gerar pulsos transientes em determinados nós do circuito, e, quando atingem o inversor de controle das portas de transmissão dos bancos de capacitores do dispositivo, podem ocasionar uma redistribuição de carga entre os capacitores do banco, afetando temporariamente o sinal que trafega pelo FPAA. Tais efeitos foram investigados através de simulações spice. Já os SEUs podem afetar os FPAAs que são baseados em memória do tipo SRAM. Para investigar tais efeitos foram realizados experimentos de injeção de falhas do tipo bit-flip (inversão de bit) no bitstream de programação de um FPAA baseado neste tipo de memória. Os experimentos mostraram que a inversão de um único bit pode ser catastrófica para o funcionamento do sistema. Posteriormente, um esquema self-checking (autoverificável) baseado em redundância foi proposto. Tal esquema foi construído com os recursos programáveis do FPAA e é capaz de recuperar os dados originais de programação do dispositivo se um erro for detectado. A capacidade do esquema proposto de detectar desvios funcionais no bloco sob teste e sua confiabilidade quando os seus próprios blocos são afetados por inversão de bits de memória, foram investigadas. Finalmente, os efeitos de dose total sobre dispositivos programáveis foram investigados através de um experimento prático, no qual um FPAA comercial foi bombardeado por radiação gama proveniente de uma fonte de Cobalto-60. Os resultados experimentais mostraramm que as chaves analógicas, que proporcionam a programabilidade do dispositivo, e seus circuitos de controle são os principais responsáveis por degradar o sinal processado pelo FPAA quando determinados níveis de dose total acumulada são atingidos. / In this work the radiation effects on Field Programmable Analog Arrays (FPAAs) are studied and mitigation techniques are proposed. The main effects induced by radiation sources in electronic circuits operating in space and at high altitudes are SEU (Single Event Upset), SET (Single Event Transient) and TID (Total Ionizing Dose). FPAAs are programmable analog circuits that provide design flexibility and some interesting features for applications such as adaptive control and instrumentation and evolvable analog hardware. These features can be very useful in avionics and space applications, where the system environmental variables can vary significantly in few minutes, being necessary to re-calibrate the sensor conditioning circuits to correct errors or improve system performance, for example. Since the use of commercial off-the-shelf (COTS) components may reduce systems costs in such critical applications, it is very important to develop system-level mitigation techniques (to radiation effects), aiming the increasing of the reliability of commercial available devices (including FPAAs). Some FPAA models are based on SRAM memory cells, which make this kind of device vulnerable to SEU when employed in applications susceptible to radiation incidence. An SEU can affect the programming memory of the FPAA and change the device configuration, modifying the analog circuit behavior. In this work, fault injection experiments were performed in order to investigate the effects of SEU in a commercial FPAA by injecting bit-flips in the FPAA programming bitstream. Then, a self-checking scheme was proposed. This scheme, which is built with the FPAA available programming resources, is able to restore the original programming data if an error is detected. Fault injection was also performed to investigate the reliability of the checker when the bitstream section which controls its own blocks is corrupted due to an SEU. Results indicated a very low aliasing probability due to single faults in the checker (0.24%). Effects of SET were also studied, considering the disturbance of the switches (transmission gates) of the FPAA programmable capacitor banks. Spice simulations showed that transient pulses in the control circuit of the switches may lead to charge redistribution between the capacitors of the bank, affecting the voltage and current of the involved nodes. Finally, total ionizing dose (TID) effects were investigated by means of an irradiation experiment. In such experiment the FPAA was exposed to Cobalt-60 gamma radiation. The experimental results showed that the analog switches of the device as well as their control circuits are the main responsible for degradating the processed signal when certain radiation levels were achieved.

A utilização de técnicas de tolerância a falhas em software é uma forma de baixo custo para proteger processadores contra soft errors. Contudo, elas causam aumento no tempo de execução e utilização de memória. Em consequência disso, o consumo de energia também aumenta. Sistemas que operam com restrição de tempo ou energia podem ficar impossibilitados de utilizar tais técnicas. Por esse motivo, este trabalho propoe técnicas de tolerância a falhas em software com custos no desempenho e memória reduzidos e cobertura de falhas similar a técnicas presentes na literatura. Como detecção é menos custoso que correção, este trabalho foca em técnicas de detecção. Primeiramente, um conjunto de técnicas de dados baseadas em regras de generalização, chamada VAR, é apresentada. As técnicas são baseadas nesse conjunto generalizado de regras para permitir uma investigação exaustiva, em termos de confiabilidade e custos, de diferentes variações de técnicas. As regras definem como a técnica duplica o código e insere verificadores. Cada técnica usa um diferente conjunto de regras. Então, uma técnica de controle, chamada SETA, é introduzida. Comparando SETA com uma técnica estado-da-arte, SETA é 11.0% mais rápida e ocupa 10.3% menos posições de memória. As técnicas de dados mais promissoras são combinadas com a técnica de controle com o objetivo de proteger tanto os dados quanto o fluxo de controle da aplicação alvo. Para reduzir ainda mais os custos, métodos para aplicar seletivamente as técnicas propostas foram desenvolvidos. Para técnica de dados, em vez de proteger todos os registradores, somente um conjunto de registradores selecionados é protegido. O conjunto é selecionado com base em uma métrica que analisa o código e classifica os registradores por sua criticalidade. Para técnicas de controle, há duas abordagens: (1) remover verificadores de blocos básicos, e (2) seletivamente proteger blocos básicos. As técnicas e suas versões seletivas são avaliadas em termos de tempo de execução, tamanho do código, cobertura de falhas, e o Mean Work to Failure (MWTF), o qual é uma métrica que mede o compromisso entre cobertura de falhas e tempo de execução. Resultados mostram redução dos custos sem diminuição da cobertura de falhas, e para uma pequena redução na cobertura de falhas foi possível significativamente reduzir os custos. Por fim, uma vez que a avaliação de todas as possíveis combinações utilizando métodos seletivos toma muito tempo, este trabalho utiliza um método para extrapolar os resultados obtidos por simulação com o objetivo de encontrar os melhores parâmetros para a proteção seletiva e combinada de técnicas de dados e de controle que melhorem o compromisso entre confiabilidade e custos. / Software-based fault tolerance techniques are a low-cost way to protect processors against soft errors. However, they introduce significant overheads to the execution time and code size, which consequently increases the energy consumption. System operation with time or energy restrictions may not be able to make use of these techniques. For this reason, this work proposes software-based fault tolerance techniques with lower overheads and similar fault coverage to state-of-the-art software techniques. Once detection is less costly than correction, the work focuses on software-based detection techniques. Firstly, a set of data-flow techniques called VAR is proposed. The techniques are based on general building rules to allow an exhaustive assessment, in terms of reliability and overheads, of different technique variations. The rules define how the technique duplicates the code and insert checkers. Each technique uses a different set of rules. Then, a control-flow technique called SETA (Software-only Error-detection Technique using Assertions) is introduced. Comparing SETA with a state-of-the-art technique, SETA is 11.0% faster and occupies 10.3% fewer memory positions. The most promising data-flow techniques are combined with the control-flow technique in order to protect both dataflow and control-flow of the target application. To go even further with the reduction of the overheads, methods to selective apply the proposed software techniques have been developed. For the data-flow techniques, instead of protecting all registers, only a set of selected registers is protected. The set is selected based on a metric that analyzes the code and rank the registers by their criticality. For the control-flow technique, two approaches are taken: (1) removing checkers from basic blocks: all the basic blocks are protected by SETA, but only selected basic blocks have checkers inserted, and (2) selectively protecting basic blocks: only a set of basic blocks is protected. The techniques and their selective versions are evaluated in terms of execution time, code size, fault coverage, and Mean Work To Failure (MWTF), which is a metric to measure the trade-off between fault coverage and execution time. Results show that was possible to reduce the overheads without affecting the fault coverage, and for a small reduction in the fault coverage it was possible to significantly reduce the overheads. Lastly, since the evaluation of all the possible combinations for selective hardening of every application takes too much time, this work uses a method to extrapolate the results obtained by simulation in order to find the parameters for the selective combination of data and control-flow techniques that are probably the best candidates to improve the trade-off between reliability and overheads.