In wireless communication systems, one of the most important resources being focused on all the researchers is spectrum. A cognitive radio (CR) system is one of the efficient ways to access the radio spectrum opportunistically, and efficiently use the available underutilized licensed spectrum. Spectrum utilization can be significantly enhanced by developing more applications with adopting CR technology. CR systems are implemented using a radio technology called software-defined radios (SDR). SDR provides a flexible and cost-effective solution to fulfil the requirements of end users. We can see a lot of innovations in Internet of Things (IoT) and increasing number of smart devices. Hence, a CR system application involving an IoT device is studied in this thesis. Opportunistic spectrum access involves two tasks of CR system: spectrum sensing and dynamic spectrum access. The functioning of the CR system is rest upon the spectrum sensing. There are different spectrum sensing techniques used to detect the spectrum holes and a few of them are discussed here in this thesis. The simplest and easiest to implement energy detection spectrum sensing technique is used here to implement the CR system. Dynamic spectrum access involves different models and strategies to access the spectrum. Amongst the available models, an interweave model is more challenging and is used in this thesis. Interweave model needs effective spectrum sensing before accessing the spectrum opportunistically. The system designed and simulated in this thesis is capable of transmitting an output from an IoT device using USRP and GNU radio through accessing the radio spectrum opportunistically.

Software radio is a radio that is substantially defined in software and whose physical layer behavior can be significantly altered through changes to its software. As a primary goal of software radio is the ability to support existing and future wireless protocols, software radio necessitates the use of a rapidly reprogrammable baseband processing solution. However third generation wireless protocols represent a significant increase in complexity over second generation protocols. Due to the natural performance sacrifices that must be made when moving an application from an Application Specific Integrated Circuit (ASIC) to a general purpose processor or a digital signal processor, it is feared that reprogrammable processing solutions may not suffice for the emerging wireless protocols, which would significantly hinder the realization of software radio, particularly in the handheld domain where power consumption and chip area are critical. Recently, the Configurable Computing Lab at Virginia Tech developed a new breed of reprogrammable processor which they called "custom computing machine" (CCM). Representing a dramatic departure from traditional architectures used for baseband processing solutions, CCMs utilize a large number of optimized and programmable processing cores connected through a programmable mesh. Due to this architectural approach, CCMs have been promoted as supplying a level of processing power and power efficiency similar to ASICs while providing a level of reconfigurability similar to that of a DSP. Subsequently, Dr. Srikathyayani Srikanteswara proposed a new software radio architecture, known as the Layered Radio Architecture, which is intended to facilitate the inclusion of CCMs into a software radio. The primary goal of the research presented in this thesis is to demonstrate how a particular CCM, Stallion, can be used within the Layered Radio Architecture to provide sufficient processing performance, power efficiency, and reconfigurability to meet the constraints of the handheld domain through implementations of a single user adaptive receiver with adaptive complex filtering and a W-CDMA downlink rake receiver. These metrics are measured from a detailed simulation of Stallion and the Configuration Layer of the Layered Radio Architecture using advanced object oriented programming techniques that facilitate the inclusion of statistics gathering routines into normal operation. To provide perspective, these statistics are compared to the performance that could be expected from an implementation on a top-of-the-line DSP. / Master of Science

This dissertation presents novel Harmonic Rejection (HR) Mixer architectures to obtain a high level of harmonic rejection. This is achieved by reducing the sensitivity to mismatches in devices operating at high frequencies. Consequently, the HR performance for this mixer architecture is primarily determined by resistor and capacitor matching at low intermediate frequencies (IF). Since large resistor areas can be used at relatively less power penalty in the low frequency IF section, superior HR performance is realized. A design fabricated in 110 nm CMOS process, rejects up to the fi rst 14 local oscillator (LO) harmonics and achieves 3rd, 5th and 7th HR ratios in excess of 52, 54 and 55 dB respectively, without any calibration or trimming. This mixer architecture also rejects flicker noise, has improved image rejection (IR) and second-order input-intercept-point (IIP2) performance. By using a clock N times the desired LO frequency, this scheme rejects the (N-1)th LO harmonic only by an amount of 20log(N-1) dB. A new technique is presented that enables better HR for the (N-1)th harmonic while preserving the level of rejection for other harmonics. This mixer fabricated in 55 nm standard CMOS process has a programmable number of 8, 10, 12 or 14 mixer phases and achieves an improvement of 29 dB for the (N-1)th harmonic while achieving 52 dB of rejection for the 3rd harmonic. It also rejects flicker noise and has an IIP2 performance of 68 dBm. The mixers presented in this dissertation set the state-of-the-art in HR performance for single-stage mixers with configurable number of phases without using any calibration or trimming. / text

Le développement de la radio logicielle fait suite à l’évolution rapide du domaine des télécommunications. Les besoins en performance et en dynamicité ont donné naissance à des MPSoC dédiés à la radio logicielle. La spécialisation de ces MPSoC rend cependant leur pro- grammation et leur vérification complexes. Des travaux proposent d’atténuer cette complexité par l’utilisation de paradigmes tels que le modèle de calcul flot de données. Parallèlement, le besoin de modèles flexibles et vérifiables a mené au développement de nouveaux modèles flot de données paramétriques. Dans cette thèse, j’étudie la compilation d’applications utilisant un modèle de calcul flot de données paramétrique et ciblant des plateformes de radio logicielle. Après un état de l’art du matériel et logiciel du domaine, je propose un raffinement de l’ordonnancement flot de données, et présente son application à la vérification des tailles mémoires. Ensuite, j’introduis un nouveau format de haut niveau pour définir le graphe et les acteurs flot de données, ainsi que le flot de compilation associé. J’applique ces concepts à la génération de code optimisé pour la plateforme de radio logicielle Magali. La compilation de parties du protocole LTE permet d’évaluer les performances du flot de compilation proposé. / The emergence of software-defined radio follows the rapidly evolving telecommunication domain. The requirements in both performance and dynamicity has engendered software- defined-radio-dedicated MPSoCs. Specialization of these MPSoCs make them difficult to program and verify. Dataflow models of computation have been suggested as a way to mi- tigate this complexity. Moreover, the need for flexible yet verifiable models has led to the development of new parametric dataflow models. In this thesis, I study the compilation of parametric dataflow applications targeting software-defined-radio platforms. After a hardware and software state of the art in this field, I propose a new refinement of dataflow scheduling, and outline its application to buffer size’s verification. Then, I introduce a new high-level format to define dataflow actors and graph, with the associated compilation flow. I apply these concepts to optimised code generation for the Magali software-defined-radio platform. Compilation of parts of the LTE protocol are used to evaluate the performances of the proposed compilation flow.

Les travaux de recherche de cette thèse de doctorat s’inscrivent dans le cadre de la conception d’unconvertisseur analogique-numérique (ADC, Analog-to-Digital Converter) large bande et à haute résolution afinde numériser plusieurs standards de communications sans fil. Il répond ainsi au concept de la radio logiciellerestreinte (SDR, Software Defined Radio). L’objectif visé est la reconfigurabilité par logiciel et l’intégrabilité envue d’un système radio multistandard. Les ADCs à sur-échantillonnage de type sigma-delta () s’avèrent debons candidats dans ce contexte de réception SDR multistandard en raison de leur précision accrue. Bien queleur bande passante soit réduite, il est possible de les utiliser dans une architecture en parallèle permettantd’élargir la bande passante. Nous nous proposons alors dans cette thèse de dimensionner et d’implanter unADC parallèle à décomposition fréquentielle (FBD) basé sur des modulateurs  à temps-discret pour unrécepteur SDR supportant les standards E-GSM, UMTS et IEEE802.11a. La nouveauté dans l’architectureproposée est qu’il est programmable, la numérisation d’un signal issu d’un standard donné se réalise enactivant seulement les branches concernées de l’architecture parallèle avec des sous-bandes defonctionnement et une fréquence d’échantillonnage spécifiée. De plus, le partage fréquentiel des sous-bandesest non uniforme. Après validation du dimensionnement théorique par simulation, l’étage en bande de base aété dimensionné. Cette étude conduit à la définition d’un filtre anti-repliement passif unique d’ordre 6 et detype Butterworth, permettant l’élimination du circuit de contrôle de gain automatique (AGC). L’architectureFBD requière un traitement numérique permettant de combiner les signaux à la sortie des branches enparallèle pour reconstruire le signal de sortie finale. Un dimensionnement optimisé de cet étage numérique àbase de démodulation a été proposé. La synthèse de l’étage en bande de base a montré des problèmes destabilité des modulateurs . Pour y remédier, une solution basée sur la modification de la fonction detransfert du signal (STF) afin de filtrer les signaux hors bande d’intérêt par branche a été élaborée. Unediscontinuité de phase a été également constatée dans le signal de sortie reconstruit. Une solution deraccordement de phase a été proposée. L’étude analytique et la conception niveau système ont étécomplétées par une implantation de la reconstruction numérique de l’ADC parallèle. Deux flots de conceptionont été considérés, un associé au FPGA et l’autre indépendant de la cible choisie (VHDL standard).L’architecture proposée a été validée sur un FPGA Xilinx de type VIRTEX6. Une dynamique de 74 dB a étémesurée pour le cas d’étude UMTS, ce qui est compatible avec celle requise du standard UMTS. / The work presented in this Ph.D. dissertation deals with the design of a wideband and accurate Analog-to-Digital Converter (ADC) able to digitize signals of different wireless communications standards. Thereby, itresponds to the Software Defined Radio concept (SDR). The purpose is reconfigurability by software andintegrability of the multistandard radio terminal. Oversampling  (Sigma Delta) ADCs have been interestingcandidates in this context of multistandard SDR reception thanks to their high accuracy. Although they presentlimited operating bandwidth, it is possible to use them in a parallel architecture thus the bandwidth isextended. Therefore, we propose in this work the design and implementation of a parallel frequency banddecomposition ADC based on Discrete-time  modulators in an SDR receiver handling E-GSM, UMTS andIEEE802.11a standard signals. The novelty of this proposed architecture is its programmability. Where,according to the selected standard digitization is made by activating only required branches are activated withspecified sub-bandwidths and sampling frequency. In addition the frequency division plan is non-uniform.After validation of the theoretical design by simulation, the overall baseband stage has been designed. Resultsof this study have led to a single passive 6th order Butterworth anti-aliasing filter (AAF) permitting theelimination of the automatic gain control circuit (AGC) which is an analog component. FBD architecturerequires digital processing able to recombine parallel branches outputs signals in order to reconstruct the finaloutput signal. An optimized design of this digital reconstruction signal stage has been proposed. Synthesis ofthe baseband stage has revealed  modulators stability problems. To deal with this problem, a solution basedon non-unitary STF has been elaborated. Indeed, phase mismatches have been shown in the recombinedoutput signal and they have been corrected in the digital stage. Analytic study and system level design havebeen completed by an implementation of the parallel ADC digital reconstruction stage. Two design flows havebeen considered, one associated to the FPGA and another independent of the chosen target (standard VHDL).Proposed architecture has been validated using a VIRTEX6 FPGA Xilinx target. A dynamic range over 74 dB hasbeen measured for UMTS use case, which responds to the dynamic range required by this standard.

This term paper is the second part of the dissertation FM RDS signal processing using FPGAs. In the first half of the work is processed the information needed before the actual design and implementation. These can be divided into three themes. The first theme is the received signal VHF / FM + RDS, the second one handles the problem of software radio and last topic concerns FPGAs. The second half deals with the solution implementation and receiver radio VHF / FM and bitrate optional RDS to digital form and its implementation on FPGA. This section also includes the measurement of results.

Cognitive radio is frequently touted as a platform for implementing dynamic distributed radio resource management algorithms. In the envisioned scenarios, radios react to measurements of the network state and change their operation according to some goal driven algorithm. Ideally this flexibility and reactivity yields tremendous gains in performance. However, when the adaptations of the radios also change the network state, an interactive decision process is spawned and once desirable algorithms can lead to catastrophic failures when deployed in a network. This document presents techniques for modeling and analyzing the interactions of cognitive radio for the purpose of improving the design of cognitive radio and distributed radio resource management algorithms with particular interest towards characterizing the algorithms' steady-state, convergence, and stability properties. This is accomplished by combining traditional engineering and nonlinear programming analysis techniques with techniques from game to create a powerful model based approach that permits rapid characterization of a cognitive radio algorithm's properties. Insights gleaned from these models are used to establish novel design guidelines for cognitive radio design and powerful low-complexity cognitive radio algorithms. This research led to the creation of a new model of cognitive radio network behavior, an extensive number of new results related to the convergence, stability, and identification of potential and supermodular games, numerous design guidelines, and several novel algorithms related to power control, dynamic frequency selection, interference avoidance, and network formation. It is believed that by applying the analysis techniques and the design guidelines presented in this document, any wireless engineer will be able to quickly develop cognitive radio and distributed radio resource management algorithms that will significantly improve spectral efficiency and network and device performance while removing the need for significant post-deployment site management. / Ph. D.