The SRAM memory generator in this thesis is divided into four parts: row decoder, storage cell, column decoder, and sense amplifier & write controller. The row decoder is designed using pass-transistors logic with better area and regularity compared with conventional NAND based decoders. Two different column decoders, tree structure and NOR based predecoder, are provided in current version. Although only SRAM is implemented in this thesis, the memory generator platform is complete with all the necessary models required in the embedded design. In the future, other memories, such as cache, shift register, FIFO, stacks, ROM, register files, and content addressable memory, can be integrated in this memory generator platform.

Novel logic and memory device concepts are proposed and analyzed. For the latter purpose the commercial technology computer aided design (TCAD) simulators Taurus and Sentaurus Device by Synopsys are used. These simulators allow ready definition of complex device geometries. Moreover, while not all device physics models are state-of-the-art, the wide variety of device physics considered is advantageous here when not all of the critical device physics is known a priori. The initial device concept analyzed was a one transistor (1T), one capacitor (1C) – pseudo-static random access memory (SRAM). Simulations indicate that tri-gate pass-transistors will offer better gate control and reduced leakage, and tri-gate capacitors will offer increased capacitance, making the overall device performance comparable to SRAM. The second device analyzed was a quantum dot non-volatile memory. In principle, such memories become more reliable for a given tunnel oxide thickness by localizing any leaks to individual dots. However, simulations illustrate limits on dot packing density to retain this advantage due to inter-dot tunneling. The final device, proposed and extensively analyzed here, is a novel tunnel field-effect transistor (TFET), the “hetero-barrier TFET” (HetTFET). In complementary metal-oxide-semiconductor (CMOS) logic, while switching power decreases with voltages, standby power increases due to thermionic emission of charge carriers over the source-to-channel barrier in the constituent metal-oxide-semiconductor field-effect transistors (MOSFETs). As a result, CMOS voltage and, thus, power scaling is approaching an impasse. Because TFETs are not subject to thermionic emission, they are being considering as a replacement for MOSFETs. Various materials systems and device geometries have been considered. However, even in simulation, balancing switching and standby power at low voltages while still providing sufficient transconductance for rapid switching has not proven straightforward. HetTFETs are intended to achieve high on-to-off current ratios via a threshold defined by the onset of band overlap, and high ON-state transconductances via tunneling through thin barriers defined by crystal growth, rather than relying on gate-controlled barrier narrowing in whole or part for either purpose as with other designs. Simulations of n and p-channel HetTFETs suggest the possibility of current CMOS-like performance at much lower voltages. / text

Static Random Access Memory (SRAM) is a critical component in mobile video processing systems. Because of the large video data size, the memory is frequently accessed, which dominates the power consumption and limits battery life. In energy-efficient SRAM design, a substantial amount of research is presented to discuss the mechanisms of approximate storage, but the content and environment adaptations were never a part of the consideration in memory design. This dissertation focuses on optimization methods for the SRAM system, specifically addressing three areas of Intelligent Energy-Efficient Storage system design. First, the SRAM stability is discussed. The relationships among supply voltage, SRAM transistor sizes, and SRAM failure rate are derived in this section. The result of this study is applied to all of the later work. Second, intelligent voltage scaling techniques are detailed. This method utilizes the conventional voltage scaling technique by integrating self-correction and sizing techniques. Third, intelligent bit-truncation techniques are developed. Viewing environment and video content characteristics are considered in the memory design. The performance of all designed SRAMs are compared to published literature and are proven to have improvement.

AN ABSTRACT OF THE THESIS OFAPARNA REDDY KOTTE, for the Master of science degree in Electrical and Computer Engineering, presented on November 5,2020, at Southern Illinois University Carbondale. TITLE: MEMRISTOR BASED SRAM MAJOR PROFESSOR: Dr. Haniotokis Themistoklis The easy usage and less standby leakage are the main reasons SRAMs are mostly used for mobile applications both on chip and off chip memories. Various SRAM cells have been under research for many years. In post-CMOS era, rising of memristor technology is expected to be a key driver due to its outstanding features to replace the present memory technologies. Memristor is a non-volatile component that memorizes the proportion of current passed through it, reserving the data in the form of resistance. With its non-volatile characteristics, ultra-low power consumption, higher density capability, fast operating speed, ability to function as a multi-level cell and good scalability and compatibility with CMOS technology, memristor technology is found to be best to replace the SRAM cells. Memristor based SRAM cell can be an efficient circuit component that is being proposed in this thesis which consumes less power and allows the conventional SRAM cell to retain data with lesser number of transistors at power-down without any auxiliary circuit. This thesis contains the operating procedure and simulated results of the proposed four transistor and two memristor SRAM using 90nm technology performed on Cadence Virtuoso tool.

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This report discusses the design of read/write assist circuits which are used in a SRAM cell’s design to overcome the cell’s variations. It also explains the variability problems in a SRAM bit-cell and many approaches to address them. The basic operations, SNM concept, and write margin of an SRAM are described theoretically as well as measured in simulation. The write assisted circuit, the Negative Bit-line Voltage Bias scheme, is discussed and implemented at transistor level using a six-transistor (6T) SRAM cell. With the write assisted circuit, the implemented memory array successfully performs a write operation at 0.6V and -25°C, the condition in which the same operation would fail without the write assisted circuit. During the simulation, this write assisted circuit helps to achieve the negative bias voltage of -70mV on the SRAM’s bit-lines. The cost overhead includes chip area, power consumption, and current leakage when this Negative Bit-line Voltage scheme is implemented. / text

Les circuits cryptographiques, parce qu'ils contiennent des informations confidentielles, font l'objet de manipulations frauduleuses, appelées communément attaques, de la part de personnes mal intentionnées. Plusieurs attaques ont été répertoriées et analysées. L'une des plus efficaces actuellement, appelée cryptanalyse DFA (Differential Fault Analysis), exploite la présence de fautes, injectées volontairement par l’attaquant par exemple à l’aide d’un laser, dans les calculs. Cependant, les modèles de fautes utilisés dans ces attaques sont parfois très restrictifs et conditionnent leur efficacité. Il est donc important de bien connaître quel modèle de faute est pertinent ou réalisable en fonction du circuit cible et du moyen d'injection (dans notre cas le laser). Un première étude portant sur le type de fautes (Bit-set, Bit-reset ou Bit-flip) injectées sur des points mémoires SRAM a mis en évidence la forte dépendance des fautes injectées vis à vis des données manipulées et la quasi inexistence de fautes de type Bit-flip. Ce dernier résultat favorise grandement les attaques de type Safe Error et engendre donc un réel problème de sécurité. La mise en évidence de tels résultats a été possible grâce à des cartographies de sensibilité au laser réalisées sur une cellule SRAM isolée puis sur la mémoire RAM d'un micro-contrôleur 8 bits. Pour confirmer ces résultats expérimentaux, des simulations SPICE d'injection de fautes laser ont été réalisées à partir d'un modèle développé dans l’équipe. Ce modèle prend en compte la topologie de la cible. Des tests ont ensuite été réalisés sur un circuit ASIC implémentant l'algorithme AES. L'analyse des fautes a montré la présence des trois types de fautes mais aussi un faible taux d'injection. En revanche, le taux de répétabilité des fautes était particulièrement élevé. Cela nous a permis d'améliorer une attaque existante et d'obtenir au final une attaque plus efficace que les attaques classiques, nécessitant moins de chiffrements fautés et une analyse des résultats réduite pour retrouver la clef secrète. Enfin, une évaluation des contre-mesures embarquées dans ce circuit a montré leurs inefficacités vis à vis des attaques en fautes par laser. Des pistes d'amélioration ont ensuite été proposées. / Cryptographic circuits, because they contain confidential informations, are subject to fraud from malicious users, commonly known as attacks. Several attacks have been published and analysed. One of the most effective attack, called Differential Fault Analysis (DFA), uses some fault, voluntary injected by the attacker during the computations, for example with a laser. However, fault models used by these attacks can be restrictive and determine the effectiveness of the attack. Thus, it is important to know which fault model is useful or feasible according to the targeted device or injection means (in our case the laser).A first study about the injected fault types (Bit-set, Bit-reset or Bit-flip) on SRAM memory cells highlighted the strong data dependency of the injected faults and the irrelevance of the Bit-flip fault type. This last result allows to mount Safe Error attacks and creates a real security issue. These results were obtain thanks to sensitivity laser map performed on an isolated SRAM cell and on an 8-bits micro-controller RAM memory. To confirm these experimental results, SPICE simulations have been made with a model developed in the department. This model takes into account the topology of the target.Tests were then carried out on an ASIC implementing the AES algorithm. The fault analysis showed the presence of the three types of faults but also a low injection rates. In contrast, the error repeatability was particularly high. This allowed us to simplify an existing attack and to obtain an attack more effective than conventional attacks, requiring fewer faulted cipher text and reducing the complexity of the analysis to find the secret key. Finally, an assessment of the countermeasure of this circuit showed their ineffectiveness with respect to fault laser attacks. Areas for improvement were then proposed.

La complexité des systèmes électroniques ne cesse d’augmenter, tout comme la tendance actuelle de miniaturisation des transistors. La fiabilité est ainsi devenue un continuel défi. Les environnements hostiles caractérisés par des conditions extrêmes de hautes températures affectent le bon fonctionnement des systèmes. Pour les composants de stockage de données, la température est considérée comme une menace pour la fiabilité. Le développement de techniques de suivi et de contrôle devient ainsi essentiel afin de garantir la fiabilité des mémoires volatiles et non volatiles. Dans le cadre de ma thèse, je me suis intéressée à deux types de mémoires : les mémoires NAND Flash et les mémoires SRAM. Pour contrôler les effets de la température sur les mémoires Flash, une solution basée sur l’utilisation d’un timer a été proposée afin de réduire la fréquence de rafraîchissement de ces mémoires tout en continuant à garantir l’intégrité de l’information stockée. Pour les mémoires SRAM, l’effet de la température sur la vulnérabilité par rapport aux événements singuliers (SEU) a été étudiée. Une étude comparative sur l’apparition des SEU a été menée avec différentes températures pour des cellules standards 6T-SRAM et des cellules de stockage durcies (DICE). Enfin, une méthode statistique et une approximation calculatoire basées sur des opérations de vérification périodique ont été proposées afin d’améliorer le taux d’erreurs (RBER) tolérable dans des SSDs de type Entreprise à base de mémoires Flash. / With the constant increase of microelectronic systems complexity and the continual scaling of transistors, reliability remains one of the main challenges. Harsh environments, with extreme conditions of high temperature and thermal cycling, alter the proper functioning of systems. For data storage devices, high temperature is considered as a main reliability threat. Therefore, it becomes essential to develop monitoring techniques to guarantee the reliability of volatile and non-volatile memories over an entire range of operating temperatures. In the frame of this thesis, I focus my studies on two types of memories: NAND Flash memories and SRAM. To monitor the effects of temperature in NAND Flash Memories, a timer-based solution is proposed in order to reduce the refresh frequency and continue to guarantee the integrity of data. For SRAM memories, the effect of temperature on Single Event Upset (SEU) sensitivity is studied. A comparative study on SEU occurrence under different temperatures is conducted for standard 6T-SRAM cells and hardened Dual Interlocked Storage Cells (DICE). Finally, statistical and computational approximation techniques based on periodic check operations are proposed in order to improve the tolerated Raw Bit Error Rate (RBER) in enterprise-class Flash based SSDs.

Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-09-11T13:09:26Z No. of bitstreams: 1 DIS_GUILHERME_CARDOSO_MEDEIROS_COMPLETO.pdf: 10767866 bytes, checksum: f8ce0a0593916dec149c9417c21ff36e (MD5) / Made available in DSpace on 2017-09-11T13:09:26Z (GMT). No. of bitstreams: 1 DIS_GUILHERME_CARDOSO_MEDEIROS_COMPLETO.pdf: 10767866 bytes, checksum: f8ce0a0593916dec149c9417c21ff36e (MD5) Previous issue date: 2017-08-17 / Coordena??o de Aperfei?oamento de Pessoal de N?vel Superior - CAPES / Miniaturiza??o tem sido adotada como o principal objetivo da ind?stria de Circuitos Integrados (CIs) nos ?ltimos anos, uma vez que agrega muitos benef?cios tais como desempenho, maior densidade, e baixo consumo de energia. Junto com a miniaturiza??o da tecnologia CMOS, o aumento na quantidade de dados a serem armazenados no chip causaram a amplia??o do espa?o ocupado por mem?rias do tipo Static Random-Access Memory (SRAM) em System-on-Chips (SoCs). Tal miniaturiza??o e evolu??o da nanotecnologia proporcionou muitas revolu??es na ind?stria de semicondutores, tornando necess?rio tamb?m a melhoria no processo de fabrica??o de CIs. Devido a sensibilidade causada pela miniaturiza??o e pelas variabilidades de processo de fabrica??o, eventuais defeitos introduzidos durante fabrica??o podem danificar o CI, afetando o n?vel de confiabilidade do CI e causando perdas no rendimento por die fabricado. A miniaturiza??o adotada pela ind?stria de semicondutores impulsionou a pesquisa de novas tecnologias visando a substitui??o de transistores do tipo CMOS. Transistores FinFETs, devido a suas propriedades el?tricas superiores, emergiram como a tecnologia a ser adotada pela ind?stria. Com a fabrica??o de mem?rias utilizando a tecnologia FinFET, surge a preocupa??o com testes de mem?ria, uma vez que modelos de falhas e metodologias de teste utilizados para tecnologias planares podem n?o ser suficientes para detectarem todos os defeitos presented em tecnologias multi-gate. Uma vez que esta nova tecnologia pode ser afetada por novos tipos de falhas, testes que dependem da execu??o de opera??es, m?todos de endere?amento, checagem de padr?es, e outros tipos de condi??es de est?mulo, podem deixar de serem estrat?gias confi?veis para o teste dos mesmos. Neste contexto, este trabalho de mestrado prop?e uma metodologia baseada em hardware para testar mem?rias em FinFET que monitore par?metros do bloco de mem?ria e gere sinais baseados nessas caracter?sticas. Atrav?s do uso de sensores que monitoram os par?metros do circuito (como consumo de corrente, tens?o nas bit lines) e detectam mudan?as dos padr?es monitorados, os sensores criam pulsos que representam essas varia??es. Esses pulsos s?o modulados usando t?cnicas de modula??o. Uma vez que defeitos resistivos alteram os par?metros monitorados, c?lulas afetadas por esses defeitos apresentam diferentes sinais modulados, validando a metodologia proposta e permitindo a detec??o destes defeitos e consequentemente aumentando o yield de fabrica??o e a confiabilidade do circuito ao longo da sua vida. A metodologia baseada em hardware proposta neste trabalho foi implementada utilizando sensores integrados no pr?prio CI, e foi dividida em duas abordagens: monitoramento de consumo de corrente e monitoramento da tens?o nas bit lines. Cada abordagem foi validada com a inje??o de 12 defeitos resistivos de diferentes naturezas e localiza??es, a ap?s validados considerando diferentes temperaturas de opera??o e o impacto da varia??o de processo de fabrica??o. / Miniaturization has been the industry?s main goal over the last few years, as it brings benefits such as high performance and on-chip integration as well as power consumption reduction. Alongside the constant scale-down of Integrated Circuits (ICs) technology, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy great part of Systems-on-Chip (SoCs). The constant evolution of nanotechnology brought many revolutions to semiconductors, making it also necessary to improve the integrated circuit manufacturing process. Therefore, the use of new, complex processing steps, materials, and technology has become necessary. The technology-shrinking objective adopted by the semiconductor industry promoted research for technologies to replace CMOS transistors. FinFET transistors, due to their superior electrical properties, have emerged as the technology most probably to be adopted by the industry. However, one of the most critical downsides of technology scaling is related to the non-determinism of device?s electrical parameters due to process variation. Miniaturization has led to the development of new types of manufacturing defects that may affect IC reliability and cause yield loss. With the production of FinFET-based memories, there is a concern regarding embedded memory test and repair, because fault models and test algorithms used for memories based on conventional planar technology may not be sufficient to cover all possible defects in multi-gate memories. New faults that are specific to FinFETs may exist, therefore, current test solutions, which rely on operations executing specific patterns and other stressing conditions, may not stand to be reliable tools for investigating those faults. In this context, this work proposes a hardware-based methodology for testing memories implemented using FinFET technology that monitors aspects of the memory array and creates output signals deriving from the behavior of these characteristics. Sensors monitor the circuit?s parameters and upon changes from their idle values, create pulses that represent such variations. These pulses are modulated applying the pulse width modulation techniques. As resistive defects alter current consumption and bit line voltages, cells affected by resistive defects present altered modulated signals, validating the proposed methodology and allowing the detection of these defects. This further allows to increase the yield after manufacturing and circuit reliability during its lifetime. Considering how FinFET technology has evolved and the likelihood that ordinary applications will employ FinFET-based circuits in the future, the development of techniques to ensure circuit reliability has become a major concern. The presented hardware-based methodology, which was implemented using On-Chip Sensors, has been divided in two approaches: monitoring current consumption and monitoring the voltage level of bit lines. Each approach has been validated by injecting a total of 12 resistive defects, and evaluated considering different operation temperatures and the impact of process variation.