<p>This thesis discusses non-linearities associated with a sampling switch and compares transmission gate, bootstrapping and bulk-effect compensation architectures at circuit level from linearity point of view for 0.35 um CMOS process. All switch architectures have been discussed and designed with an additional constraint of switch reliability.</p><p>Results indicate that for a specified supply of 3.3 Volts, bulk-effect compensation does not improve third-order harmonic distortion significantly which defines the upper most limit on linearity for a differential topology. However, for low-voltage operations bulk-effect compensation improves third-order harmonic noticeably.</p>

This thesis discusses non-linearities associated with a sampling switch and compares transmission gate, bootstrapping and bulk-effect compensation architectures at circuit level from linearity point of view for 0.35 um CMOS process. All switch architectures have been discussed and designed with an additional constraint of switch reliability. Results indicate that for a specified supply of 3.3 Volts, bulk-effect compensation does not improve third-order harmonic distortion significantly which defines the upper most limit on linearity for a differential topology. However, for low-voltage operations bulk-effect compensation improves third-order harmonic noticeably.

RF switches are an essential building block in numerous applications, including tactical radar systems, satellite communications, global positioning systems (GPS), automotive radars, wireless communications, radio astronomy, radar transceivers, and various instrumentation systems. For many of these applications the circuits have to operate reliably under extreme operating conditions, including conditions outside the domain of commercial military specifications. The objective of this thesis is to present the design procedure, simulation, and measurement results for Radio Frequency (RF) switches in 130 nm Silicon Germanium (SiGe) BiCMOS process technology. The novelty of this work lies in the proposed new topology of an ultrahigh-isolation single-pole, single-throw (SPST) and a single pole, four-throw (SP4T) nMOS based switch for multiband microwave radar systems. The analysis of cryogenic temperature effects on these circuits and devices are discussed in this work. The results shows that several key-figures-of-merits of a switch, like insertion loss, isolation, and power handling capability (P1dB) improve at cryogenic temperatures. These results are important for several applications, including space-based extreme environment application where FET based circuits would need to operate reliably across a wide-range of temperature.

Self-adaptivity, characterized by the ability to dynamically adjust behavior at runtime, is a growing trend in the evolution of modern embedded systems. While self-adaptive systems tend to be flexible and autonomous, self-adaptivity may inevitably complicate software design, test and analysis. A strategy for taming the growing software complexity of self-adaptive systems is to partition system behaviors into different operational modes specified at design time. Such a multi-mode system can change behavior by switching between modes at runtime under certain circumstances. Multi-mode systems can benefit from a complementary approach to the software development of complex systems: Component-Based Software Engineering (CBSE), which fosters reuse of independently developed software components. However, the state-of-the-art component-based development of multi-mode systems does not take full advantage of CBSE, as reuse of modes at component level is barely addressed. Modes are often treated as system properties, while mode switches are handled by a global mode manager. This centralized mode management entails global information of all components, whereas the global information may be inaccessible in component-based systems. Another potential problem is that a single mode manager does not scale well, particularly at design time,  for a large number of components and modes.   In this thesis we propose a distributed solution to the component-based development of multi-mode systems, aiming for a more efficient and scalable mode management. Our goal is to fully incorporate modes in software component reuse, supporting reuse of multi-mode components, i.e., components able to run in multiple modes. We have developed a generic framework, the Mode-Switch Logic (MSL), which not only supports reuse of multi-mode components but also provides runtime mechanisms for handling mode switch. MSL includes three fundamental elements: (1) a mode-aware component model with the formal specification of reusable multi-mode software components; (2) a mode mapping mechanism for the seamless composition of multi-mode components; and (3) a mode-switch runtime mechanism which is executed by each component in isolation from its functional execution and coordinates the mode switches of different components without the need of global mode information. The mode-switch runtime mechanism has been verified by model checking in conjunction with mathematical proofs. We also provide a mode-switch timing analysis for the runtime mechanism to respect real-time requirements.   MSL is dedicated to the mode aspect of a system irrespective of component execution semantics, thus independent of the choice of component models. We have integrated MSL in the ProCom component model with the extension of support for reuse of multi-mode components and distributed mode-switch handling. Although the distributed mode-switch handling of MSL is more flexible and scalable than the conventional centralized approach, when components are deployed on a single hardware platform and global mode information is available, centralized mode-switch handling is more efficient in terms of runtime overhead and mode-switch time. Hence, MSL is supplemented with a mode transformation technique to enhance runtime mode-switch efficiency by converting the distributed mechanism to a centralized mechanism. MSL together with the mode transformation technique has been implemented in a prototype tool where one can build multi-mode systems by reusing multi-mode components. The applicability of MSL is demonstrated in two proof-of-concept case studies. / ARROWS - Design Techniques for Adaptive Embedded Systems

ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California / Network switches are an integral part of most network-based data acquisition systems. Switches fall into the category of network infrastructure. They support the interconnection of nodes and the movement of data in the overall network. Unlike endpoints such as data acquisition units, recorders, and display modules, switches do not collect, store or process data. They are a necessary expense required to build the network. The goal of this paper is to show how a small integrated network switch can be used to maximize the value proposition of a given switch port in the network. This can be accomplished by maximizing the bandwidth utilization of individual network segments and minimizing the necessary wiring needed to connect all the network components.

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This master thesis was part of a project at the Acreo Swedish ICT AB to investigate the 28 nm FDSOI CMOS process technology for the LTE front-end application. The project has resulted in a chip that contains different test circuits such as power amplifier (PA), mixer, low noise amplifier (LNA), RF power switch, and a receiver front-end. This thesis presents the evaluation of the RF power switch. At first, a stand-alone six-stacked single pole single throw (SPST) RF power switch was designed according to Rascher, and then it was modified to single pole double throw (SPDT) RF power switch according to the requirements of the project. This report presents an overview of the FDSOI CMOS process, basic theory of the RF switch, and the evaluation techniques. The post-simulation results showed that with the proper substrate biasing and matching (50 Ω), the RF switch will provide 2.5 dB insertion loss (IL) up to 27 dBm input power and over 30 dB isolation with 30 dBm input power at 2 GHz. / Detta examensarbete har varit en del av ett projekt på Acreo Swedish ICT AB för att undersöka 28 nm FDSOI CMOS teknik för LTE front-end tillämpningar. Projektet har resulterat i ett chip som innehåller olika testkretsar: effektförstärkare, mixer, RF-effektomkoppare, LNA, och en mottagarfront-end. Denna avhandling presenterar en utvärdering av RF-omkopplaren. En SPST RF-omkopplare med sex staplade transistor konstruerades enligt Rascher. Sedan modifierades konstruktionen till en SPDT-omkoppare i enlighet med kraven för projektet. Denna rapport presenterar en översikt över FDSOI CMOS-tekniken, grundläggande teori för en RF switch samt utvärderingsmetoder. Simuleringsresultaten visade att med rätt substratbiasering och matchning (50 Ω), så ger RF-omkopplaren 2,5 dB förlust (IL) på upp till 27 dBm ineffekt och över 30 dB isolering med 30 dBm ineffekt vid 2 GHz.

La haute performance ainsi que la basse consommation d’énergie offertes par lesField-Programmable Gate Arrays (FPGAs) contribuent à leur popularité en tant queaccélérateurs matériels. Cet argument a été soutenu par les intégrations récentes des FPGAs dans des systèmes cloud et centre de données. Toutefois, le potentiel d’une architecture reconfigurable peut être encore optimisé en traitant les FPGAs comme une ressource virtualisée et en les offrant une capacité de multitâche. La solution pour interrompre une tâche sur FPGAs à pour objectif d’effectuer un changement de contexte matériel (hardware context switch) a été un sujet de recherche depuis des nombreuses années. Les travaux précédents ont principalement proposé une stratégie pour extraire le contexte d’une tâche en cours de son exécution d’un FPGA pour offrir la possibilité de sa reprise plus tard. Cependant, la communication tout au long du processus n’a pas reçu autant d’attention.Dans cette thèse, nous étudions la gestion de communication d’une tâche matérielle durant son changement de contexte. Cette gestion de communicationest nécessaire pour garantir la cohérence de la communication d’une tâche dans un système reconfigurable avec la capacité de changement de contexte. Autrement, un changement de contexte matériel est seulement autorisé sous des contraintes restrictifs; il est possible après que les flux de communication soient fini et que toutes les données d’entrées/de sorties sont déjà consommées. De plus, certaines techniques demandent l’homogénéité au sein de la plate-forme pour qu’un changement de contexte matériel puisse se réaliser.Nous présentons içi un mécanisme qui conserve la cohérence de communication durant un changement de contexte matériel dans une architecture reconfigurable. Les données de communication sont gérées avec le contexte de tâche pour assurer leur intégrité. La gestion du contexte et les données de communication suivent un protocole spécifique pour des architectures hétérogènes reconfigurables. Ce protocole permet donc un changement de contexte matériel pendant que la tâche a encore des flux de communication. À partir des expérimentations, nous découvrons que le surcoût de la gestion de communication devient négligeable car notre mécanisme fournit une grande réactivité nécessaire pour l’allocation de tâche de façon préemptive - outre que sa consistance de communication. Enfin, les applications de solution proposée sont présentées dans un prototypage de tâche migration et dans un système utilisant un hyperviseur. / Field-Programmable Gate Arrays (FPGAs) have been gaining popularity as hardware accelerators in heterogeneous architectures thanks to their high performance and low energy consumption. This argument has been supported by the recent integration of FPGA devices in cloud services and data centers. The potential offered by the reconfigurable architectures can still be optimized by treating FPGAs as virtualizable resources and offering them multitasking capability. The solution to preempt a hardware task on an FPGA with the objective of context switching it has been in research for many years. The previous works mainly proposed the strategy to extract the context of a running task from the FPGA to provide the possibility of its resumption at a later time. The communication during the process, on the contrary, has not been receiving much attention.In this work, we study the communication management of a hardware task whileit is being context switched. This communication management is necessary to ensure the consistency in the communication of a task with context switch capability in a reconfigurable system. Otherwise, a hardware context switch can only be allowed under restrictive constraints which may lead to a considerable penalty in performance; context switching a task is possible after the communication flows finish and the input/output data have been consumed. Furthermore, certain techniques demand homogeneity in the platform for a hardware context switch can take place.We present a mechanism which preserves the communication consistency during ahardware context switch in a reconfigurable architecture. The input/output communication data are managed together with the task context to ensure their integrity. The overall management of the hardware task context and communication data follows a dedicated protocol developed for heterogeneous reconfigurable architectures. This protocol thus allows a hardware context switch to take place while the task still has ongoing communication flows on Reconfigurable System-on-Chips (RSoCs). From the experiments, we discover that the overhead due to managing the communication data becomes negligible since our mechanism provides the necessary high responsiveness for preemptive scheduling, besides the consistency in communication. Finally, the applications of the proposed solution are presented in a task migration prototyping and in a hypervisor-based system.

The majority of ATM switches that have been proposed only support unicast (point-to-point) connections. Those supporting multicast (point-to-multipoint) connections tend to perform poorly, with acceptable multicast performance only achievable using an excessive amount of hardware. Because of the growing importance of multicast traffic, there is the demand for multicast switch designs which offer both low hardware complexity and high performance. This research investigates a class of multicast ATM switches called recycling switches which can satisfy both requirements. Recycling switch performance is studied using a simulated network model. The major performance parameters measured are the loss rate, mean delay, and delay variance of cells crossing through the switch under uniform and bursty traffic patterns. The reason recycling is not more widely used in multicast switches is the perception that it can lead to some multicast cells receiving lower quality of service than others. This research demonstrates a new priority-based approach to designing recycling multicast ATM switches which addresses this problem while maintaining low complexity and excellent scalability. / Masters Thesis