Made available in DSpace on 2014-06-12T15:59:36Z (GMT). No. of bitstreams: 2 arquivo5342_1.pdf: 1635663 bytes, checksum: 8b17150a09a68bf3edb4a462d481c800 (MD5) license.txt: 1748 bytes, checksum: 8a4605be74aa9ea9d79846c1fba20a33 (MD5) Previous issue date: 2006 / A capacidade de reconfiguração tem se tornado uma característica de grande importância em projetos de sistema digitais completos em um único circuito integrado (System-on-Chips). A demanda por sistemas cada vez mais flexíveis e com grande poder computacional vem demonstrar o crescente interesse por esta área de pesquisa. Neste contexto, a computação reconfigurável vem oferecer um compromisso entre as vantagens do hardware de funcionalidade fixa, e a flexibilidade dos processadores programáveis por software [ADR1.2]. Porém, existe uma certa necessidade por ferramentas e metodologias de projeto que dêem o suporte necessário à construção de SoCs reconfiguráveis [BEN05], cujas aplicações são de extrema complexidade. Neste sentido, o projeto ADRIATIC [ADR1.2] [ADR2.1] [ADR2.2] propõe o desenvolvimento de uma metodologia de projeto de hardware/software co-design e co-verificação, em alto nível, para aplicações Wireless reais, procurando atenuar esta deficiência. De forma similar, o trabalho de pesquisa proposto visa o desenvolvimento de uma metodologia de projeto, em alto nível, que possibilite a implementação de projetos de SoCs, com módulos dinamicamente reconfiguráveis, utilizando a linguagem de descrição de sistemas, SystemC [SYS03] [SYS02], com o objetivo de construir um modelo executável para o sistema projetado

Technological advances are providing us with the capability to integrate more and more functionality into a single chip. This is leading to a new design paradigm, System On a Chip (SOC). In SOC designs all the functionality of a system is put inside a single chip, leading to increased performance, reduced power consumption, lower costs, and reduced size. SOC design brings with it new challenges and difficulties, however. The designs are now large, complicated and involve both software and hardware components. The designs have to be modeled at a high level of abstraction before partitioning into hardware and software components for final implementation. SystemC is a system level modeling language useful for System On a Chip design. It provides various features to perform system level modeling and simulation, which are missing in the generic HDL's such as VHDL and Verilog. The hardware portion of the SystemC models can be synthesized into hardware using commercial tools . The software portion can be rewritten as embedded software for the target processor. The aim of this thesis is to explore the SOC design process and to define methods for software synthesis of SystemC models. Software synthesis involves translation of SystemC models into code that is suitable for execution on an embedded processor. A simple scheduler that replaces the SystemC simulation kernel is proposed. This scheduler allows SystemC models to be executed directly as embedded software without the need for extensive modification or translation. Application of this process to the development of a GSM speech processing system, including the translation of part of the SystemC model into software that will execute on an embedded processor, is shown and the results are presented. / Master of Science

Concevoir un système embarqué implique de trouver un compromis algorithme/architecture en fonction des contraintes temps-réel. Thèse : pour un MPSoC et plus particulièrement avec les circuits reconfigurables qui permettent de modifier le support d'exécution en cours de fonctionnement, l'évaluation préalable des comportements fluctuants d'un système réactif devient une nécessité. Il faut donc valider par simulation (de haut niveau) tout en permettant l'exploration de l'espace de conception architectural, matériel et logiciel. Le point de vue du gestionnaire de la plateforme est choisi pour explorer à haut niveau les réactions du système aux choix de partitionnement et surtout l'influence de l'algorithmique des services du système d'exploitation et de leurs implémentations possibles. Pour cela un modèle de services d'OS modulaire permet de simuler fonctionnellement et conjointement, en SystemC, le matériel, les tâches logicielles et le système d'exploitation, répartis sur plusieurs nœuds d'exécution hétérogènes communicants. Le modèle a permis d'évaluer l'architecture temps-réel idéale d'une application dynamique de vision robotique conjointement à l'exploration des services de gestion de zone reconfigurable modélisé. Par ailleurs, ce modèle d'OS à été intégré dans un simulateur de MPSoC hétérogène d'une puissance estimé à un Tera opérations par seconde. / Designing an embedded system implies to look for the right algorithm/architecture compromise depending on the real-time constraints. For MPSoC an especially with reconfigurable devices which enable to modify the running executing support, the preliminary evaluation of the variable behaviors of a reactive system becomes necessary.This could be done by a high level simulation allowing to explore the architectural design space, hardware and software. The platform manager point of view is used to explore the systems reactions to the partitioning choices and also the influence of the various algorithms and the impact of implementations of the operating system's services refined in hardware or software. For that, a SystemC model composed of modular OS services allow to jointly and functionally simulate hardware, software tasks and the operating system, distributed on heterogeneous communicating execution nodes. To evaluate the perfect real-time reconfigurable architecture of a dynamical robot vision application, we explored its partitioning and the useful OS services accordingly. This model has been integrated in a big simulator of an heterogeneous chip designed to provide a Tera operations per second power.

Nos ambientes de desenvolvimento de sistemas integrados da atualidade, os requisitos dos sistemas devidos ao alto grau de funcionalidades incorporadas vêm-se incrementando, gerando uma alta complexidade nos projetos. Isto traz como consequência o aumento na quantidade de ciclos dentro do fluxo de projeto. Uma solução tem sido o uso de blocos IP para acelerar o desenvolvimento. Entretanto, para garantir um grau elevado de confiabilidade destes componentes, os processos de verificação devem comprovar que todas as propriedades do circuito estejam sendo cumpridas. Uma das técnicas utilizadas para isto é verificação funcional por simulação, que procura explorar, através da injeção de vetores de teste, a maior porção possível de todo o espaço de estados do circuito. Quanto maior o número de estados possíveis, maior o número de vetores de testes que devem ser inseridos. Portanto, o número de vetores de teste deve ser reduzido de forma considerável, entretanto, por este fato, métricas para determinar a completeza do processo de verificação, definidas como modelos de cobertura, têm sido necessárias. As métricas de cobertura são estabelecidas segundo as estratégias de observação do projeto sob verificação, DUV, sendo bastante comum na indústria a de caixa preta que tem como objetivo a estimulação das entradas e a observação dos eventos de saída do DUV. Neste caso, para determinar se o sistema cumpre com as especificações, o engenheiro de verificação, deve definir os eventos à saída que considera relevantes e as métricas para determinar a quantidade de vezes que devem ser observadas. Este tipo de modelagem é conhecido como cobertura por itens. A quantidade de itens e os eventos a serem observados podem ser dfinidos pelo conhecimento especialista, dos engenheiros de verificação ou, para simplificar esta tarefa, uma distribuição uniforme é adotada. Como estas formas de modelagem não abstraem todas as propriedades do circuito, o perfil da distribuição de valores dos eventos (parâmetros) escolhidos, em geral, não estão correlacionados com o perfil real verficado durante a execução dos testbenches , tendo como consequência o aumento dos tempos de simulação. Para tratar do problema acima, o presente trabalho tem como objetivo geral o desenvolvimento de uma metodologia para obter um modelo de cobertura de saída que apresente um perfil de distribuição semelhante ao real e que, assim, assista o engenheiro de verificação na seleção dos pontos ou intervalos de saída de interesse, adicionado-os às decisões derivadas de seu conhecimento especialista. Pela metodologia utilizada, encontra-se a(s) equação(ões) que define(m) a(s) saída(s) do circuito sob verificação e, a partir destas, a distribuição probabilística por evento observável. No centro da metodologia está a ferramenta PrOCov (Probabilistic Output Coverage), projetada com os objetivos acima. A metodologia e a ferramenta foram testadas com alguns exemplos de circuitos, modelos em alto nível do filtro FIR, do processador FFT e do filtro Elliptic, todos descritos em SystemC. Nos três casos testados, o PrOCov encontrou satisfatoriamente os respectivos perfis de saída. Estes foram comparados com os perfis obtidos por simulação, mostrando que uma excelente precisão pode ser obtida; apenas pequenas variações foram encontradas devidas a erros de aproximação. Também variações de precisão e tempo de simulação em função da resolução dos parâmetros de saída (eventos) foram analisadas nesta dissertação. / In current integrated system development environments, the requirements for the design of multi-function systems have increased constantly. Consequently, the number of iterations in the design flow has also grown. A solution for this problem has been the use of IP-cores to speed up the hardware development. However, to guarantee high level of reliability for these components, the verification process has to be kept strict in other to prove if the all system properties have been satisfied. The mainstream technique that has been used in the industry for the verification process is the dynamic functional verification. It aims to explore, by test vector injection, all the state space of the circuit. The higher the number of possible states, the higher the number of test vectors to be inserted. Therefore, the number of test vectors must be kept as low as possible. Due to that, completion and sufficiency metrics, identified as the coverage model, should be carefully defined. The coverage metrics are established according the observation strategies of the design under verification, DUV, where the black box approach is very common in the industry, being aimed at the stimulation of the inputs and observing the events of the DUV output. To determine whether the system meets the specifications, the verification engineer must define the events (s)he considers relevant at the output and the metrics used to determine the amount of times that the results must be observed. This type of modeling is known as item coverage. The amount of items and events to be observed may be defined by the experience of the engineer, but in most cases, to simplify this task, a uniform distribution is adopted. Those forms of modeling do not abstract the functionality of the circuit, then, the probability distribution of the chosen events is uncorrelated to the real simulated distribution, when the testbenchs are implemented. Therefore, the resulting simulation time increases. To solve the problem that is mentioned above, this work aims the development of a methodology to compute the output coverage, which should be similar to the real output value distribution and thus assist the engineer in the selection of the proper check points or output ranges of interest, by adding them to the decisions derived from his(her) knowledge. This methodology finds the equations that represent the outputs of the DUV and, from them, it computes the output probabilistic distribution. At the core of this methodology is the PrOCov (Probabilistic Output Coverage) tool, which was developed with the goals above. Both methodology and tool were tested with three circuits described in high level language, the FIR filter, FFT processor and Elliptic filter, written in SystemC. In all three cases, PrOCov presented a satisfactorily output distribution. Excellent precision could be achieved by the results, with only small variations found due to approximation errors. Also variations of accuracy and simulation time due to different resolutions of the output parameters (events) were analyzed in this dissertation.

Increasing the complexity of modern electronic systems leads to Electronic System Level (ESL) modeling concept, which supports hardware and software co-design and co-verification environment in a single framework. SystemC language, which is an IEEE approved electronic design standard for system design and verification processes, provides such an environment by supporting a wide range of abstraction levels from system-level to register-transfer level (RTL). In this thesis, two different models of a processor core, whose instruction set architecture (ISA) is compatible with 16-bit TI MSP430 microcontroller, are designed by employing the classical hardware modeling capability of the SystemC language. With its well-designed orthogonal instruction set, elegant addressing modes, useful constant generators and flexible von-Neumann architecture, 16-bit RISC-like processor of the MSP430 microcontroller is an ideal selection for the system-on-a-chip (SoC) designs. Instruction set and addressing modes of the designed processors are simulated thoroughly. In addition, original 16-bit and 32-bit cyclic redundancy code (CRC) programs are used in order to verify the processor cores. In this study, SystemC to hardware flow is also illustrated by synthesizing the Arithmetic and Logic Unit (ALU) part of the processor into a Xilinx-based hardware.

In this thesis, a direct digital synthesis (DDS) based function generator design module is presented, defined and implemented using two digital hardware modeling/design languages namely SystemC and VHDL. The simulation, synthesis and applicability performances of these two design languages are compared by following all digital hardware design stages. The advantages and open issues of SystemC based hardware design flow are emphasized in order to be a reference for future studies. SystemC initially appeared as a modeling language like HDL design languages. In the last years, SystemC gained popularity also as a hardware design language and it is expected to become alternative to traditional design languages. Using a single platform for hardware modeling, design and verification reduces the spent time and cost. The designed DDS function generator module supports standard I2C and UART communication protocols and it is in ready to use format for digital applications. In this thesis, the function generator module VHDL code is implemented into Xilinx FPGA and verified on the hardware platforms.

In this thesis, an 8-bit microcontroller, PIC 16F871, has been implemented using SystemC with classical hardware design methods. Analog modules of the microcontroller have been modeled behaviorally with SystemC-AMS which is the analog and mixed signal extensions for the SystemC. SystemC-AMS provides the capability to model non-digital modules and synchronization with the SystemC kernel. In this manner, electronic systems that have both digital and analog components can be described and simulated very effectively. The PIC 16F871 is a well known and very common microcontroller. Its architecture, peripheral modules and analog components makes this microcontroller pretty good model for a System on Chip (SoC) concept. Designed microcontroller&rsquo / s peripheral modules, instruction set and addressing modes have been verified utilizing the test codes. Besides, designed microcontroller has been tested with 16-bit CRC code. Moreover, a synchronous demodulator system that involves designed microcontroller and additional analog units has been constructed and simulated. Finally, SystemC to hardware flow has been demonstrated with implementation of arithmetic logic unit of the 16F871 into FPGA based hardware.

In this thesis, co-design and co-verification of a microcontroller hardware and software using SystemC is studied. For this purpose, an MC68HC11 microcontroller unit, a test bench that contains input and output modules for the verification of microcontroller unit are implemented using SystemC programming language and a visual simulation program is developed using C# programming language in Microsoft .NET platform. SystemC is a C++ class library that is used for co-designing hardware and software of a system. One of the advantages of using SystemC in system design is the ability to design each module of the system in different abstraction levels. In this thesis, test bench modules are designed in a high abstraction level and microcontroller hardware modules are designed in a lower abstraction level. At the end, a simulation platform that is used for co-simulation and co-verification of hardware and software modules of overall system is developed by combining microcontroller implementation, test bench modules, test software and visual simulation program. Simulations at different levels are performed on the system in the developed simulation platform. Simulation results helped observing errors in designed modules easily and making corrections until all results verified designed hardware modules. This stuation showed that co-designing and co-verifying hardware and software of a system helps finding errors and making corrections in early stages of system design cycle and so reducing design time of the system.

Die Simulation heterogener Systeme auf hoher Abstraktionsebene gewinnt auf Grund der zunehmenden Komplexität technischer Systeme stetig an Bedeutung. Unter heterogenen Systemen versteht man technische Systeme, die aus analoger und digitaler Elektronik, aus Komponenten verschiedener physikalischer Domänen wie mechanischen Strukturen, thermischen und optischen Komponenten sowie aus Software bestehen können. Genügte es bisher, die einzelnen Komponenten für sich in ihrer eigenen Domäne mit einem speziellen Simulator zu simulieren, so ist es heute unerläßlich, auch die Interaktionen zwischen den Komponenten zu erfassen. Um solche Systeme mit einer einheitlichen Beschreibungsform erfassen zu können, entstand aus der digitalen Hardwarebeschreibungssprache VHDL die Systembeschreibungssprache VHDL-AMS. Bei der Modellierung eines Systems muß das tatsächliche Verhalten der Komponenten abstrahiert werden, um mathematisch erfaßbar und in begrenzter Zeit simulierbar zu sein. Der Grad der Abstraktion beeinflußt jedoch die Genauigkeit der Simulationsergebnisse wesentlich. Dabei muß bzw. kann das Verhalten in unterschiedlichen Komponenten unterschiedlich stark abstrahiert werden, um noch akzeptable Simulationsgenauigkeiten erzielen zu können. VHDL-AMS erlaubt die Beschreibung von Komponenten auf unterschiedlichen Abstraktionsniveaus. Man kann die unterschiedlich abstrakten Modelle der Komponenten aber nur schwer in einer Systemsimulation gemeinsam simulieren, da unterschiedlich abstrakte Modelle auch unterschiedlich abstrakte Schnittstellen aufweisen, so daß die Modelle nur mühsam miteinander verbunden werden können. Ein Austausch eines abstrakten Modells einer Komponente gegen ein weniger abstraktes Modell oder umgekehrt ist mit vielen fehleranfälligen und zeitaufwendigen Anpassungsschritten verbunden. Im Rahmen dieser Arbeit wird ein methodischer Ansatz vorgestellt, der es auf der Basis einer Vereinheitlichung der Modellschnittstellen ermöglicht, unterschiedlich abstrakte Modelle gemeinsam zu simulieren und einzelne Modelle gegen abstraktere oder weniger abstrakte Modelle ohne nennenswerten Zeit- und Modellierungsaufwand auszutauschen. Es werden die zu verwendenden Interfaceobjekte und Datentypen für digitale, analoge elektrische und nichtelektrische Schnittstellen unter VHDL-AMS und SystemC-AMS vorgestellt. Ebenso werden Methoden vorgestellt, die digitales, ereignisdiskretes Verhalten auf konservative elektrische Schnittstellen bzw. nichtkonservatives analoges Verhalten auf digitale Schnittstellen abbilden. Weiterhin wird erläutert, wie sich digitale Protokolle über Abstraktionsebenen hinweg übertragen lassen und ein modifizierter Top-Down Design-Flow vorgestellt. Die Demonstration der Anwendbarkeit der Methode erfolgt anhand eines Beispiels.

Mikroelektronikos technologinėms galimybėms stipriai lenkiant projektavimo galimybes, projektavimo etapas reikalauja naujų metodų. Vienas iš problemos sprendimų būdų yra atkartojimo technologija. Pirmoje dalyje yra analizuojama literatūra. Apžvelgiamas atkartojimo technologijos objektas. Remiantis literatūra, pateikiamas platus ir siauras atkartojimo technologijos apibrėžimas. Pateikiami komponento apibrėžimai, komponento pakartotinio panaudojimo sąvokos ir metodai. Taip pat apžvelgiami mikroprocesoriai, mikroprocesorių architektūros. Antroje dalyje išanalizuojamas pateiktas mikroprocesorius, jo komponentai. Pasirenkama procesorinių komponentų bendrinimo kryptis. Taip pat analizuojamas procesoriaus instrukcijų rinkinys, bei galimybė bendrinti instrukcijų dekodavimo ir valdymo įrenginius. Trečioje dalyje, suformuluotiems uždaviniams pateikiami tyrimo rezultatai. Pateikiami procesoriaus komponentų bendrinimo bei sintezės rezultatai. Taip pat įvertinami instrukcijų dekodavimo ir valdymo įrenginių bendrinimo bei sintezės rezultatai. Ketvirtoje dalyje pateikiamos išvados bei rekomendacijos. / The design process requires new methods, because technological abilities of microelectronics overtake design possibilities. One way of the solution is a reuse technology. In the first chapter the analysis of literature has been made. Also the reuse technology object has been reviewed. According to literature the wide and narrow definitions of reuse technology are presented. Definitions of component, methods and concepts of generic components have been delivered. Overlook through the microprocessors and their architectures have been made. In the second chapter a microprocessor and its components are analysed. The directions of generalisation for microprocessor components are proposed. Also analysis of instruction set, instruction decoder and control units generalisation possibility is discussed. The third chapter provides generalisation results for formulated tasks. Results of generalisation and synthesis of processor components are presented. Also results of instruction decoder, control units generalisation and synthesis are delivered. Conclusions and recommendations are formulated in the fourth part.