Cette thèse se situe dans le contexte de la vérification fonctionnelle des circuits intégrés complexes. L’objectif de ce travail est de créer un flot de vérification conjoint au flot de conception basé sur une technique appelée "vérification basée sur les assertions(ABV)". Le concept de base du flot est le raffinement automatique des spécifications formelles données sous la forme d’assertions PSL du niveau TLM au niveau RTL. La principale difficulté est la disparité des deux domaines : au niveau TLM, les communications sont modélisées par des appels de fonctions atomiques. Au niveau RTL, les échanges sont assurés par des signaux binaires évoluant selon un protocole de communication précis. Sur la base d’un ensemble de règles de transformation temporelles formelles, nous avons réalisé un outil permettant d’automatiser le raffinement de ces spécifications. Comme le raffinement des modèles, le raffinement des assertions n’est pas entièrement automatisable : des informations temporelles et structurelles doivent être fournies par l’utilisateur. L’outil réalise la saisie de ces informations de façon ergonomique, puis procède automatiquement à la transformation temporelle et structurelle de l’assertion. Il permet la génération d’assertions RTL mais aussi hybrides. Les travaux antérieurs dans ce domaine sont peu nombreux et les solutions proposées imposent de fortes restrictions sur les assertions considérées. À notre connaissance, le prototype que nous avons mis en oeuvre est le premier outil qui réalise un raffinement temporel fondé sur la sémantique formelle d’un langage de spécification standard (PSL). / The context of this thesis is the functional verification of complex integrated circuits.The objective of our work is to create a seamless verification flow joint to the design flowand based on a proved technique called Assertions-Based Verification (ABV). The mainchallenge of TLM to RTL refinement is the disparity of these two domains : at TLM,communications are modeled as atomic function calls handling all the exchanged data.At RTL, communications are performed by signals according to a specific communicationprotocol. The proposed temporal transformation process is based on a set of formaltransformation rules. We have developed a tool performing the automatic refinement ofPSL specifications. As for design refinement assertion refinement is not fully automated.Temporal and structural information must be provided by the user, using an ergonomicinterface. The tool allows the generation of assertions in RTL but also hybrid assertions.Little work has been done before in this area, and the proposed solutions suffer from severerestrictions. To our knowledge, our prototype is the first tool that performs a temporaltransformation of assertions based on the formal semantics of a standard specificationlanguage (PSL).

Le marché de l’Internet des Objets (IdO) est en pleine progression. Il va continuer à croître et à se développer à un rythme soutenu dans les prochaines années. Les objets connectés sont constitués de composants électroniques dédiés, de processeurs et de codes logiciels. La conception de tels systèmes constitue aujourd’hui un challenge au niveau industriel. Ce challenge est renforcé par la concurrence du marché et le délai de commercialisation qui impactent directement sur le développement d’un système. Le processus de conception actuel consiste en l’élaboration d’un cahier des charges. Dans un premier temps, l’équipe en charge du développement matériel commence à développer le produit. Ensuite, la partie applicative peut être mise au point par les développeurs logiciels. Une fois le premier prototype matériel disponible, l’équipe logicielle peut alors intégrer sa partie et tenter de la valider fonctionnellement. Cette étape peut mettre en lumière des défauts dans le logiciel mais aussi lors de la conception matérielle. Malheureusement,la découverte ce type d’erreurs intervient beaucoup trop tard dans le processus de conception retardant la commercialisation du système. Afin de sécuriser au plus tôt les développements matériel et logiciel, des méthodologies basées sur le standard SystemC/Transaction Level Modeling (TLM) ont été proposées. Elles permettent de modéliser et de simuler du matériel. Durant les phases amont de conception d’un système, elles permettent de mettre en commun une version virtuelle du (futur) système entre les équipes logicielle et matérielle. Cette version virtuelle est plus couramment appelée plateforme virtuelle. Elle permet de tester et de valider le plus tôt possible lors du cycle de conception, de réduire le coût matériel en limitant la fabrication de prototypes, mais aussi de gagner du temps et donc de l’argent en diminuant les risques. Or, les objets intègrent de plus en plus de fonctionnalités aux niveaux matériel et logiciel. Les besoins ayant évolué, le standard de simulation SystemC/TLM ne répond plus à l’heure actuelle à toutes les attentes. Ces attentes concernent plus particulièrement les aspects liés à la simulation de systèmes composés de nombreuses fonctionnalités, de protocoles de communication disparates mais aussi de modèles complexes et consommateur de temps pendant la simulation. Des activités de recherche ont déjà été menées sur ces sujets. Cependant, elles ont pour la plupart abouti à des solutions qui ne sont pas interopérables. Les solutions existantes ne permettent donc pas de bénéficier de la réutilisation des modèles de la littérature. Afin de répondre à ces problèmes,une solution permettant la configuration de modèles SystemC/TLM a été recherchée. Cette dernière fait désormais partie du standard Configuration, Control and Inspection (CCI). Dans un second temps, la modélisation de protocoles de communication à un haut niveau d’abstraction(TLM Loosely Timed (LT) et Approximately Timed (AT)) a été étudiée, et plus précisément des protocoles de type non bus. Une évolution du standard actuel permettant d’améliorer le support,l’interopérabilité, la réutilisation a été proposée dans le cadre de la thèse. Ensuite, une évolution du standard SystemC et plus précisément du comportement du noyau de simulation a été étudiée pour supporter l’attente d’événements asynchrones. Ce type d’événement ouvre la voie à la parallélisation et la distribution de modèles sur différents threads / machines. Enfin, une solution permettant l’intégration de modèles de Central Processing Units (CPU) intégrés dans QuickEMUlator (QEMU), un émulateur / virtualisateur de système, a été étudiée. Finalement, toutes ces contributions ont été associées à travers la modélisation d’un ensemble d’objets connectés à une passerelle. / The market for Internet Of Things (IOT) is on the rise. It is predicted to continue to grow at a sustained pace in the coming years. Connected objects are composed of dedicated electronic components, processors and software. The design of such systems is today a challenge from an industrial point of view. This challenge is reinforced by market competition and time tomarket that directly impact the success of a system. In a current design process involvesthe development of a specification. Initially, the team in charge of hardware development beginsto design the system. Second, the application part can be done by software developers. Oncethe first hardware prototype is available, the software team can then integrate their part and try tovalidate the functionality. This step may reveal defects in the software but also in the hardware architecture. Unfortunately, the discovery of these errors occurs far too late in the design process,could impacts the marketing of the system and potentially its success. In order to ensure that the hardware and software designs will work together as early as possible, methodologies based onthe SystemC / Transaction Level Modeling (TLM) standard have been widely adopted. They involvethe modelling and simulation of the proposed hardware architectures. During the initial phasesof a product’s design, they enable the software and hardware team to share a virtual version ofthe (future) system. This virtual version is more commonly referred to as a virtual platform. It facilitates early software development, test and validation; reduces material cost by limiting the number of prototypes; saves time and money by reducing risks. However, connected objects are increasingly incorporating hardware and software features. As the requirements have evolved, theSystemC / TLM simulation standard no longer meets all expectations. It includes aspects related to the simulation of systems composed of many functionality, disparate communication protocolsbut also complex and time consuming models during the simulation. Some works have already been carried out on these subjects. However, as the number of components increases, all formsof interoperability of models and tools become increasingly difficult to handle. Moreover, mostof the research has resulted in solutions that are not inter-operable and can not reuse existingmodels. To solve these problems, this thesis proposes a solution for configuring SystemC / TLMmodels. It is now part of the standard Configuration, Control and Inspection (CCI). In a secondstep, the modeling of high-level abstraction communication protocols (TLM Loosely Timed (LT)and Approximately Timed (AT)) has been studied, as it relates to non-bus protocols. An evolution of the standard to improve support, interoperability and reuse is also proposed. In a third step,a change of the SystemC standard and more precisely of the behavior of the simulation kernelhas been studied to support asynchronous events. These open the way to parallelization and distribution of models on different threads / machines. In a fourth step, a solution to integrate Central Processing Units (CPU) models integrated in Quick EMUlator (QEMU), a system emulator/ virtualizer, has been studied. Finally, all these contributions have been applied in the modeling ofa set of objects connected to a gateway.

Orientadores: Sandro Rigo, Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-17T16:52:44Z (GMT). No. of bitstreams: 1 Faveri_RodrigoRichardCantos_M.pdf: 2472151 bytes, checksum: 93bf01477c1e5bef38efd314232f9a69 (MD5) Previous issue date: 2010 / Resumo: SystemC é uma linguagem de desenvolvimento de sistemas de hardware como, por exemplo, os modelos arquiteturais SoC (Systems-on-Chip) e, em conjunto com a biblioteca e metodologia TLM (Transacüon Levei Modeling), oferece a infraestrutura de simulação necessária capaz de realizar a simulação de software e hardware rapidamente em um alto nível de abstração. O seu núcleo de simulação foi construído como uma cadeia de threads, que são executadas uma por vez. Sendo assim, essa modelagem do núcleo de simulação do SystemC não é capaz de se beneficiar dos recursos oferecidos pelos novos processadores com mais de um núcleo de processamento, para obter ganhos de desempenho de simulação. Com o aumento da complexidade dos projetos de circuitos eletrônicos e a diminuição dos prazos para que um produto de SoC se torne comercial, o desempenho das simulações se tornou essencial. No presente trabalho, apresenta uma nova versão do SystemC capaz de executar em processadores multinúcleos com ganhos de desempenho de 2,üx à 22,029x à versão original em máquinas de 4 e 12 núcleos de processamento simulando plataformas contendo de 4 a 64 threads. Além disso, também foram realizadas mudanças nas interfaces TLM, para que a sincronização dos processos paralelos seja independente dos eventos hoje presentes no SystemC e, devido às alterações no núcleo de simulação do SystemC, a linguagem de descrição de arquitetura ArchC também foi adaptada para conseguir executar em um ambiente paralelo de simulação / Abstract: SystemC is a modeling language for development of hardware systems, such SoCs (Systems-on-Chip) architectural models, and integrated with the methodology and library TLM (Transaction Level Modeling), it offers the required simulation platform infrastructure capable to simulate software and hardware in a fast way at different abstration levels. However, its single thread simulation kernel prevents it from utilizing the potential computing power of multi-core machines to speed up the simulation. With the complexity and the functionality of new circuits and applications size increasing and the time-to-market becoming shorter, the simulation speed-up is essential. In the present work, we introduce a new SystemC version, able to perform in multi-core machines and, consequently, with performance gains of 2.Ox to 22.029x to the original version on machines with 4 and 12 cores simulating platforms with 4 to 64 threads. Furthermore, changes were made on the TLM interfaces for parallel process can synchronize independently of SystemC events, and because the changes in the SystemC simulation kernel, Archc also had to be adapted for execute in a parallel simulation environment / Mestrado / Mestre em Ciência da Computação

Orientadores: Sandro Rigo, Guido Costa Souza de Araujo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-13T11:44:55Z (GMT). No. of bitstreams: 1 Costa_RichardMaciel_M.pdf: 4274440 bytes, checksum: 4094fea059358a9a5eb39c56aa5f1f3c (MD5) Previous issue date: 2008 / Resumo: Em um passado recente os sistemas eram constituídos de partes discretas tais como microprocessadores, memórias e Application Specific Integrated Circuits (ASICs). Essa separação clara e simples tornava possível a especificação ser feita por uns poucos projetistas utilizando uma abordagem top-down: a partir de um modelo comportamental ou Register-Transfer Level (descritos em VHDL, por exemplo), progressivamente refinando o modelo ate o nível Transistor-to-Transistor. Entretanto, o avanço contínuo do processo de miniaturização de transistores possibilitou a criação de sistemas completos integrados em um único chip (também chamados de System-on-chip). Dado que esses sistemas s~ao tipicamente constituídos por diversos componentes complexos, um nível mais alto de abstração - o de sistema - foi criado, juntamente com suas linguagens associadas (como a linguagem SystemC), para facilitar o trabalho dos projetistas. As linguagens utilizadas para modelar no nível de sistema são diferentes das linguagens utilizadas para modelar nos níveis comportamental e Register-Transfer. Assim, surge o problema de como co-verificar componentes descritos em diferentes níveis de abstração; característica desejável para projetos de grande porte, já que fornece uma garantia de interoperabilidade entre os componentes no sistema final. Este trabalho, então, apresenta uma metodologia para resolver o problema de co-simulação entre a linguagem de descrição de hardware VHDL e a linguagem de descrição de sistema SystemC através do uso da Verilog Procedural Interface (VPI). Alem da metodologia em si, descreve-se o trabalho no sentido de criar um arcabouço para validar a metodologia e testes comparativos entre a implementação feita e uma ferramenta comercial popular. / Abstract: In a recent past, systems were mostly constituted by well-separated parts such as microprocessors, memories and Application Specific Integrated Circuits (ASICs). That simple and clear organization allowed entire systems to be designed by only a few designers through a top-down approach: from the behavioral or register transfer model (using VHDL, for instance) advancing to the transistor-to-transistor level. However, the continuous advance of the process of shrinking transistors made it possible to create entire systems integrated in a single die (called System-on-chip). Because these systems are usually constituted by many complex components, a higher abstraction level - the system level - was created, together with the associated languages, to ease the work of the designers. The languages used to model on the system level are diferent from the languages used to model on the behavioral and register-transfer levels. Therefore, the problem of how to co-verify components written in diferent abstraction levels arises; this co-verification is desirable for big projects, since it provides a way to check if the components of the target system are working together. This project presents a methodology to solve the co-simulation problem between the hardware description language VHDL and the system description languagem SystemC through the use of the Verilog Procedural Interface (VPI). We describe the methodology and also describe the framework used to validate the methodology and comparative tests between this framework and a well-known comercial tool. / Mestrado / Arquitetura de Computadores / Mestre em Ciência da Computação

Nos ambientes de desenvolvimento de sistemas integrados da atualidade, os requisitos dos sistemas devidos ao alto grau de funcionalidades incorporadas vêm-se incrementando, gerando uma alta complexidade nos projetos. Isto traz como consequência o aumento na quantidade de ciclos dentro do fluxo de projeto. Uma solução tem sido o uso de blocos IP para acelerar o desenvolvimento. Entretanto, para garantir um grau elevado de confiabilidade destes componentes, os processos de verificação devem comprovar que todas as propriedades do circuito estejam sendo cumpridas. Uma das técnicas utilizadas para isto é verificação funcional por simulação, que procura explorar, através da injeção de vetores de teste, a maior porção possível de todo o espaço de estados do circuito. Quanto maior o número de estados possíveis, maior o número de vetores de testes que devem ser inseridos. Portanto, o número de vetores de teste deve ser reduzido de forma considerável, entretanto, por este fato, métricas para determinar a completeza do processo de verificação, definidas como modelos de cobertura, têm sido necessárias. As métricas de cobertura são estabelecidas segundo as estratégias de observação do projeto sob verificação, DUV, sendo bastante comum na indústria a de caixa preta que tem como objetivo a estimulação das entradas e a observação dos eventos de saída do DUV. Neste caso, para determinar se o sistema cumpre com as especificações, o engenheiro de verificação, deve definir os eventos à saída que considera relevantes e as métricas para determinar a quantidade de vezes que devem ser observadas. Este tipo de modelagem é conhecido como cobertura por itens. A quantidade de itens e os eventos a serem observados podem ser dfinidos pelo conhecimento especialista, dos engenheiros de verificação ou, para simplificar esta tarefa, uma distribuição uniforme é adotada. Como estas formas de modelagem não abstraem todas as propriedades do circuito, o perfil da distribuição de valores dos eventos (parâmetros) escolhidos, em geral, não estão correlacionados com o perfil real verficado durante a execução dos testbenches , tendo como consequência o aumento dos tempos de simulação. Para tratar do problema acima, o presente trabalho tem como objetivo geral o desenvolvimento de uma metodologia para obter um modelo de cobertura de saída que apresente um perfil de distribuição semelhante ao real e que, assim, assista o engenheiro de verificação na seleção dos pontos ou intervalos de saída de interesse, adicionado-os às decisões derivadas de seu conhecimento especialista. Pela metodologia utilizada, encontra-se a(s) equação(ões) que define(m) a(s) saída(s) do circuito sob verificação e, a partir destas, a distribuição probabilística por evento observável. No centro da metodologia está a ferramenta PrOCov (Probabilistic Output Coverage), projetada com os objetivos acima. A metodologia e a ferramenta foram testadas com alguns exemplos de circuitos, modelos em alto nível do filtro FIR, do processador FFT e do filtro Elliptic, todos descritos em SystemC. Nos três casos testados, o PrOCov encontrou satisfatoriamente os respectivos perfis de saída. Estes foram comparados com os perfis obtidos por simulação, mostrando que uma excelente precisão pode ser obtida; apenas pequenas variações foram encontradas devidas a erros de aproximação. Também variações de precisão e tempo de simulação em função da resolução dos parâmetros de saída (eventos) foram analisadas nesta dissertação. / In current integrated system development environments, the requirements for the design of multi-function systems have increased constantly. Consequently, the number of iterations in the design flow has also grown. A solution for this problem has been the use of IP-cores to speed up the hardware development. However, to guarantee high level of reliability for these components, the verification process has to be kept strict in other to prove if the all system properties have been satisfied. The mainstream technique that has been used in the industry for the verification process is the dynamic functional verification. It aims to explore, by test vector injection, all the state space of the circuit. The higher the number of possible states, the higher the number of test vectors to be inserted. Therefore, the number of test vectors must be kept as low as possible. Due to that, completion and sufficiency metrics, identified as the coverage model, should be carefully defined. The coverage metrics are established according the observation strategies of the design under verification, DUV, where the black box approach is very common in the industry, being aimed at the stimulation of the inputs and observing the events of the DUV output. To determine whether the system meets the specifications, the verification engineer must define the events (s)he considers relevant at the output and the metrics used to determine the amount of times that the results must be observed. This type of modeling is known as item coverage. The amount of items and events to be observed may be defined by the experience of the engineer, but in most cases, to simplify this task, a uniform distribution is adopted. Those forms of modeling do not abstract the functionality of the circuit, then, the probability distribution of the chosen events is uncorrelated to the real simulated distribution, when the testbenchs are implemented. Therefore, the resulting simulation time increases. To solve the problem that is mentioned above, this work aims the development of a methodology to compute the output coverage, which should be similar to the real output value distribution and thus assist the engineer in the selection of the proper check points or output ranges of interest, by adding them to the decisions derived from his(her) knowledge. This methodology finds the equations that represent the outputs of the DUV and, from them, it computes the output probabilistic distribution. At the core of this methodology is the PrOCov (Probabilistic Output Coverage) tool, which was developed with the goals above. Both methodology and tool were tested with three circuits described in high level language, the FIR filter, FFT processor and Elliptic filter, written in SystemC. In all three cases, PrOCov presented a satisfactorily output distribution. Excellent precision could be achieved by the results, with only small variations found due to approximation errors. Also variations of accuracy and simulation time due to different resolutions of the output parameters (events) were analyzed in this dissertation.

L'évolution des systèmes embarqués se traduit aujourd'hui par des ensembles complexes, dits systèmes cyber-physiques, opérant principalement en réseau et interagissant fortement avec leur environnement.Intégrés à des circuits de contrôle et de traitement du signal, les micro-systèmes électromécaniques, ou MEMS, jouent un rôle primordial dans ces ensembles en tant que capteurs ou actionneurs.La conception de tels systèmes requiert des solutions globales et pluri-disciplinaires telles que le prototypage virtuel.Basée sur des modèles haut-niveau, cette technique permet d'anticiper le comportement du système dès les premières phases de conception et de le raffiner lors de phases plus avancées.Ces méthodes ont progressivement été appliquées à la conception de circuits intégrés, notamment avec l'utilisation de langages de description matérielle, tels que VHDL ou Verilog.En adoptant un niveau d'abstraction supérieur, SystemC a largement contribué au développement concourant des parties matérielles et logicielles.Parallèlement, les extensions proposées dans SystemC-AMS répondent au nombre croissant de composants analogiques dans les circuits intégrés et constituent une base prometteuse pour le prototypage virtuel de systèmes hétérogènes.Pour cette raison, cette thèse traite de la modélisation et de la simulation haut-niveau de dispositifs MEMS en SystemC-AMS.Dans un premier temps, nous évaluons les capacités actuelles du standard et des modèles de calcul proposés dans SystemC-AMS.Nous démontrons les limites et la difficulté d'élaborer des modèles équivalents de dispositifs MEMS dont la géométrie et les couplages internes nécessitent des descriptions plus détaillées.Nous proposons donc, dans un deuxième temps, d'intégrer directement dans SystemC-AMS des modèles réduits de dispositifs MEMS.La réduction d'ordre de modèle est une méthode mathématique permettant de créer des représentations compactes de systèmes initialement très larges en termes de degrés de liberté.Ainsi, nous utilisons les modèles générés depuis l'outil d'analyse en éléments finis \emph{MEMS+} et proposons une interface de programmation pour les insérer dans des modèles SystemC-AMS.Après avoir détaillé les principales fonctionnalités de l'interface, nous discutons les améliorations possibles du standard et de la solution présentée.Enfin, nous vérifions notre solution avec l'étude d'un accéléromètre et comparons les résultats avec l'état de l'art en termes de précision des modèles et de performances de simulation.Cette thèse propose ainsi une méthodologie complète pour intégrer des dispositifs MEMS dans un environnement de simulation haut-niveau. / Embedded systems have evolved to more complex assemblies, called Cyber-Physical Systems (CPS), mostly operating through networks and tightly interacting with the environment.As actuators or sensors, micro-electromechanical systems (MEMS) are essential elements in these systems where they are integrated along with control and signal processing units.Designing such solutions requires a multi-domain approach like virtual prototyping.Based on system-level models, this technique allows to anticipate the global behavior in early-design phases and to further refine it in more advanced steps.Integrated circuits were progressively designed with respect to this method, especially through Hardware Description Languages (HDLs) like VHDL or Verilog.By adopting a higher-abstraction degree, SystemC enabled the co-development of hardware/software specific applications.In parallel, the Analog and Mixed-Signal (AMS) extensions proposed in SystemC-AMS partly addressed the increasing amount of analog components and are considered as a promising alternative for the virtual prototyping of heterogeneous systems.To that end, this thesis addresses the system-level modeling and simulation of MEMS devices in SystemC-AMS.First, we evaluate the current capabilities of the standard and supported models of computation in SystemC-AMS.We demonstrate the limitations and the the difficulty to elaborate equivalent models of MEMS devices whose geometry and internal coupling require more detailed descriptions.Second, we propose to directly integrate MEMS reduced models in SystemC-AMS.Model-order reduction is a mathematical technique to decrease the number of degrees of freedom and generate compact models from large-scale systems.We thus integrate the reduced models exported from the finite-element analysis tool \emph{MEMS+} and propose an Application Programmable Interface (API) to insert these \textit{ad hoc} models in SystemC-AMS.After reviewing the main API features, we discuss some improvements of both the standard and the presented solution.Finally, we verify our solution through the use case of an accelerometer and compare the results with the state of the art in terms of modeling accuracy and simulation performance.This thesis introduces a framework to integrate MEMS devices with the surrounding electronics in a unified system-level simulation environment.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

Mémoire numérisé par la Direction des bibliothèques de l'Université de Montréal.

La simulation des systèmes embarqués multiprocesseurs (MPSoC), dés les premières phases de conception, joue un rôle primordial puisqu'elle permet de réduire le temps d'arrivée sur le marché du produit final. Néanmoins, comme ces MPSoC deviennent de plus en plus complexes et hétérogènes, les méthodes conventionnelles de simulation de bas niveau ne sont plus adéquates. La solution proposée à travers cette thèse est l'intégration dans un seul environnement de plusieurs niveaux de simulation. Ceci permet l'évaluation des performances à un niveau précoce dans le flot de conception. L'environnement est utile dans l'exploration de l'espace des solutions architecturales et permet de converger rapidement vers le couple Architecture/Application le plus adéquat. Dans la première partie de cette thèse, nous présentons un outil de simulation performant et qui offre, à travers les trois niveaux qui le composent, différents compromis entre la vitesse de simulation et la précision de l'estimation des performances. Ces trois niveaux se différencient par les détails de l'architecture nécessaires à chacun et se basent sur le standard SystemC-TLM. Dans la deuxième étape, nous nous sommes intéressés à la consommation d'énergie dans les MPSoc. Pour cela, nous avons enrichi notre environnement de simulation par des modèles de consommation d'énergie flexibles et précis. Enfin dans la troisième étape de notre thèse, une chaîne de compilation basée sur la méthodologie Ingénierie Dirigée par les Modèles (!DM) est développée et intégrée à l'environnement Gaspard. Cette chaîne permet la génération automatique du code SystemC à partir d'une modélisation de haut niveau d'un MPSoc. / Multiprocessor system on chip (MPSoC) simulation in the first design steps has an important impact in reducing the time to market of the final product. However, MPSoC have become more and more complex and heterogeneous. Consequently, traditional approaches for system simulation at lower levels cannot adequately Support the complexity needed for the design of future MPSoc. ln this thesis, we propose a framework composed of several simulation levels. This enables early performance evaluation in the design flow. The proposed framework is useful for design space exploration and permits to find rapidly the most adequate Architecture/Application configuration. ln the first part ofthis thesis, we present an efficient simulation tool composed of three levels that offer several performance/energy tradeoffs. The three levels are differentiated by the accuracy of architectural descriptions based on the SystemC- TLM standard. ln the second part, we are interested by the MPSoC energy consumption. For this, we enhanced Our simulation framework with flexible and accurate energy consumption models. FinaIly in the third part, a compilation chain based on a Model Driven Engineering (MDE) approach is developed and integrated in the Gaspard environment. This chain allows automatic SystemC code generation from high level MPSoC modeling.

FlexRay, developed by a consortium of over hundred automotive companies, is a real-time in-vehicle communication protocol for automotive networks. It is being used as a higher-performance, time-triggered, and deterministic serial bus in automobiles for many safety-critical and x-by-wire systems. In x-by-wire systems the hydraulic parts of systems such as steering and braking are replaced with electronics. As x-by-wire systems are safety-critical, they must be fault-tolerant, deterministic, and should have synchronized time base (global time). FlexRay fulfils all these requirements as it is a deterministic and fault-tolerant serial bus system with data rates of 10 Mbps for extremely safety- and time-critical applications. As, FlexRay has become the de-facto standard for high speed safety-critical communications in automotive domain, and timing analysis of FlexRay still continues to generate significant research interest. The FlexRay allows both time-triggered and event-triggered messages. The static (ST) segment allows time-triggered transmission, while dynamic (DYN) segment allows event-triggered transmission. As the DYN segment transmits messages based on their priorities; so the delay suffered by a message depends on the interferences by its higher priority messages. Computing interferences of the higher priority messages is a challenging problem for the DYN segment of FlexRay [32]. So, in order to compute interferences of the higher priority messages one way is to use simulation technique. The SystemC simulator proposed in this thesis is used to model and simulate the behaviour of the DYN segment of the FlexRay protocol. This modelling and simulation is done on system level using the system description language SystemC. The simulator estimates the delay suffered by a message instances because of the interferences of higher priority messages. This estimation of delay is done by taking no-jitter/jitter into consideration. Finally, in both the cases the delay suffered by each and every message instance is plotted.