Energy consumption will reduce the battery life time and increase the weight and cost of mobile devices. Low-power design methods become an important issue of SOC. Until now, there is no commercial power estimates software in system-level. Users must add power estimation to SystemC simulation environment by themselves. In this paper, we proposed a system-level power estimation framework. Users can use their custom power model, and add power estimation automatically. The proposed framework separates the SystemC simulation environment and power estimation into two independent procedures. First, we generate a data collection SystemC module automatically based on the parameters set up by users. This data collection module will automatically collect the information of parameters from SystemC simulation environment, and send these information to power estimation program. Power estimation program will calculate power consumption according to these parameters and formulas set by user. Users can add power estimation to their SystemC simulation environment quickly and use our framework to analysis the power consumption of their SOC system to find improvement issues. Users can use of our framework to compare and analyze various low-power design methods. In this paper, we applied our framework to estimate the power consumption of a 3D graphics SOC to authenticate the functional and practical ability of our framework.

The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means that it needs more power consumption. Therefore, the essential issue that we are facing now is to reduce the power consumption in order to fit the capacity of the batteries. In the current system level design, there is no presentable commercial tool for designers to estimate the power consumption of the system. This thesis proposes a framework for system level power estimation, which allows the users to add the power models of these modules developed by them in the system level. Moreover, the power models of CPU, memory and bus are also provided. Besides the power models and convenient method to modify these models, a power management unit is also provided. With this unit, the designers can use different power management policies to manage the system¡¦s power consumption and decide its power efficiency. In this thesis, the framework is constructed under the environment of SystemC, so the users can alternate the power model and power management policy rapidly. By using this framework, the designers can more conveniently and rapidly estimate the system¡¦s power consumption and improve the system¡¦s architecture. Therefore, it can fast examine the advantages and disadvantages of various power models and power management policies.

Les densités d'intégration actuelles des circuits intégrés permettent de disposer de SoC (systèmes sur puce) de plus en plus complexes, intégrant de plus en plus de standards. Par conséquent, le problème des interconnexions entre tous les blocs IP (Intellectual Property) constituant le SoC devient un point critique que les structures de communications actuelles ne parviennent plus à solutionner.<br />Ces problèmes sont notamment liés aux besoins de plus en plus forts en mobilité et en débit dans les architectures de communication actuelles et futures. Ainsi, les solutions à base de NoC (Network on Chip) offrent de bonnes perspectives en terme de bande passante et de flexibilité pour pallier notamment aux limites actuelles des topologies bus. Les travaux de thèse présentés ici portent sur la méthodologie de modélisation et d'exploration d'architectures de réseaux sur puce appliquée aux télécommunications.<br />Le contexte radio-télécommunications étudié est celui proposé dans le cadre du projet Européen 4MORE pour lequel nous avons contribué. Une des contraintes de ce projet était d'intégrer dans un SoC la technique MC-CDMA (Multiple Carrier Code Division Multiple Access) combinant la technique MIMO en utilisant un média de communication innovant.<br />Ainsi, nous avons contribué à cette intégration en proposant une méthodologie de conception permettant d'aider le concepteur dans le choix des différents paramètres caractérisant le NoC pour satisfaire les contraintes temps réel de l'application spécifiées dans le cahier des charges.<br />Ces travaux de thèse ont porté sur la modélisation et l'interconnexion des composants IP constituant la chaîne algorithmique du projet 4MORE afin de les intégrer dans un modèle SystemC du NoC. Par ailleurs, les choix de dimensionnement du réseau et des contraintes de placement des blocs IP sur celui-ci ont un impact important sur les performances globales de l'application. Nous avons mis en place un outil AAA (Adéquation Algorithme Architecture) permettant de réaliser l'adéquation des contraintes de l'application sur l'architecture en minimisant les chemins de communication tout en veillant à ne pas violer les bandes passantes théoriques des liens de communication entre routeurs.<br />Le flot de conception mis en œuvre permet au concepteur de générer le modèle SystemC du NoC et permettra à cours terme de générer le code VHDL associé du modèle SystemC simulé afin d'accélérer les phases de simulation et de donner la possibilité de valider logiciellement et matériellement (cible FPGA) l'architecture avec son application.

Functional verification is a critical part in the hardware design process cycle, and it contributes for nearly two-thirds of the overall development time. With increasing complexity of hardware designs and shrinking time-to-market constraints, the time and resources spent on functional verification has increased considerably. To mitigate the increasing cost of functional verification, research and academia have been engaged in proposing techniques for improving the simulation of hardware designs, which is a key technique used in the functional verification process. However, the proposed techniques for accelerating the simulation of hardware designs do not leverage the performance benefits offered by multiprocessors/multi-core and heterogeneous processors available today. With the growing ubiquity of powerful heterogeneous computing systems, which integrate multi-processor/multi-core systems with heterogeneous processors such as GPUs, it is important to utilize these computing systems to address the functional verification bottleneck. In this thesis, I propose a technique for accelerating SystemC simulations across multi-core CPUs and GPUs. In particular, I focus on accelerating simulation of SystemC models that are described at both the Register-Transfer Level (RTL) and Transaction Level (TL) abstractions. The main contributions of this thesis are: 1.) a methodology for accelerating the simulation of mixed abstraction SystemC models defined at the RTL and TL abstractions on multi-core CPUs and GPUs and 2.) An open-source static framework for parsing, analyzing, and performing source-to-source translation of identified portions of a SystemC model for execution on multi-core CPUs and GPUs.

Zugl.: Tübingen, Univ., Diss., 2008

Zugl.: Chemnitz, Techn. Univ., Diss., 2010

Les systèmes sur puces intègrent aujourd’hui sur le même substrat des parties analogiques et des unités de traitement numérique. Tandis que la complexité de ces systèmes s’accroissait, leur temps de mise sur le marché se réduisait. Une conception descendante globale et coordonnée du système est devenue indispensable de façon à tenir compte des interactions entre les parties analogiques et les partis numériques dès le début du développement. Dans le but de répondre à ce besoin, cette thèse expose un processus de raffinement progressif et méthodique des parties analogiques, comparable à ce qui existe pour le raffinement des parties numériques. L'attention a été plus particulièrement portée sur la définition des niveaux analogiques les plus abstraits et à la mise en correspondance des niveaux d’abstraction entre parties analogiques et numériques. La cohérence du raffinement analogique exige de détecter le niveau d’abstraction à partir duquel l’utilisation d’un modèle trop idéalisé conduit à des comportements irréalistes et par conséquent d’identifier l’étape du raffinement à partir de laquelle les limitations et les non linéarités aux conséquences les plus fortes sur le comportement doivent être introduites. Cette étape peut être d’un niveau d'abstraction élevé. Le choix du style de modélisation le mieux adapté à chaque niveau d'abstraction est crucial pour atteindre le meilleur compromis entre vitesse de simulation et précision. Les styles de modélisations possibles à chaque niveau ont été examinés de façon à évaluer leur impact sur la simulation. Les différents modèles de calcul de SystemC-AMS ont été catégorisés dans cet objectif. Les temps de simulation obtenus avec SystemC-AMS ont été comparés avec Matlab Simulink. L'interface entre les modèles issus de l'exploration d'architecture, encore assez abstraits, et les modèles plus fin requis pour l'implémentation, est une question qui reste entière. Une bibliothèque de composants électroniques complexes décrits en SystemC-AMS avec le modèle de calcul le plus précis (modélisation ELN) pourrait être une voie pour réussir une telle interface. Afin d’illustrer ce que pourrait être un élément d’une telle bibliothèque et ainsi démontrer la faisabilité du concept, un modèle d'amplificateur opérationnel a été élaboré de façon à être suffisamment détaillé pour prendre en compte la saturation de la tension de sortie et la vitesse de balayage finie, tout en gardant un niveau d'abstraction suffisamment élevé pour rester indépendant de toute hypothèse sur la structure interne de l'amplificateur ou la technologie à employer. / Systems on Chip (SoC) embed in the same chip analogue parts and digital processing units. While their complexity is ever increasing, their time to market is becoming shorter. A global and coordinated top-down design approach of the whole system is becoming crucial in order to take into account the interactions between the analogue and digital parts since the beginning of the development. This thesis presents a systematic and gradual refinement process for the analogue parts comparable to what exists for the digital parts. A special attention has been paid to the definition of the highest abstracted analogue levels and to the correspondence between the analogue and the digital abstraction levels. The analogue refinement consistency requires to detect the abstraction level where a too idealised model leads to unrealistic behaviours. Then the refinement step consist in introducing – for instance – the limitations and non-linearities that have a strong impact on the behaviour. Such a step can be done at a relatively high level of abstraction. Correctly choosing a modelling style, that suits well an abstraction level, is crucial to obtain the best trade-off between the simulation speed and the accuracy. The modelling styles at each abstraction level have been examined to understand their impact on the simulation. The SystemC-AMS models of computation have been classified for this purpose. The SystemC-AMS simulation times have been compared to that obtained with Matlab Simulink. The interface between models arisen from the architectural exploration – still rather abstracted – and the more detailed models that are required for the implementation, is still an open question. A library of complex electronic components described with the most accurate model of computation of SystemC-AMS (ELN modelling) could be a way to achieve such an interface. In order to show what should be an element of such a library, and thus prove the concept, a model of an operational amplifier has been elaborated. It is enough detailed to take into account the output voltage saturation and the finite slew rate of the amplifier. Nevertheless, it remains sufficiently abstracted to stay independent from any architectural or technological assumption.

Proceeding from a specification, one develops an abstract mathematical model of a system, or portion of a system. This model of a system is validated to insure that the specification is interpreted accurately and to explore different algorithms for implementing the system behavior. We use the words "portion of a system," because only rarely are systems designed wholly using a purely top-down approach. Commonly, the design approach is a mixture of top-down and bottom-up. But even in this mixed approach, top-down techniques are critical to the development of new, advanced system features and improving the performance of existing system components. An example of this style of design tools and environments is Ptolemy II. Ptolemy II is a high-level modeling tool created at UC-Berkeley. It supports heterogeneous and homogeneous modeling, simulation, and design of concurrent systems. High-level modeling of such embedded systems as digital electronics, hardware, and software can be effectively represented. The bottom-up design approach exploits design reuse to achieve the productivity necessary to build complex systems. Historically, chip design companies have always reused designs in going from one product generation to another, but the efficiency of bottom-up design is enhanced by the use of IP (Intellectual Property) cores that a company can buy from an outside source. Design libraries are useful for system design and are an example of IP cores. A sound methodology to translate Ptolemy models to SystemC models would have a very beneficial effect on the CAD/EDA industry. Ptolemy II is written in Java and its high-level designs, or abstract graph models, are represented as XML documents. Ptolemy's major emphasis is on the methodology for defining and producing embedded software together with the system in which it is embedded. SystemC is written in C++, and its industrial use is gaining momentum due to its ability to represent functionality, communication, software, and hardware at various levels of abstraction. SystemC produces synthesizable code. A methodology to convert Ptolemy models to synthesizable SystemC code would be the technical epitome of a hybrid between top-down and bottom-up design styles and methodologies. Such a methodology would enable system designers to obtain fast design exploration, efficient IP-reuse, and validation. Ptolemy has various components and models of computation. A model of computation dictates how components interact between other components. SystemC has its own models of computation and design libraries. XML and Perl are both powerful tools by themselves, and we use these tools in this research to create a sound methodology for translating Ptolemy models (high-level of abstraction) to synthesizable SystemC code (low-level of abstraction), i.e.: code which can serve as input to hardware tools. / Ph. D.

À l'ère de systèmes électroniques intégrés, les ingénieurs font face au défi de concevoir et de tester des systèmes hétérogènes contenant des parties analogiques, numériques, mécaniques et même du logiciel embarqué. Cela reste très difficile car il n'y a pas d'outil unifiant ces différents domaines de l’ingénierie. Ces systèmes, dits hétérogènes, ont leur comportement exprimées et spécifiés par plusieurs formalismes, chacun particulier à son domaine d'expertise (diagramme de machines à état pour les circuits de contrôle numérique, équations différentielles pour les modèles mécaniques, ou bien des réseaux de composants pour les circuits analogiques). Les outils de conception existants sont destinés à traiter des systèmes homogènes en utilisant un seul formalisme à la fois. Dans l'état actuel, l'industrie se bat avec des problèmes d'intégration à chaque étape de la conception, à savoir la spécification, la simulation, la validation et le déploiement. L'absence d'une approche qui comprend les spécifications des interfaces inter-domaines est souvent la cause des problèmes d'intégration de différentes parties d'un système hétérogène. Cette thèse propose une approche pour faire face à l'hétérogénéité en utilisant SysML comme outil fédérateur. Notre proposition repose sur la définition d'une sémantique explicite pour les diagrammes SysML ainsi que des éléments d'adaptation sémantiques capables d'enlever les ambiguïtés dans les interfaces multi-domaines. Pour démontrer l'efficacité de ce concept, un ensemble d'outils basés sur l'ingénierie dirigé par les modèles a été construit pour générer du code exécutable automatiquement à partir des spécifications. / In the era of highly integrated electronics systems, engineers face the challenge of designing and testing multi-faceted systems with single-domain tools. This is difficult and error-prone. These so called heterogeneous systems have their operation and specifications expressed by several formalisms, each one particular to specific domains or engineering fields (software, digital hardware, analog, etc.). Existing design tools are meant to deal with homogeneous designs using one formalism at a time. In the current state, industry is forced to battle with integration issues at every design step, i.e. specification, simulation, validation and deployment. Common divide-to-conquer approaches do not include cross-domain interface specification from the beginning of the project. This lack is often the cause of issues and rework while trying to connect parts of the system that were not designed with the same formalism. This thesis proposes an approach to deal with heterogeneity by embracing it from the beginning of the project using SysML as the unifying tool. Our proposal hinges on the assignment of well-defined semantics to SysML diagrams, together with semantic adaptation elements. To demonstrate the effectiveness of this concept, a toolchain is built and used to generate systems simulation executable code automatically from SysML specifications for different target languages using model driven engineering techniques.

The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope. / The wide variety of interconnection structures presently nowadays for SoC (Systemon- Chip), bus and networks-on-Chip NoCs, each of them with a wide set of setup parameters, provides a huge amount of design alternatives. Although the interconnection structure is a key SoC component, there are few design tools in order to set the appropriate configuration parameters for a given application. An efficient SoC project may comply an exploration stage among the possible solutions for the communication structure, during the first steps of the design process. The absence of appropriate tools for that exploration makes critical the designer?s judgment. The present study aims to enhance the communication SoC structure design area, when a NoC is used. This work proposes a methodology that allows the establishment of the NoC communication parameters using a high level model (SystemC TLM timed). Our approach analyzes and evaluates the NoC performance under a wide variety of traffic conditions. The experimental stage was conducted employing a model of a net represented by a SystemC TLM timed (Hermes_Temp). Parametric and pseudo-random generators control the network traffic. The analysis was carried on with a tool designed for these purpose, which generates a group of performance metrics. The results allow to elucidate the global and inner network behavior. The performance values are useful for the heterogeneous and homogeneous NoC design projects, improving the performance evaluation studies scope.