Nowadays the designs of HW/SW are extremely complex. HW/SW co-verification is really difficult, consequently the new design layer, Electronic-System Level (ESL), is proposed to replace the original design flow. Today¡¦s ESL can verify the whole system simulation include the Processor, Bus, Memory¡K such as the HWs. It also can run a small program on the system. But it is hard to verify the larger program - such as the operation system because the limitations of the simulation speed. Currently some people proposed the QEMU-SystemC virtual platform. It can greatly speed up the CPU simulation speed. But the abstract simulated CPU has no timing information. It is infeasible to explore the system execution time and performance. We proposed the method: CPU, Cache, TLB and SDRAM with timing model; connect the CPU and the designed HW in TLM bus module in the HW/SW co-simulation. We can analyze the performance in the estimated timing information, and it will not take many simulation times. In addition, we developed the analysis program to show the execution time in each program block. It can help designer to locate the performance bottleneck quickly in the complex HW/SW. A case study is the 3D graphic SoC. We find the performance bottleneck in HW/SW design according the performance information purposed by our work.

With complexities of Systems-on-Chip rising almost daily, the system designers have been searching for new methodology that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However, the most important things that system designers care about are system architectures (components topology), HW/SW performance, and the communication protocols. System designer has to make decisions on these factors in a very short time. Furthermore, the transaction level model (TLM) can satisfy the requests on simulation speed and the information that system designer need. We implement a TLM virtual prototype platform with SystemC composing with the variable wrappers. The basic modules: ISS interface, user-define modules and a flexible bus. Based on the infrastructures, a much faster modeling process of the system can be achieved in this thesis. Finally, the platform will run the whole-system-simulation to verify the functional model and collect the dynamic information on the buses and IPs to diagnose the bottle-neck of the system.

In this thesis, the VLSI implementation of Viterbi decoder using a design and simulation platform called SystemC is studied. For this purpose, the architecture of Viterbi decoder is tried to be optimized for VLSI implementations. Consequently, two novel area efficient structures for reconfigurable Viterbi decoders have been suggested. The traditional and SystemC design cycles are compared to show the advantages of SystemC, and the C++ platforms supporting SystemC are listed, installation issues and examples are discussed. The Viterbi decoder is widely used to estimate the message encoded by Convolutional encoder. For the implementations in the literature, it can be found that special structures called trellis have been formed to decrease the complexity and the area. In this thesis, two new area efficient reconfigurable Viterbi decoder approaches are suggested depending on the rearrangement of the states of the trellis structures to eliminate the switching and memory addressing complexity. The first suggested architecture based on reconfigurable Viterbi decoder reduces switching and memory addressing complexity. In the architectures, the states are reorganized and the trellis structures are realized by the usage of the same structures in subsequent instances. As the result, the area is minimized and power consumption is reduced. Since the addressing complexity is reduced, the speed is expected to increase. The second area efficient Viterbi decoder is an improved version of the first one and has the ability to configure the parameters of constraint length, code rate, transition probabilities, trace-back depth and generator polynomials.

Zur Beschreibung elektronischer Systeme hat SystemC inzwischen eine festen Platz in der Entwurfslandschaft gefunden. Ein wesentlicher Vorteil eines SystemC-Modells ist die bereits vorhandene Möglichkeit einer Simulation. Neben der rein funktionalen Simulation zur Entwurfsvalidierung ergeben sich für eine Simulation mit injizierten Fehlern zusätzliche Herausforderungen. In dieser Arbeit werden diverse Techniken zur Fehlerinjektion in SystemC vorgestellt. Einige vergleichende Experimente helfen diese Techniken zu bewerten. Anschließend werden einige Modelle präsentiert, die es gestatten, SystemC auch auf niederen Ebenen des Hardwareentwurfs einzusetzen. Mit den vorgeschlagenen Methoden eröffnet sich hiermit die Möglichkeit einer genauen Untersuchung zur Auswirkung von Hardwarefehlern in digitalen Schaltungen mit Hilfe von SystemC.

In diesem Beitrag wird eine Methode zur Beschreibung von Kostenfaktoren und deren Verknüpfung über Hierarchiegrenzen hinweg dargestellt. Sie eignet sich sowohl für rein digitale Systeme mit Softwareanteilen als auch für gemischt analog/digitale Systeme. Damit ist sie im Hardware-Software Codesign und im Analog-Digital Codesign zum Vergleich verschiedener Systemkompositionen anwendbar. Die Implementierung mit C++ ermöglicht neben einer Nutzung mit digitalem SystemC auch den Einsatz mit der analogen SystemC-Erweiterung SystemC-AMS und vereinfacht die Nutzung gegenüber einer vorhandenen VHDL-Implementierung. Als Anwendungsbeispiel fungieren Komponenten eines Systems zur Inertialnavigation.

Beim Aufbau von konfigurierbaren wafer-scale Systemen für pulsgekoppelte neuronale Netze werden hohe Anforderungen an die Kommunikation zwischen einzelnen Komponenten gestellt. Zur Unterstützung des Hardwareentwurfs, aber auch um die parallele Entwicklung der Software zu ermöglichen, können Simulationsmodelle verwendet werden. Der Aufbau der Architektur und die Implementierung als SystemC-Modell werden beschrieben. Aus der Simulation sind Rückschlüsse auf die Architektur möglich, es ergeben sich aber auch Anforderungen an die zu entwickelnde Softwareumgebung.

In this work was studying literature related to object orientated programming tools for hardware design, capabilities for modeling and synthesis of high-level models of abstraction. It was founded-out the operating principles of high-speed bus and created prototype of such bus in TLM level. It was created methodology for transformation of high-speed bus prototype to RTL level. This methodology was used for transformation of high-speed bus prototype to RTL level. Transformed module was synthesized to gate level. Simulation speed of high-speed bus model in TLM was compared with simulation speed of model in behavioral level. It was demonstrated universality and reuse capabilities of TLM models.

In this thesis, an 8-bit microcontroller, 8051 core, is implemented using SystemC programming language. SystemC is a new generation co-design language which is capable of both programming software and describing hardware parts of a complete system. The benefit of this design environment appears while developing a System-on-Chip (SoC), that is a system consisting both custom hardware parts and embedded software parts. SystemC is not a completely new language, but based on C++ with some additional class libraries and extensions to handle hardware related concepts such as signals, multi-valued logic, clock and delay elements. 8051 is an 8 bit microcontroller which is widely used in industry for many years. The 8051 core is still being used as the main controller in today&rsquo / s highly complex chips, such as communication and bus controllers. During the development cycles of a System-on-Chip, instead of using separate design environments for hardware and software parts, the usage of a unified co-design environment provides a better design and simulation methodology which also decreases the number of iterations at hardware software integration. In this work, an 8-bit 8051 microcontroller core and external memory modules are developed using SystemC that can be re-used in future designs to achieve more complex System-on-Chip&rsquo / s. During the development of the 8051 core, simulation results are analyzed at each step to verify the design from the very beginning of the work, which makes the design processes more structured and controlled and faster as a result.

Η ραγδαία αύξηση της πολυπλοκότητας των συστημάτων σε ολοκληρωμένα κυκλώματα (System-on-Chip, SoC), η πίεση του χρόνου για την είσοδό τους στην αγορά, καθώς και το υψηλό κόστος της διαδικασίας σχεδίασης και παραγωγής τους, έχει οδηγήσει τη βιομηχανία ανάπτυξης συστημάτων SoC στην κατεύθυνση της επαναχρησιμοποίησης «πυρήνων πνευματικής ιδιοκτησίας» (intellectual property cores), αλλά και στην αύξηση της αφαιρετικότητας της σχεδίασης, από το επίπεδο καταχωρητών (Register Transfer Level, RTL) στο επίπεδο του συστήματος (Electronic System Level Design, ESL). Η αύξηση αυτή της αφαιρετικότητας επιτυγχάνεται σήμερα, κατεξοχήν, με τη μεθοδολογία μοντελοποίησης συστημάτων SystemC TLM. Η μέθοδος αυτή μοντελοποιεί, κυρίως, την επικοινωνία μεταξύ των δομικών στοιχείων του συστήματος, δημιουργώντας ένα μοντέλο του συστήματος εύκολο στην κατασκευή, ταχείας εξομοίωσης και έτοιμο από τα πρώτα στάδια της σχεδίασης. Τα SystemC TLM μοντέλα ενός SoC δίνουν έτσι τη δυνατότητα να γίνει ανάλυση της απόδοσης του, αρχιτεκτονική του εξερεύνηση, επιβεβαίωση της λειτουργίας του καθώς επίσης και ανάπτυξη του λογισμικού που θα τρέχει πάνω σε αυτό, νωρίς στη διαδικασία σχεδίασης Στα πλαίσια αυτής της εργασίας αναπτύχθηκε ένα SystemC TLM μοντέλο του ελεγκτή CAN (CAN Controller). Ο ελεγκτής αυτός χρησιμοποιείται για την επικοινωνία μικροελεγκτών μέσω ενός σειριακού διαύλου (CAN Bus). Τα πλεονεκτήματα ενός δικτύου CAN είναι πολλά όπως, χαμηλή πολυπλοκότητα, μεγάλες ταχύτητες επικοινωνίας (έως 1Mbps), καλό μηχανισμό διαχείρισης σφαλμάτων, κ.α. Ο ελεγκτής που χρησιμοποιήθηκε ως αναφορά για την ανάπτυξη του μοντέλου αλλά και για συγκριτικά tests, είναι αυτός που έχει αναπτυχθεί από την Ευρωπαϊκή Υπηρεσία Διαστήματος (ESA) στα πλαίσια του προγράμματος HurriCANe. / The rapidly increasing complexity of systems in integrated circuits (System-on-Chip, SoC), time-to-market pressure, as well as the high cost of the development process, has led the SoC industry to the reuse of intellectual property cores and the increase of the design abstraction, from the Register Transfer Level (RTL) to the system level (Electronic System Level Design, ESL). This increase in abstraction is succeeded today, predominantly, with SystemC TLM modeling systems methodology. This method is, basically, modeling the communication between the components of a system, creating this way an, easy to make, with fast simulation and ready from the first stages of the design flow, model. So, the SystemC TLM model of a SoC gives the ability to commit performance analysis, architectural exploration, functional verification as well as embedded software development, early in the design process. Part of this work is the development of a SystemC TLM model of the CAN Controller. The controller is used for the communication of microcontroller via a serial bus (CAN Bus). The advantages of a CAN network are many, like low complexity, high speed communication (up to 1Mbps), good error management mechanism, etc. The CAN controller used as a reference model for the development process and for the comparative tests , is the one developed by the European Space Agency (ESA) under the program HurriCANe.

Esta dissertação é composta de duas partes principais em que apresenta, em sua primeira parte, o desenvolvimento de uma arquitetura de hardware para compensação de movimento para decodificadores de vídeo segundo o padrão H.264/AVC. A segunda parte apresenta a modelagem de uma arquitetura de hardware para codificação de vídeo segundo o mesmo padrão. Também são apresentados os conceitos básicos da codificação e decodificação de vídeo digital segundo o padrão H.264/AVC. A arquitetura desenvolvida para compensação de movimento, denominada HP422- MoCHA (High Profile 4:2:2 Motion Compensation Hardware Architecture) (ZATT, 2008), baseada na arquitetura MoCHA (Motion Compensator Hardware Architecture) (AZEVEDO, 2007), suporta o conjunto de ferramentas da compensação de movimento para o perfil High 4:2:2 do H.264/AVC. Esta arquitetura está particionada em três blocos principais: Preditor de Vetores de Movimento, Acesso à Memória e Processador de Amostras. Esses blocos funcionam na forma de um pipeline, existindo buffers entre os mesmos para armazenar os resultados intermediários. A descrição foi desenvolvida com a linguagem VHDL e alcança desempenho para decodificar, em tempo real, vídeos HDTV 1920x1080 a 30 quadros por segundo. Na literatura atual não foi encontrada nenhuma solução detalhada para a compensação de movimento no perfil High 4:2:2 do padrão H.264/AVC. Uma nova estrutura para interpolação de amostra na compensação de movimento foi proposta, sendo que sua versão para o Perfil Main se mostra 17% mais compacta, em termos de gates, que a solução mais compacta encontrada na literatura, sem degradação de performance. A segunda parte do texto detalha a modelagem de uma arquitetura de codificação de vídeo segundo o H.264/AVC. A descrição utiliza a linguagem SystemC e consumiu aproximadamente 15.000 linhas de código. Seu projeto foi desenvolvido com o objetivo de codificar vídeo H.264/AVC segundo o perfil Main do padrão com desempenho para codificar vídeos 1920x1080 em tempo real, a 30 quadros por segundo. A modelagem alcançou o objetivo principal de chegar a uma implementação funcional de um codificador, embora assumindo diversas restrições de codificação, permitindo a caracterização temporal e de comunicação do codificador. Dessa forma, o modelo se mostra uma poderosa ferramenta para o desenvolvimento do sistema de codificação em HW, desde a etapa de projeto até a verificação final. Não foi encontrado na literatura, até o presente momento, nenhum trabalho que descreva uma modelagem em alto nível de um hardware para o codificador, ou mesmo para o decodificador, de vídeo H.264/AVC. / This thesis is comprised by two main parts that present, in the first part, the development of a motion compensation hardware architecture for video decoders in compliance with the H.264/AVC standard. The second part presents a hardware architecture modeling for a video encoder compliant to the same video standard. The digital video coding basics in the H.264/AVC standard are also reviewed. The developed motion compensation hardware architecture, named HP422-MoCHA (High Profile 4:2:2 Motion Compensation Hardware Architecture) (ZATT, 2008), is based on the MoCHA (Motion Compensator Hardware Architecture) (AZEVEDO, 2007) architecture. It supports the motion compensation toolset for the H.264/AVC High 4:2:2 profile. This architecture is divided in three main modules: Motion Vector Predictor, Memory Access and Sample Processor. These modules work in a pipeline and are interfaced by buffers to store the intermediate data. The architecture was described in the VHDL language and reaches the required throughput for real time decoding of HDTV 1920x1080 video sequences at 30 frames per second. In the current literature another detailed motion compensation solution for the H.264/AVC High 4:2:2 could not be found. A new filtering organization for the motion compensation sample interpolator was proposed and its Main profile version reduces 17% the gate count in comparison to the smallest solution found in the literature, without any performance degradation. The second part of the thesis details the modeling of a hardware architecture for a video encoder for the H.264/AVC standard. The model was described in SystemC language and used 15,000 source code lines. The project was designed for real time encoding of Main profile H.264/AVC for 1920x1080 video sequences at 30 frames per second. The model supported the main objective which was to obtain a functional encoder implementation, despite of the several encoding restrictions, permitting the temporal and communications characterization of the encoder. The model is presented as a powerful tool for the hardware video encoder development, as it is useful from the initial design to the final verification. No other hardware encoder or decoder modeling description was found in the current literature for the H.264/AVC video coding standard.