Le développement des systèmes de télécommunication et de transfert d’informations motive la mise au point de systèmes de transmission qui permettent des débits plus élevés sur des distances plus grandes. De ce fait, les transistors utilisés dans ces systèmes doivent fonctionner à des fréquences et des puissances plus élevées. Différents transistors sont apparus pour répondre au mieux aux contraintes des applications visées par ces systèmes. Les transistors à haute mobilité électronique, HEMT, en nitrure de gallium (GaN) répondent actuellement aux applications allant de 1GHz à 30GHz. Pour ces applications, les HEMT GaN concurrencent avantageusement les technologies bipolaires et BiCMOS basées sur SiGe, les LDMOS Si et SiC, ainsi que les PHEMT GaAs. Même si la filière technologique GaN est encore récente, les HEMT GaN semblent prometteurs. A l’image des autres technologies III-V (InP, GaAs), les procédés de fabrication utilisés pour les HEMT AlGaN/GaN sont complexes et entraînent la formation de nombreux défauts cristallins. Des effets parasites de fonctionnement sont induits par des mécanismes physiques qui pénalisent le transport des porteurs dans la structure. De ce fait, à l’heure actuelle, ces effets parasites ont une influence négative sur les performances de ce transistor. Ils sont principalement liés aux pièges à électrons induits par des impuretés présentes dans le matériau ou des défauts cristallins. Malgré cela, les performances sont très prometteuses et rivalisent déjà avec d’autres technologies hyperfréquences (InP, GaAs, SiC et Si) puisque les HEMTs AlGaN/GaN débitent des puissances de 4W/mm à 30GHz [ITRS08]. Les travaux présentés dans ce manuscrit sont consacrés à l'étude des phénomènes parasites dans les HEMTs AlGaN/GaN. Les composants étudiés dans ce travail proviennent du programme blanc ANR CARDYNAL et ont été fabriqués par III-V Lab Alcatel-Thales. Une méthodologie a été développer afin de permettre la simulation TCAD d’un HEMT GaN dans l’objectif de valider ou d’invalider les origines des mécanismes de dégradation ainsi que des effets parasites. Le courant de grille a été spécialement étudié et un modèle analytique permettant de le décrire en fonction de la température a été développé. Les mécanismes de transport à travers la grille ont aussi été étudiés par simulation TCAD afin de les localiser géographiquement dans la structure du transistor. / III-V nitrides have attracted intense interest recently for applications in high-temperature, high-power electronic devices operating at microwave frequencies. Great progress has been made in recent years to improve the characteristics of nitride High Electron Mobility Transistors (HEMTs). However, it's necessary to study the mecanisms involved in the electron transport as the mechanic strain on the AlGaN layer, the fixed charge distribution and leakage currents. In this goal, from DC I-V measurements, pulsed I-V measurements and DCTS measurements, TCAD simulation are used to validate the assumption on the origin of the parasitic mechanisms on the electron transport. I-V measurement in temperature (from 100K to 200K) are used to identify the nature of mechanisms (Poole-Frenkel, band-to-band tunneling, thermionic,..). With this method, an accurate study of the gate current was done. To choose the different physical phenomena and which model to implement in the TCAD simulations, an analytical model was developed with a compraison with measurements. These mechanisms are validated by TCAD simulation. The comparaison between I-V measurements and simulation permit to localize (in the transistor) these parasitic mechanisms. In conclusion of this work, a high density of traps in a thin layer under the gate increase the probability of tunnelling current through the gate. When the gate bias increases, the high density of traps in AlGaN layer is using by electrons to leak by the gate. When the gate bias increases, the valence band in AlGaN layer is aligned with the conduction band in the channel. The very thin thickness of this layer (about 25nm) makes possible a band-to-band tunneling.

Les composants actifs des convertisseurs de puissance empoyés pour la traction ferroviaire 1200 volts sont actuellement des IGBTs. Ceux-ci sont handicapés par leurs pertes en commutation et leur emballement thermique. L'utilisation de transistors MOS de puissance permettrait de pallier ces inconvénients. Néanmoins, à ces niveaux de tension, les transistors MOS sont pénalisés par leur compromis "tenue en tension/résistance passante spécifique". Dans le cadre de ces travaux de thèse, nous avons étudié différents principes pour concevoir une nouvelle structure MOS performante. Nous avons arrêté notre choix sur une structure se basant sur le concept de la superjonction, réalisé par gravure profonde et diffusion de bore. Théoriquement, cette structure atteint 13 mOcm2 pour 1200 V. Une grande partie des travaux de recherche a consisté à optimiser cette structure. Pour cela, nous avons étudié l'influence des paramètres technologiques et géométriques sur le compromis "tenue en tension/résistence passante spécifique". Nous avons également développé une terminaison innovante afin d'assurer la tenue en tension du composant. Il a ensuite fallu identifier les étapes critiques du procédé de fabrication. A partir de ces résultats, nous avons réalisé une diode 1200 V qui nous a permis de valider certaines briques technologiques.

<p>The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. </p><p>In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current </p><p>The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.</p>

<p>Today, micro- and nano-electronic devices are becoming more complex and advanced as the dimensions are shrinking. It is therefore a very challenging task to develop new device technologies with performance that can be predicted. This thesis focuses on advanced measurement techniques and TCAD simulations in order to characterize and understand the device physics of advanced semiconductor devices. </p><p>TCAD simulations were made on a novel MOSFET device with asymmetric source and drain structures. The results showed that there exists an optimum range of implantation doses where the device has a significantly higher figure-of-merit regarding speed and voltage capability, compared to a symmetric MOSFET. Furthermore, both 2D and 3D simulations were used to develop a resistive model of the substrate noise coupling. </p><p>Of particular interest to this thesis is the random dopant fluctuation (RDF). The result of RDF can be characterized using very advance and reliable measurement techniques. In the thesis an ultra-high precision parametric mismatch measurement system was designed and implemented. The best ever reported performance on short-term repeatability of the measurements was demonstrated. A new bipolar parametric mismatch phenomenon was also revealed using the measurement system.</p><p>A complete simulation platform, called SiSPET (Simulated Statistical Parameter Extraction Tool), was developed and integrated into the framework of a commercial TCAD environment. A special program for randomization of the doping was developed and proven to provide RDF effects in agreement measurement. The SiSPET system was used to investigate how different device models were able to take RDF effects into account. The RDF effects were translated in to parameter fluctuations using the developed extraction routines. It was shown that the basic MOSFET fluctuation model could be improved by including the field dependenent mobility. However, if a precise description of the fluctuations is required an advanced compact-model, such as MOS Model 11 should be used.</p>

Today, micro- and nano-electronic devices are becoming more complex and advanced as the dimensions are shrinking. It is therefore a very challenging task to develop new device technologies with performance that can be predicted. This thesis focuses on advanced measurement techniques and TCAD simulations in order to characterize and understand the device physics of advanced semiconductor devices. TCAD simulations were made on a novel MOSFET device with asymmetric source and drain structures. The results showed that there exists an optimum range of implantation doses where the device has a significantly higher figure-of-merit regarding speed and voltage capability, compared to a symmetric MOSFET. Furthermore, both 2D and 3D simulations were used to develop a resistive model of the substrate noise coupling. Of particular interest to this thesis is the random dopant fluctuation (RDF). The result of RDF can be characterized using very advance and reliable measurement techniques. In the thesis an ultra-high precision parametric mismatch measurement system was designed and implemented. The best ever reported performance on short-term repeatability of the measurements was demonstrated. A new bipolar parametric mismatch phenomenon was also revealed using the measurement system. A complete simulation platform, called SiSPET (Simulated Statistical Parameter Extraction Tool), was developed and integrated into the framework of a commercial TCAD environment. A special program for randomization of the doping was developed and proven to provide RDF effects in agreement measurement. The SiSPET system was used to investigate how different device models were able to take RDF effects into account. The RDF effects were translated in to parameter fluctuations using the developed extraction routines. It was shown that the basic MOSFET fluctuation model could be improved by including the field dependenent mobility. However, if a precise description of the fluctuations is required an advanced compact-model, such as MOS Model 11 should be used.

The development of computer aided design tools for devices and circuits has increased the interest for accurate transistor modeling in microwave applications. In the increasingly expanding wireless communication market, there is a huge demand for high performance RF power devices. The silicon LD- MOSFET transistor is dueto its high power performance is today widely used in systems such as mobile base stations, private branch exchanges (PBX), and local area networks (LAN) utilizing the bands between 0.9 to 2.5 GHz. In this research we simulated LD-MOSFET transistor characteristics of the structure provided by Infineon technology at Kista, Stockholm. The maximum drain current obtained in the simulation was 400 mA at a gate voltage of 8 V. This value is somewhat higher than the measured one. This difference can be attributed to the parasitic effects since no parasitic effects were included in the simulations in the beginning. The only parasitic effect studied was by placing the source contact at the bottom of the substrate according to real commercial device. The matching between simulated and measured results were improved and maximum drain current was reduced to 300 mA/mm which was 30% higher than the measured drain current The large signal RF simulations were performed in time-domain in our novel technique developed at LiU. This technique utilizes a very simple amplifier circuit without any passive components. Only DC bias and RF signals are applied to the gate and drain terminals, with the same fundamental frequency but with 180o phase difference. The RF signal at the drain acting as a short at higher harmonics. These signals thus also acted as an active match to the transistor. Large signal RF simulations were performed at 1, 2 and 3 GHz respectively. The maximum of drain current signal was observed at the maximum of drain voltage signal indicating the normal behavior of the transistor. At 1 GHz the output power was 1.25 W/mm with 63% of drain efficiency and 23.7 dB of gain. The out pout power was decreased to 1.15 W/mm and 1.1 W/mm at 2 and 3 GHz respectively at the same time the efficiency and gain was also decreased to 57% and 19 dB at 2 GHz and 51% and 15 dB at 3GHz respectively.

Nesta tese são apresentados estudos do impacto de armadilhas no desempenho elétrico de MOSFETs em nível de circuito e um simulador Ensamble Monte Carlo (EMC) é apresentado visando a análise do impacto de armadilhas em nível de dispositivo. O impacto de eventos de captura e emissão de portadores por armadilhas na performance e confiabilidade de circuitos é estudada. Para tanto, um simulador baseado em SPICE que leva em consideração a atividade de armadilhas em simulações transientes foi desenvolvido e é apresentado seguido de estudos de caso em células SRAM, circuitos combinacionais, ferramentas de SSTA e em osciladores em anel. Foi também desenvolvida uma ferramenta de simulação de dispositivo (TCAD) atomística baseada no método EMC para MOSFETs do tipo p. Este simulador é apresentado em detalhes e seu funcionamento é testado conceitualmente e através de comparações com ferramentas comerciais similares. / This thesis presents studies on the impact of charge traps in MOSFETs at the circuit level, and a Ensemble Monte Carlo (EMC) simulation tool is developed to perform analysis on trap impact on PMOSFETs. The impact of charge trapping on the performance and reliability of circuits is studied. A SPICE based simulator, which takes into account the trap activity in transient simulations, was developed and used on case studies of SRAM, combinational circuits, SSTA tools and ring oscillators. An atomistic device simulator (TCAD) for modeling of p-type MOSFETs based on the EMC simulation method was also developed. The simulator is explained in details and its well function is tested.

abstract: This PhD thesis consists of three main themes. The first part focusses on modeling of Silver (Ag)-Chalcogenide glass based resistive memory devices known as the Programmable Metallization Cell (PMC). The proposed models are examined with the Technology Computer Aided Design (TCAD) simulations. In order to find a relationship between electrochemistry and carrier-trap statistics in chalcogenide glass films, an analytical mapping for electron trapping is derived. Then, a physical-based model is proposed in order to explain the dynamic behavior of the photodoping mechanism in lateral PMCs. At the end, in order to extract the time constant of ChG materials, a method which enables us to determine the carriers’ mobility with and without the UV light exposure is proposed. In order to validate these models, the results of TCAD simulations using Silvaco ATLAS are also presented in the study, which show good agreement. In the second theme of this dissertation, a new model is presented to predict single event transients in 1T-1R memory arrays as an inverter, where the PMC is modeled as a constant resistance while the OFF transistor is model as a diode in parallel to a capacitance. The model divides the output voltage transient response of an inverter into three time segments, where an ionizing particle striking through the drain–body junction of the OFF-state NMOS is represented as a photocurrent pulse. If this current source is large enough, the output voltage can drop to a negative voltage. In this model, the OFF-state NMOS is represented as the parallel combination of an ideal diode and the intrinsic capacitance of the drain–body junction, while a resistance represents an ON-state NMOS. The proposed model is verified by 3-D TCAD mixed-mode device simulations. In order to investigate the flexibility of the model, the effects of important parameters, such as ON-state PMOS resistance, doping concentration of p-region in the diode, and the photocurrent pulse are scrutinized. The third theme of this dissertation develops various models together with TCAD simulations to model the behavior of different diamond-based devices, including PIN diodes and bipolar junction transistors (BJTs). Diamond is a very attractive material for contemporary power semiconductor devices because of its excellent material properties, such as high breakdown voltage and superior thermal conductivity compared to other materials. Collectively, this research project enhances the development of high power and high temperature electronics using diamond-based semiconductors. During the fabrication process of diamond-based devices, structural defects particularly threading dislocations (TDs), may affect the device electrical properties, and models were developed to account of such defects. Recognition of their behavior helps us understand and predict the performance of diamond-based devices. Here, the electrical conductance through TD sites is shown to be governed by the Poole-Frenkel emission (PFE) for the temperature (T) range of 323 K ˂ T ˂ 423 K. Analytical models were performed to fit with experimental data over the aforementioned temperature range. Next, the Silvaco Atlas tool, a drift-diffusion based TCAD commercial software, was used to model diamond-based BJTs. Here, some field plate methods are proposed in order to decrease the surface electric field. The models used in Atlas are modified to account for both hopping transport in the impurity bands associated with high activation energies for boron doped and phosphorus doped diamond. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2017

abstract: The scaling of transistors has numerous advantages such as increased memory density, less power consumption and better performance; but on the other hand, they also give rise to many reliability issues. One of the major reliability issue is the hot carrier injection and the effect it has on device degradation over time which causes serious circuit malfunctions. Hot carrier injection has been studied from early 1980's and a lot of research has been done on the various hot carrier injection mechanisms and how the devices get damaged due to this effect. However, most of the existing hot carrier degradation models do not consider the physics involved in the degradation process and they just calculate the change in threshold voltage for different stress voltages and time. Based on this, an analytical expression is formulated that predicts the device lifetime. This thesis starts by discussing various hot carrier injection mechanisms and the effects it has on the device. Studies have shown charges getting trapped in gate oxide and interface trap generation are two mechanisms for device degradation. How various device parameters get affected due to these traps is discussed here. The physics based models such as lucky hot electron model and substrate current model are presented and gives an idea how the gate current and substrate current can be related to hot carrier injection and density of traps created. Devices are stressed under various voltages and from the experimental data obtained, the density of trapped charges and interface traps are calculated using mid-gap technique. In this thesis, a simple analytical model based on substrate current is used to calculate the density of trapped charges in oxide and interface traps generated and it is a function of stress voltage and stress time. The model is verified against the data and the TCAD simulations. Finally, the analytical model is incorporated in a Verilog-A model and based on the surface potential method, the threshold voltage shift due to hot carrier stress is calculated. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2017

abstract: In recent years, there has been increased interest in the Indium Gallium Nitride (InGaN) material system for photovoltaic (PV) applications. The InGaN alloy system has demonstrated high performance for high frequency power devices, as well as for optical light emitters. This material system is also promising for photovoltaic applications due to broad range of bandgaps of InxGa1-xN alloys from 0.65 eV (InN) to 3.42 eV (GaN), which covers most of the electromagnetic spectrum from ultraviolet to infrared wavelengths. InGaN’s high absorption coefficient, radiation resistance and thermal stability (operating with temperature > 450 ℃) makes it a suitable PV candidate for hybrid concentrating solar thermal systems as well as other high temperature applications. This work proposed a high efficiency InGaN-based 2J tandem cell for high temperature (450 ℃) and concentration (200 X) hybrid concentrated solar thermal (CSP) application via numerical simulation. In order to address the polarization and band-offset issues for GaN/InGaN hetero-solar cells, band-engineering techniques are adopted and a simple interlayer is proposed at the hetero-interface rather than an Indium composition grading layer which is not practical in fabrication. The base absorber thickness and doping has been optimized for 1J cell performance and current matching has been achieved for 2J tandem cell design. The simulations also suggest that the issue of crystalline quality (i.e. short SRH lifetime) of the nitride material system to date is a crucial factor limiting the performance of the designed 2J cell at high temperature. Three pathways to achieve ~25% efficiency have been proposed under 450 ℃ and 200 X. An anti-reflection coating (ARC) for the InGaN solar cell optical management has been designed. Finally, effective mobility model for quantum well solar cells has been developed for efficient quasi-bulk simulation. / Dissertation/Thesis / Doctoral Dissertation Physics 2017