A bord des véhicules électriques (VE) et Hybrides (VEH), les fonctions de tractions sont assurées par des convertisseurs électroniques de puissances. Ces derniers sont constitués de module de puissance (IGBTs ou MOSFETs). Au cours de leur fonctionnement, ces modules sont parfois soumis à de fortes contraintes électriques et thermiques qui amènent à une défaillance ou même à une destruction. Le premier objectif sera de réaliser un banc expérimentale permettant d'étudier le vieillissement des modules IGBTs en régîmes extrêmes de fonctionnement (mode de court-circuit). Ainsi, nous évaluerons les différents indicateurs de vieillissements permettant de prédire la défaillance du composant. Il sera question aussi de suivre le vieillissement ou une dégradation initié sur les composants IGBTs par thermographie infrarouge. Le second objectif sera de modéliser et simuler par éléments finis différentes structures d'IGBTs, afin de valider les modèles en fonctionnement statique et dynamique. L'avantage de l'approche multicellulaire par rapport à l'approche unicellulaire sera mis en avant.

Le Large Hadron Collider (LHC), située au CERN, Genève, produit des collisions de protons accélérés à une énergie de 3.5 TeV depuis le 23 Novembre 2009. L'expérience ATLAS enregistre depuis des données et poursuit sa recherche de nouvelle physique à travers l'analyse de la cinématique des événements issues des collisions. L'augmentation prévue de la luminosité sur la période s'étalant de 2011 2020 apportera de nouveaux défis pour le détecteur qui doivent être considérés pour maintenir les bonnes performance de la configuration actuelle. Le détecteur interne sera le sous-détecteur le plus affecté par l'augmentation de la luminosité qui se traduira par une augmentation des dommages occasionnés par la forte radiation et par la multiplication du nombre de traces associées à chaque croisement de faisceau. Les dommages causés par l'irradiation intense entrainera une perte d'efficacité de détection et une réduction du nombre de canaux actifs. Un intense effort de Recherche et Développement (R&D) est présentement en cours pour concevoir un nouveau détecteur pixel plus tolérant aux radiations et au cumul des événements générant un grand nombre de traces à reconstruire. Un premier projet de mise-à-jour du détecteur interne, nommé Insertable B-Layer (IBL) consiste à ajouter un couche de détection entre le tube à vide du faisceau et la première couche de silicium. Le projet SLHC prévoit de remplacer l'ensemble du détecteur interne par une version améliorée plus tolérante aux radiations et aux cumuls des événements. Dans cet ouvrage, je présente une étude utilisant la simulation technologique assisté par ordinateur (TCAD) portant sur les méthodes de conception des détecteurs pixels planaires permettant de réduire les zones inactives des détecteurs et d'augmenter leurs tolérances aux radiations. Les différents modèles physiques disponible ont étés étudiés pour développer un modèle cohérent capablede prédire le fonctionnement des détecteurs pixels planaires après irradiation. La structure d'anneaux de gardes utilisée dans le détecteur interne actuel a été étudié pour obtenir de l'information sur les possible méthodes permettant de réduire l'étendu de la surface occupée par cette structure tout en conservant un fonctionnement stable tout au long de la vie du détecteur dans l'expérience ATLAS. Une campagne de mesures sur des structures pixels fut organisée pour comparer les résultats obtenue grâce à la simulation avec le comportement des structures réelles. Les paramètres de fabrication ainsi que le comportement électrique ont été mesurés et comparés aux simulations pour valider et calibrer le modèle de simulation TCAD. Un modèle a été développé pour expliquer la collection de charge excessive observée dans les détecteurs planaires en silicium lors de leur exposition a une dose extrême de radiations. Finalement, un modèle simple de digitalisation à utiliser pour la simulation de performances détecteurs pixels individuels exposés à des faisceau de haute énergie ou bien de l'ensemble du détecteur interne est présenté. Ce modèle simple permets la comparaison entre les données obtenue en faisceau test aux modèle de transport de charge inclut dans ladigitalisation. Le dommage dû à la radiation , l'amincissement et l'utilisation de structures à bords minces sont autant de structures dont les effets sur la collecte de charges affectent les performance du détecteur. Le modèle de digititalisation fut validé pour un détecteur non-irradié en comparant les résultats obtenues avec les données acquises en test faisceau de haut énergie. Le modèle validé sera utilisé pour produire la première simulation de l'IBL incluant les effets d'amincissement du substrat, de dommages dûes aux radiations et de structure dotés de bords fins.

Une des principales solutions technologiques liées à la réduction d'échelle de la technologie CMOS est aujourd'hui clairement orientée vers les transistors MOSFET faiblement dopés à multiples grilles. Ceux-ci proposent une meilleure immunité contre les effets canaux courts comparés aux transistors MOSFET bulk planaires (cf. ITRS 2011). Parmi les MOSFETs à multiples grilles, le transistor FinFET SOI est un candidat intéressant de par la similarité de son processus de fabrication avec la technologie des transistors planaires. En parallèle, il existe une réelle attente de la part des concepteurs et des fonderies à disposer de modèles compacts efficaces numériquement, précis et proches de la physique, insérés dans les " design tools " permettant alors d'étudier et d'élaborer des circuits ambitieux en technologie FinFET. Cette thèse porte sur l'élaboration d'un modèle compact orienté conception du transistor FinFET valide aux dimensions nanométriques. Ce modèle prend en compte les effets canaux courts, la modulation de longueur de canal, la dégradation de la mobilité, leseffets de mécanique quantique et les transcapacités. Une validation de ce modèle est réalisée par des comparaisons avec des simulations TCAD 3D. Le modèle compact est implémenté en langage Verilog-A afin de simuler des circuits innovants à base de transistors FinFET. Une modélisation niveau-porte est développée pour la simulation de circuits numériques complexes. Cette thèse présente également un modèle compact générique de transistors MOSFET SOI canaux long faiblement dopés à multiple grilles. La dépendance à la température est prise en compte. Selon un concept de transformation géométrique, notre modèle compact du transistor MOSFET double grille planaire est étendu pour s'appliquer à tout autre type de transistor MOSFET à multiple grille (MuGFET). Une validation expérimentale du modèle MuGFET sur un transistor triple grille est proposée. Cette thèse apporte enfin des solutions pour la modélisation des transistors MOSFET double grille sans jonction.

Le développement des technologies de communication et de l'information nécessite des composants semi-conducteurs ultrarapides et à faible niveau de bruit. Les transistors bipolaires à hétérojonction (TBH) sont des dispositifs qui visent des applications à hautes fréquences et qui peuvent satisfaire ces conditions. L'objet de cette thèse est l'étude expérimentale et la modélisation du bruit haute fréquence des TBH Si/SiGe:C (technologie STMicroelectronics) et InP/InGaAs (III-V Lab Alcatel-Thales).Accompagné d'un état de l'art des performances dynamiques des différentes technologies de TBH, le chapitre I rappelle brièvement le fonctionnement et la caractérisation des TBH en régime statique et dynamique. La première partie du chapitre II donne la description des deux types de TBH, avec l'analyse des performances dynamiques et statiques en fonction des variations technologiques de ceux-ci (composition de la base du TBH SiGe:C, réduction des dimensions latérales du TBH InGaAs). Avec l'aide d'une modélisation hydrodynamique, la seconde partie montre l'avantage d'une composition en germanium de 15-25% dans la base du TBH SiGe pour atteindre les meilleurs performances dynamiques. Le chapitre III synthétise des analyses statiques et dynamiques réalisées à basse température permettant de déterminer le poids relatif des temps de transit et des temps de charge dans la limitation des performances des TBH. L'analyse expérimentale et la modélisation analytique du bruit haute fréquence des deux types de TBH sont présentées en chapitre IV. La modélisation permet de mettre en évidence l'influence de la défocalisation du courant, de l'auto-échauffement, de la nature de l'hétérojonction base-émetteur sur le bruit haute fréquence. Une estimation des performances en bruit à basse température des deux types de TBH est obtenues avec les modèles électriques.

The present work investigates the technology development of state-of-the-art SiGe and SiGeC Heterojunction Bipolar Transistors (HBT) by means of technology computer aided design (TCAD). The objective of this work is to obtain an advanced HBT very close to the real device not only in its process fabrication steps, but also in its physical behavior, geometric architecture, and electrical results. This investigation may lead to achieve the best electrical performances for the devices studied, in particular a maximum operating frequency of 500 GHz. The results of this work should help to obtain more physical and realistic simulations, a better understanding of charge transport, and to facilitate the development and optimization of SiGe and SiGeC HBT devices.The TCAD simulation kits for SiGe/SiGeC HBTs developed during our work have been carried out in the framework of the STMicroelectronics bipolar technology evolution. In order to achieve accurate simulations we have used, developed, calibrated and implemented adequate process models, physical models and extraction methodologies. To our knowledge, this work is the first approach developed for SiGe/SiGeC HBTs which takes into account the impact of the strain, and of the germanium and carbon content in the base, for both: process and electrical simulations.In this work we will work with the successive evolutions of B3T, B4T and B5T technologies. For each new device fMAX improves of 100 GHz, thus the technology B3T matches to 300 GHz, B4T and B5T to 400 and 500 GHz, respectively.Chapter one introduces the SiGe SiGeC heterojunction bipolar technologies and their operating principles. This chapter deals also with the high frequency AC transistor operation, the extraction methods for fMAX and the carrier transport in extremely scaled HBTs.Chapter two analyzes the physical models adapted to SiGeC strained alloys used in this work and the electrical simulation of HBT devices. This is also an important work of synthesis leading to the selection, implementation and development of dedicated models for SiGeC HBT simulation.Chapter three describes the B3T TCAD simulation platform developed to obtain an advanced HBT very close to the real device. In this chapter the process fabrication of the B3T technology is described together with the methodology developed to simulate advanced HBT SiGeC devices by means of realistic TCAD simulations.Chapter four describes the HBT architectures developed during this work. We will propose low-cost structures with less demanding performance requirements and highly performing structures but with a higher cost of production. The B4T architecture which has been manufactured in clean-room is deeply studied in this chapter. The impact of the main fabrication steps is analyzed in order to find the keys process parameters to increase fMAX without degrading other important electrical characteristics. At the end of this chapter the results obtained is used to elaborate a TCAD simulation platform taking into account the best trade-off of the different key process parameters to obtain a SiGeC HBT working at 500 GHz of fMAX.

Recently, several SiGe HBT devices fabricated on CMOS-compatible silicon on insulator (SOI) substrates (SiGe HBTs-on-SOI) have been demonstrated, combining the well-known SiGe HBT performance with the advantages of SOI substrates. These new devices are especially interesting in the context of extreme environments - highly challenging surroundings that lie outside commercial and even military electronics specifications. However, fabricating HBTs on SOI substrates instead of traditional silicon bulk substrates requires extensive modifications to the structure of the transistors and results in significant trade-offs. The present work investigates, with measurements and TCAD simulations, the performance and reliability of SiGe heterojunction bipolar transistors fabricated on silicon on insulator substrates with respect to operation in extreme environments such as at extremely low or extremely high temperatures or in the presence of radiation (both in terms of total ionizing dose and single effect upset).

Este trabalho apresenta o desenvolvimento de um sensor de corrente transiente destinado a detectar a ocorrência de um evento transiente causado pela incidência de radiação ionizante em um circuito integrado. Iniciando com uma descrição dos efeitos da radiação sobre os circuitos integrados e dos tipos de radiação de interesse, os fundamentos da técnica Bulk- BICS são apresentados e as propostas existentes na literatura são expostas e avaliadas, com ênfase no sensor que utiliza a célula de memória dinâmica DynBICS, resultado de um trabalho prévio e do qual se dispõe de amostras fabricadas. Sobre essas amostras são efetuados testes elétricos, um ensaio de dose total irradiada TID e um ensaio de estimulação laser, cujos resultados são apresentados e confirmam a funcionalidade da topologia da célula de memória dinâmica aplicada a circuitos Bulk-BICS. Em seguida, é apresentada a topologia da célula de memória integrativa como uma evolução da célula de memória dinâmica e propõe-se o circuito de um novo sensor Bulk-BICS baseado na nova célula. O funcionamento elétrico do circuito desse novo sensor TRIBICS é avaliado através de simulação de circuitos determinando-se a sensibilidade e o tempo de resposta do sensor utilizando-se pulsos de corrente em dupla exponencial. É feita uma análise do funcionamento da célula de memória estática e, através de uma comparação de desempenho entre as células de memória estáticas utilizadas em três circuitos propostos e a célula de memória integrativa, utilizando um modelo simplificado, mostra-se que a célula de memória integrativa é mais rápida e sensível do que as contrapartes estáticas O sensor TRIBICS é então simulado em conexão com um modelo de dispositivo, sendo antes apresentados os modelos TCAD do inversor utilizado como alvo da incidência da radiação nas simulações. São apresentados resultados obtidos individualmente para o transistor NMOS e para o transistor PMOS, nos quais se mostra a formação de um canal condutivo entre dreno e fonte durante o SET. Mostra-se, também, que os resultados obtidos com a simulação de dispositivos não concorda com aqueles proporcionados pela simulação de circuitos no tocante à divisão das correntes transitórias entre dreno, fonte e substrato. O resultado das simulações de dispositivo efetuadas com os modelos TCAD em modo misto com o circuito TRIBICS descrito em SPICE mostram a relação entre a transferência de energia da irradiação LET e a efetiva deteção do SET provocado, em função da distância entre os contatos de bulk ou substrato, permitindo determinar a máxima distância entre contatos para 100% de certeza na deteção do SET. Com isso, obtém-se uma estimativa do número de transistores que pode ser monitorado pelos Bulk-BICS. É proposta a estratégia de implementação dos Bulk-BICS na forma de uma standard cell a ser posicionada entre os grupos de transistores sob monitoração, e uma estimativa da relação entre as áreas dos transistores monitorados e do Bulk-BICS é apresentada. Por fim, é estudada a questão da fabricação dos Bulk-BICS no mesmo substrato dos transistores monitorados e uma maneira de fazê-la é proposta. Os resultados encontrados permitem definir a viabilidade e a eficácia da técnica Bulk-BICS como forma de deteção de eventos transientes em sistemas digitais. / A current sensor to detect the occurrence of a single-event transient that is caused by the incidence of ionizing radiation in an integrated circuit is presented. Radiation of interest and their effects on the integrated circuits are discussed. Fundamentals of the Bulk-BICS technique and the circuits proposed in the literature to implement this technique are discussed and evaluated, with emphasis on the dynamic memory cell-based circuit DynBICS, which was developed as a previous work and with fabricated samples available. Experimental results obtained from a series of electrical tests, a TID test, and a laser-stimulated test that were conducted on a number of fabricated and packaged samples are presented. The results confirm that the dynamic memory cell is suitable and robust enough to be used in Bulk-BICS circuits. Next, evolution of the dynamic memory cell into an integrative memory cell is discussed and the circuit of a Bulk-BICS using this new memory cell topology is presented. The electrical operation of this new sensor TRIBICS is evaluated using circuit simulations. By using double-exponential current pulses, both the sensitivity and the response time are determined. The static memory cell operation is analyzed and a comparison of performance between static and integrative cells is performed using a simplified model. The results show that the integrative memory cell is faster and more sensitive than the static cells used in three state-ofthe- art sensors published in literature Then the TRIBICS sensor is simulated connected to a TCAD-modeled device, comprising an inverter, which is used as a target for radiation impact. TCAD models are previously presented and the results obtained when the PMOS and NMOS transistors are separately excited by radiation show the formation of a conductive link between drain and source regions during the occurrence of SET. The simulations also show that the results obtained by using TCAD simulations do not agree with the ones obtained by using circuit simulation regarding the current share among drain, source and bulk during the SET. Mixed-mode simulations using the TCAD models in conjunction of TRIBICS circuits described in SPICE show the relationship between LET and the effective SET-detection with the inter-tap distance as a parameter, and allows to determine the inter-tap distance for 100% of SET detection efficiency. Based on these results, an estimate of how many transistors can be monitored by the Bulk-BICS is obtained. It is proposed to implement the Bulk-BICS as a standard cell, to be positioned in between the standard cell that compose a digital circuit and the area overhead necessary to implant the sensors in a real circuit is estimated. The problem on how to manufacture the Bulk-BICS circuit in the same substrate of the monitored transistors is studied and a solution is proposed. The results show the viability and effectiveness of the Bulk-BICS technique, as a means to detect single-event transients in digital systems.

Este trabalho apresenta o desenvolvimento de um sensor de corrente transiente destinado a detectar a ocorrência de um evento transiente causado pela incidência de radiação ionizante em um circuito integrado. Iniciando com uma descrição dos efeitos da radiação sobre os circuitos integrados e dos tipos de radiação de interesse, os fundamentos da técnica Bulk- BICS são apresentados e as propostas existentes na literatura são expostas e avaliadas, com ênfase no sensor que utiliza a célula de memória dinâmica DynBICS, resultado de um trabalho prévio e do qual se dispõe de amostras fabricadas. Sobre essas amostras são efetuados testes elétricos, um ensaio de dose total irradiada TID e um ensaio de estimulação laser, cujos resultados são apresentados e confirmam a funcionalidade da topologia da célula de memória dinâmica aplicada a circuitos Bulk-BICS. Em seguida, é apresentada a topologia da célula de memória integrativa como uma evolução da célula de memória dinâmica e propõe-se o circuito de um novo sensor Bulk-BICS baseado na nova célula. O funcionamento elétrico do circuito desse novo sensor TRIBICS é avaliado através de simulação de circuitos determinando-se a sensibilidade e o tempo de resposta do sensor utilizando-se pulsos de corrente em dupla exponencial. É feita uma análise do funcionamento da célula de memória estática e, através de uma comparação de desempenho entre as células de memória estáticas utilizadas em três circuitos propostos e a célula de memória integrativa, utilizando um modelo simplificado, mostra-se que a célula de memória integrativa é mais rápida e sensível do que as contrapartes estáticas O sensor TRIBICS é então simulado em conexão com um modelo de dispositivo, sendo antes apresentados os modelos TCAD do inversor utilizado como alvo da incidência da radiação nas simulações. São apresentados resultados obtidos individualmente para o transistor NMOS e para o transistor PMOS, nos quais se mostra a formação de um canal condutivo entre dreno e fonte durante o SET. Mostra-se, também, que os resultados obtidos com a simulação de dispositivos não concorda com aqueles proporcionados pela simulação de circuitos no tocante à divisão das correntes transitórias entre dreno, fonte e substrato. O resultado das simulações de dispositivo efetuadas com os modelos TCAD em modo misto com o circuito TRIBICS descrito em SPICE mostram a relação entre a transferência de energia da irradiação LET e a efetiva deteção do SET provocado, em função da distância entre os contatos de bulk ou substrato, permitindo determinar a máxima distância entre contatos para 100% de certeza na deteção do SET. Com isso, obtém-se uma estimativa do número de transistores que pode ser monitorado pelos Bulk-BICS. É proposta a estratégia de implementação dos Bulk-BICS na forma de uma standard cell a ser posicionada entre os grupos de transistores sob monitoração, e uma estimativa da relação entre as áreas dos transistores monitorados e do Bulk-BICS é apresentada. Por fim, é estudada a questão da fabricação dos Bulk-BICS no mesmo substrato dos transistores monitorados e uma maneira de fazê-la é proposta. Os resultados encontrados permitem definir a viabilidade e a eficácia da técnica Bulk-BICS como forma de deteção de eventos transientes em sistemas digitais. / A current sensor to detect the occurrence of a single-event transient that is caused by the incidence of ionizing radiation in an integrated circuit is presented. Radiation of interest and their effects on the integrated circuits are discussed. Fundamentals of the Bulk-BICS technique and the circuits proposed in the literature to implement this technique are discussed and evaluated, with emphasis on the dynamic memory cell-based circuit DynBICS, which was developed as a previous work and with fabricated samples available. Experimental results obtained from a series of electrical tests, a TID test, and a laser-stimulated test that were conducted on a number of fabricated and packaged samples are presented. The results confirm that the dynamic memory cell is suitable and robust enough to be used in Bulk-BICS circuits. Next, evolution of the dynamic memory cell into an integrative memory cell is discussed and the circuit of a Bulk-BICS using this new memory cell topology is presented. The electrical operation of this new sensor TRIBICS is evaluated using circuit simulations. By using double-exponential current pulses, both the sensitivity and the response time are determined. The static memory cell operation is analyzed and a comparison of performance between static and integrative cells is performed using a simplified model. The results show that the integrative memory cell is faster and more sensitive than the static cells used in three state-ofthe- art sensors published in literature Then the TRIBICS sensor is simulated connected to a TCAD-modeled device, comprising an inverter, which is used as a target for radiation impact. TCAD models are previously presented and the results obtained when the PMOS and NMOS transistors are separately excited by radiation show the formation of a conductive link between drain and source regions during the occurrence of SET. The simulations also show that the results obtained by using TCAD simulations do not agree with the ones obtained by using circuit simulation regarding the current share among drain, source and bulk during the SET. Mixed-mode simulations using the TCAD models in conjunction of TRIBICS circuits described in SPICE show the relationship between LET and the effective SET-detection with the inter-tap distance as a parameter, and allows to determine the inter-tap distance for 100% of SET detection efficiency. Based on these results, an estimate of how many transistors can be monitored by the Bulk-BICS is obtained. It is proposed to implement the Bulk-BICS as a standard cell, to be positioned in between the standard cell that compose a digital circuit and the area overhead necessary to implant the sensors in a real circuit is estimated. The problem on how to manufacture the Bulk-BICS circuit in the same substrate of the monitored transistors is studied and a solution is proposed. The results show the viability and effectiveness of the Bulk-BICS technique, as a means to detect single-event transients in digital systems.

<p>We are in the midst of a technological revolution (popularly known as Industrie 4.0 or 4th Industrial Revolution) where our cars are being equipped with hundreds of sensors that make them safer, homes are becoming smarter, industry yields are at an all-time high, and internet-of-things is a reality. This was largely possible due to the developments in communication, electronics, motor controls, robotics, cyber security, software, efficient power distribution, etc. One of the major propellants of the 4th Industrial revolution is the ever-expanding applications of power electronics devices. All electrical energy will be provided, handled, and consumed through power electronics devices in the near future. Therefore, the reliability of power electronics devices will be instrumental in driving future technological advances. </p> <p> </p> <p><br></p><p>A myriad of devices is categorized as power electronics devices, and in the heart of those devices are the transistors. Although Silicon-based transistors still dominate the power electronics market, a paradigm shift towards wide bandgap semiconductors, such as silicon carbide (SiC), gallium nitride (GaN), beta-gallium oxide etc., is underway. However, realizing the full potential of these devices demands unconventional design, layout, and reliability. </p> <p> </p> <p>In this thesis, we try to establish a generalized model of reliability for power and logic transistors. We start by defining a comprehensive, substrate-, self-heating-, and reliability-aware safe operating area (SOA) that analytically establishes the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability before actual device fabrication. Then we take a deeper look into the reliability of individual transistors (a beta-gallium oxide transistor and a Silicon-based LDMOS), to test the predictions by the safe operating area, using both experiments and simulations. In the beta-gallium oxide transistor, we studied its implementation in a DC-DC voltage converter and concluded that the self-heating is a performance bottleneck and suggested approaches to alleviate it. For the LDMOS transistor, we investigated the hot carrier degradation (HCD) using experiments and simulations. We established that the HCD degradation kinetics is universal, and physics is the same as a classical transistor, despite a complicated geometry. Finally, we studied the correlation between HCD and radiation in LDMOS used in space shuttles, airplanes, etc., to determine its lifetime. </p><p><br></p> <p> </p> <p>We have holistically analyzed the reliability of power transistors by extending the theories of logic transistors in this thesis. Therefore, this thesis takes us a step closer to a generalized reliability model for power transistors by developing a comprehensive and predictive model for the safe operating area, encompassing all sources of stresses (e.g., electrical, thermal, and radiation) it experiences during operation.</p>

Cette thèse de doctorat s’inscrit dans la thématique de la fiabilité des circuits intégrés dans l’industrie de la microélectronique. Un circuit intégré peut être exposé à des agresseurs électriques potentiellement dangereux pendant toute sa durée de vie. Idéalement, les circuits devraient pouvoir encaisser ces excès d’énergie sans perdre leur fonctionnalité. En réalité, des défaillances peuvent être observées lors de tests de qualification ou en application finale. Il est donc dans l’intérêt des fabricants de réduire ces défaillances. Actuellement, il existe des circuits de protection sur puce conçus pour dévier l’énergie de ces agresseurs à l’écart des composants fragiles. Le terme anglophone Electrical Overstress (EOS) englobe tous les agresseurs électriques qui dépassent une limite au-delà de laquelle les composants peuvent être détruits. La définition de ce terme est traitée en détail dans la thèse. L’objectif de cette thèse est de comprendre le statut du sujet des EOS dans l’industrie. On propose ensuite une nouvelle méthodologie de caractérisation de circuits pour quantifier leur robustesse face à des formes d’onde représentatives présélectionnées. On propose également des solutions de circuits de protection sur puce que ce soit au niveau de nouveaux composants actifs ou au niveau de la conception des circuits électroniques de protection. Par exemple on propose un nouveau composant basé sur le thyristor qui a la capacité de s’éteindre même si la tension d’alimentation est présente sur l’anode. Une autre proposition est de désactiver les circuits de protection face aux décharges électrostatiques lorsque les puces sont dans un environnement où l’on est sur ou ces agresseurs ne présentent plus de danger. Finalement, des perspectives du travail de thèse sont citées. / This Ph.D. thesis concerns reliability issues in the microelectronics industry for the most advanced technology nodes. In particular, the Electrical OverStress (EOS) issue is studied. Reducing EOS failures in Integrated Circuits (ICs) is becoming more and more important. However, the EOS topic is very complex and involves many different causes, viewpoints, definitions and approaches. In this context, a complete analysis of the current status of the EOS issue is carried out. Then, the Ph.D. objectives can be defined in a clear way. In particular, robustness increase of on-chip protection structures and IC characterization against EOS-like aggressors are two of the main goals. In order to understand and quantify the behavior of ICs against these aggressors, a dedicated EOS test bench is put in place along with the definition of a characterization methodology. A full characterization and comparison is performed on two different Electro- Static Discharge (ESD) power supply clamps. After identifying the potential weaknesses of the promising Silicon-Controlled Rectifier (SCR) device, a new SCR-based device with a turn-off capability is proposed and studied thanks to 3-D Technology Computer-Aided Design (TCAD)simulation. Triggering and turn-off behaviors are studied, as well as its optimization. Finally, three different approaches are proposed for improving the robustness of the IC onchip protection circuits. They are characterized thanks to the EOS test bench which allows identifying their assets as well as their points of improvement.