Neste trabalho é apresentado um estudo dos transistores MOS sem junções (Junctionless Nanowire Transistors - JNTs), cujo foco é a modelagem de suas características elétricas e a análise do funcionamento dos mesmos quanto à tensão de limiar, ponto invariante com a temperatura e operação analógica. Os JNTs possuem uma concentração de dopantes constante da fonte ao dreno sem apresentar gradientes. Eles foram desenvolvidos a fim de se evitar as implantações iônicas de fonte e dreno, que requerem condições rigorosamente controladas para se evitar a difusão de dopantes para o interior do canal em dispositivos de tamanho extremamente reduzido (sub-20 nm). Dessa forma, esses dispositivos permitem um maior escalamento, com um processo de fabricação simplificado. Os trabalhos recentes de modelagem desses transistores consideram dispositivos de canal longo, de forma geral o comprimento utilizado é de 1 µm, de porta dupla ou cilíndricos. Pouco tem sido feito relacionado à modelagem de JNTs porta tripla e a influência da temperatura no funcionamento dos mesmos. Assim, este trabalho tem como objetivo a modelagem do funcionamento dos dispositivos MOS sem junções de porta tripla quanto à tensão de limiar, potencial de superfície, carga de condução e corrente de dreno. Os modelos são derivados da solução da equação de Poisson com as condições de contorno adequadas, apresentando grande concordância com simulações numéricas tridimensionais e com resultados experimentais para dispositivos com comprimento de canal de até 30 nm. No caso do modelo da tensão de limiar, o maior erro obtido entre modelo e simulação foi de 33 mV, que representa uma percentagem menor que 5 %. Também foi apresentado um método de extração da tensão de limiar baseado na igualdade das componentes de deriva e difusão da corrente de dreno. Este método foi igualmente validado com resultados simulados, apresentando um erro máximo de 3 mV (menor que 0,5 %) e aplicado à dispositivos experimentais. A influência da temperatura na tensão de limiar também foi analisada tanto pelo modelo proposto como por simulações e resultados experimentais, mostrando que a dependência da concentração de dopantes ionizados com a temperatura devido à ionização incompleta dos portadores tem grande influência na tensão de limiar. No caso da modelagem da corrente de dreno e do potencial de superfície, foi acrescentada uma correção de efeitos de canal curto. O erro médio foi menor que 12 % para as curvas de corrente e suas derivadas quando comparadas à dos dispositivos experimentais de comprimento de canal de 30 nm. Também foi realizado um estudo do funcionamento dos JNTs, mostrando que o ponto invariante com a temperatura, onde a corrente de dreno se mantém constante independente da temperatura, pode ou não existir nesses dispositivos dependendo da resistência série e de sua dependência com a temperatura. Por fim, a operação analógica dos dispositivos sem junções é analisada para dispositivos de diferentes dimensões. / In this work, a study of the Junctionless Nanowire Transistors (JNTs) is presented, focusing their modeling and analyzing their operation. The JNTs are heavily doped devices with a doping concentration constant from source to drain, without presenting doping gradients. They have been developed in order to avoid drain and source ion implantation, which requires rigorous controlled conditions to avoid dopants diffusion into the channel in extremely reduced devices (sub-20 nm). Therefore, these devices provide a higher scalability with a simplified fabrication process. Recent works on junctionless nanowire transistors modeling have considered long-channel (a length of 1 µm is commonly used) double-gate or cylindrical devices. Few works have presented the modeling of triple-gate JNTs and the temperature influence on the device operation. The goal of this work is the modeling of the threshold voltage, surface potential, conduction charge and drain current in triple-gate junctionless nanowire transistors. The models are derived from the solution of the Poisson equation with the appropriate boundary conditions and exhibit a great concordance with three-dimensional numerical simulations and experimental data even for devices with channel length of 30 nm. In the case of the threshold voltage, the higher error obtained between model and simulation was 33 mV, which represents an error lower than 5 %. A method for the threshold voltage extraction based on the equality of the drift and diffusion components of the drain current has also been presented. This method was also validated using simulated results, with a maximum error of 3 mV (lower than 0.5 %), and applied to experimental devices. The influence of the temperature on the threshold voltage has also been analyzed through the proposed model, the numerical simulations and the experimental data. It has been shown that the dependence of the ionized dopant concentration with the temperature due to the incomplete carrier ionization has a great influence on the threshold voltage. In the case of the surface potential and drain current modeling, a correction for the short channel effects has been proposed. The mean error has been lower than 12 % for the drain current curves and their derivatives when compared to the ones of experimental devices with a channel length of 30 nm. An analysis on the operation of the JNTs has been also performed, showing that the zero temperature coefficient point, in which the current is the same independent of the temperature, can or not exist depending on the series resistance and its dependence on the temperature. Finally, the operation of junctionless nanowire transistors in analog applications has been analyzed for devices of different dimensions.

This thesis describes the design, fabrication and characterization of AlGaN/GaN Heterostructure Field E ect Transistors (HFETs) grown by a Metal Organic Chemical Vapor Deposition (MOCVD) on sapphire substrates. The objective of this research is to develop AlGaN/GaN power devices with high breakdown voltage (greater than 1 kV) and low turn-on resistance. Various characteristics such as current drive (Idss), transconductance (gm) and threshold voltage (Vth) have also been measured and the results have been discussed. Two major challenges with the development of high breakdown voltage AlGaN/GaN HFETs in the past have been high material defect density and non-optimized fabrication technologies which gives rise to bu er leakage and surface leakage, respectively. In this thesis, mesa isolation, ohmic and gate metal contacts, and passivation techniques, have been discussed to improve the performance of these power transistors in terms of low contact resistance and low gate leakage. The relationship between breakdown voltage and Rds(ON)A with respect to the gate-drain length (Lgd) is also discussed. First, unit cell devices were designed (two-fingered cells with Wg = 100, 300, 400 m) and characterized, and then they were extended to form large area devices (upto Wg = 40 mm). The design goals were classied into three parts: - High Breakdown Voltage: This was achieved by designing devices with variations in Lgd, - Low turn-on resistance: This was achieved by optimizing the annealing temperatures as well as incorporating additional thick metal pads, as well as optimizing the passivation etch recipe, - Low Gate Leakage: The gate leakage was reduced signicantly by using a gate metal with a larger barrier height. All devices with Lgd larger than 10 m exhibited excellent breakdown voltage characteristics of over 800 V, and it progressed as the Lgd increased. The turn-on resistance was also reduced signicantly below 20 m-cm2, for devices with Lgd = 15, 25, and 20 m. The gate leakage was measured for all devices upto 200 V, and was in the range of 10-100 nA, which is one of the best values reported for multi-ngered devices with Lgd in the range of 2.4-5 mm. Some of the key challenges faced in fabrication were determining a better gate metal layer to reduce gate leakage, optimizing the passivation via etch recipe, and reducing surface leakage.

Ce travail de thèse a pour sujet l'étude de transistors en couches minces (TFTs) à base d'Indium Gallium Zinc Oxide (IGZO). Nous nous sommes intéressés au procédé de réalisation des TFTs, et à la caractérisation des couches d'IGZO afin d'obtenir les caractéristiques au plus près de l'état de l'art. Nous avons également étudié le processus de passivation, paramètre identifié comme critique pour stabiliser les TFT et atteindre de bonnes performances.Dans un premier temps, nous avons mis au point les conditions du dépôt de la couche active, et de la réalisation des TFTs. Les analyses morphologiques et structurales ont montré l'absence de cristallites de couche, ainsi qu'une surface peu rugueuse. La densité des porteurs de charge de la couche IGZO diminue lorsque le débit d'oxygène, variable durant son dépôt, augmente. La couche active déposée à 200°C et à 4 sccm d'oxygène présente une densité de porteurs de charge de l'ordre de 1E17 cm-3, valeur adaptée au fonctionnement des TFTs.Dans un second temps, nous avons évalué l'influence d'un recuit sur les caractéristiques des TFTs. Nous avons mis en évidence que le recuit sous oxygène conduit à des TFTs opérationnels, tandis que celui sous azote ou en absence de recuit induisent une suppression de l'effet de champ. Nos études ont également montré qu'une température de recuit de 300°C est favorable aux performances des transistors. Les premiers TFTs présentent des mobilités entre 5 et 15 cm2/Vs, des rapports ION/IOFF de l'ordre de 1E7, et des pentes sous le seuil d'environ 0.3 V/décade. Les tensions de seuil (VT), quant à elles, demeurent faibles donc restent à améliorer.Pour finir, nous avons étudié l'impact d'une couche de passivation sur les TFTs, en raison de la dégradation des caractéristiques de ces derniers dans l'atmosphère ambiante. Les couches de SiO2 (déposée par PECVD) et d'Al2O3 (déposée par ALD) ont été étudiées. Nous avons mis en évidence que ces passivations peuvent dégrader les TFTs au lieu de les protéger. VT tend à se décaler dans le sens négatif lorsque l'on augmente l'épaisseur de la couche d'Al2O3 ou le débit de Silane durant le dépôt du SiO2. Une des raisons principales de ce phénomène est la présence de l'hydrogène généré lors de la passivation. Nous avons évalué les solutions pour éviter la dégradation lors du dépôt et assurer une bonne protection du TFT. / This thesis aims to study thin-film transistors (TFTs) based on Indium Gallium Zinc Oxide (IGZO) in the framework of applications in active matrix flat panel LCD and OLED display. The TFT fabrication process and the characterization of IGZO deposited film are two key studies in this thesis in order to obtain TFT electrical characteristics close to the state-of-the-art. We have also studied the passivation which is identified as crucial for stabilizing the TFT and achieving good performance.The deposition of the active layer and the fabrication process of TFT are firstly studied. Smooth surface of deposited films is demonstrated by AFM and the absence of the crystalline peak of the material is shown by X-ray diffraction. The density of charge carriers decreases with the increase of oxygen flow rate. The active layer deposited at 200°C and at 4 sccm of oxygen flow has a carrier density in the order of 1E17 cm-3 which is suitable for TFT operation. This condition is chosen to fabricate IGZO-based TFT in this thesis.In a second step, we have evaluated the influence of annealing condition on TFTs' electrical characteristics. Annealing in oxygen leads to operational TFTs while doing the same under nitrogen or the absence of annealing suppresses field-effect behavior. Our studies have also shown that annealing temperature of 300°C is suitable to obtain good performance of the transistors. From this study, we have obtained TFTs with high mobility (between 5 and 15 cm2/Vs), high ION/IOFF ratios (about 1E7), and reasonable sub threshold slope (about 0.3 V/decade). The threshold voltage (VT) however remains low (between -4 and -2 V) and needs to be improved.Finally, we have investigated the impact of a passivation layer on the performance of IGZO TFTs. SiO2 film (deposited by PECVD) and Al2O3 film (formed by ALD) were studied. We have observed that such passivation can degrade the TFTs rather than protecting them. Concretely, VT shifts in negative direction when increasing the Al2O3 layer thickness or the silane flow during SiO2 deposition. Principal reason for this shift is the presence of hydrogen which is generated during passivation. We have evaluated some solutions to reduce the degradation during deposition and ensure a good protection of the TFTs.

La miniaturisation des transistors MOSFETs sur silicium massif présente de nombreux enjeux en raison de l'apparition de phénomènes parasites. Notamment, la réduction de la surface des dispositifs entraîne une dégradation de la variabilité de leurs caractéristiques électriques. La technologie planaire totalement désertée, appelée communément FDSOI (pour Fully Depleted Silicon on Insulator), permet d'améliorer le contrôle électrostatique de la grille sur le canal de conduction et par conséquent d'optimiser les performances. De plus, de par la présence d'un canal non dopé, il est possible de réduire efficacement la variabilité de la tension de seuil des transistors. Cela se traduit par un meilleur rendement et par une diminution de la tension minimale d'alimentation des circuits SRAM (pour Static Random Access Memory). Une étude détaillée de la variabilité intrinsèque à cette technologie a été réalisée durant ce travail de recherche, aussi bien sur la tension de seuil (VT) que sur le courant de drain à l'état passant (ISAT). De plus, le lien existant entre la fluctuation des caractéristiques électriques des transistors et des circuits SRAM a été expérimentalement analysé en détail. Une large partie de cette thèse est enfin dédiée à l'investigation de la source de variabilité spécifique à la technologie FDSOI : les fluctuations de l'épaisseur du film de silicium. Un modèle analytique a été développé durant cette thèse afin d'étudier l'influence des fluctuations locales de TSi sur la variabilité de la tension de seuil des transistors pour les nœuds technologiques 28 et 20nm, ainsi que sur un circuit SRAM de 200Mb. Ce modèle a également pour but de fournir des spécifications en termes d'uniformité σTsi et d'épaisseur moyenne µTsi du film de silicium pour les prochains nœuds technologiques. / The scaling of bulk MOSFETs transistors is facing various difficulties at the nanometer era. The variability of the electrical characteristics becomes a major challenge which increases as the device dimensions are scaled down. Fully-Depleted Silicon On Insulator (FDSOI) technology, developed as an alternative to bulk transistors, exhibits a better electrostatic immunity which enables higher performances. Moreover, the reduction of the Random Dopant Fluctuation allows excellent variability immunity for the FDSOI technology due to its undoped channel. It leads to a yield enhancement and a reduction of the minimum supply voltage of SRAM circuits. The variability has been analyzed deeply during this thesis in this technology, both on the threshold voltage (VT) and on the ON-state current (ISAT). The correlation between the electrical characteristics of MOSFETs devices (i.e., the threshold voltage and the standard deviation σVT) and SRAM cells (i.e., the SNM and σSNM) has been investigated thanks to an extensive experimental study and modeling. This purpose of this thesis is also to analyze the specific FDSOI variability source: silicon thickness fluctuations. An analytical model has been developed in order to quantify the impact of local TSi variations on the VT variability for 28 and 20nm technology nodes, as well as on a 200Mb SRAM array. This model also enables to evaluate the silicon thickness mean (µTsi) and standard deviation (σTsi) specifications for next technology nodes.

Logic-in-memory circuits promise to overcome the von-Neumann bottleneck, which constitutes one of the limiting factors to data throughput and power consumption of electronic devices. In the following we present four-input logic gates based on only two ferroelectric FETs (FeFETs) with hafnium oxide as the ferroelectric material. By utilizing two complementary inputs, a XOR and a XNOR gate are created. The use of only two FeFETs results in a compact and nonvolatile design. This realization, moreover, directly couples the memory and logic function of the FeFET. The feasibility of the proposed structures is revealed by electrical measurements of HKMG FeFET memory arrays manufactured in 28nm technology.

Silicon Carbide, a wide band gap (WBG) semiconductor, has pushed electrical limits beyond Silicon (Si) when it comes to power electronics. It has offered the electrification of society showing promise for a greener future. However, owing to higher material defects, particularly at the oxide/semiconductor interface, threshold voltage (VTH) instability has been a persistent problem. This thesis examines the drift in VTH when a bipolar ac gate bias stress is applied to 4H-SiC MOSFETs. For this purpose, a gate stress setup using a gate driver IC is created. This is followed by a measure-stress-measure (MSM) sequence at varying gate voltages to study the effects of VGS,on, VGS,off, and voltage overshoots on the drift. Two critical VGS,off biases are found. The drift is negligible until the first critical point, accelerated, between the first and second bias, and decelerated beyond the second point with degradation of the oxide. Overshoots/undershoots in the gate drive loop shows an excess drift of 37.77% with only undershoots contributing entirely to this percentage. Drift at higher temperature is smaller than at room temperature but with changing slope. After 400 hours of stress at +18/ − 8V, a VTH drift of 17.5% while a RDS,on drift of only 2.5 % is measured. End of life VTH for devices in this thesis show a drift of 280mV at the automotive application switching limit and 500mV at the solar applications switching limit. The findings are intended for better understanding of device performance limits at high switching cycles and voltage biases. / Bredbandgapsmaterialet kiselkarbid har utvidgat gränserna för kraftelektronikens elektriska prestanda jämfört med vad som går att åstadkomma med kisel. Kiselkarbiden har gett nya möjligheter för samhällets elektrifiering vilket är lovande för en grön framtid. På grund av materialdefekter speciellt vid gränsytan mellan kiselkarbid (SiC) och kiseldioxid har det varit ett bestående problem med drivande tröskelspänning. Det här examensarbetet undersöker drift för tröskelspänningen då gate-terminalen i en 4H-SiC MOSFET utsätts för en bipolär alternerande spännings-stress. För detta ändamål har en mätuppställning med en IC-krets för gate-styrning byggts upp. Detta följs av en mät-stress-mät sekvens för varierande gate-source spänningar (VGS) för att studera effekter av VGS,on,VGS,off och spännings-överslängar på tröskelspänningsdriften. Två kritiska nivåer för VGS,off har påvisats. Tröskelspänningsdriften är försumbar före den första nivån, accelererad mellan den första och andra nivån, och retarderad efter den andra nivån med degradering av gate-oxiden. För överslängar och underslängar i gate-spänningen syns en extra tröskelspänningsdrift på 37.77 % där enbart underslängarna bidrar till driften. Tröskelspänningsdriften vid högre temperatur är mindre än vid rumstemperatur men med förändrad lutning för subtröskelspänningskarakteristiken. Efter 400 timmars stress med +18V/-8V, uppmättes en tröskelspänningsdrift på 17.5 % men endast 2.5 % drift för on-resistansen. Vid slutet av förväntad livstid i form av switch-cykler uppmättes 280 mV drift för biltillämpningar och 500 mV för solpanelstillämpningar. Resultaten är ämnade att förbättra förståelsen för komponentprestandans begränsningar efter ett stort antal switch-cykler och olika gate-source spänningar.

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Thin Film Transistors (TFTs) are widely used in large area electronics because they offer the advantage of low cost fabrication and wide substrate choice. TFTs have been conventionally used for switching applications in large area display arrays. But when it comes to designing a sensor actuator system on a flexible substrate comprising entirely of organic and inorganic TFTs, there are two main challenges – i) Fabrication of complementary TFT devices is difficult ii) TFTs have a drift in their threshold voltage (VT) on application of gate bias. Also currently there are no circuit simulators in the market which account for the effect of VT drift with time in TFT circuits. The first part of this thesis focuses on integrating the VT shift model in the commercially available AIM-Spice circuit simulator. This provides a new and powerful tool that would predict the effect of VT shift on nodal voltages and currents in circuits and also on parameters like small signal gain, bandwidth, hysteresis etc. Since the existing amorphous silicon TFT models (level 11 and level 15) of AIM-Spice are copyright protected, the open source BSIM4V4 model for the purpose of demonstration is used. The simulator is discussed in detail and an algorithm for integration is provided which is then supported by the data from the simulation plots and experimental results for popular TFT configurations. The second part of the thesis illustrates the idea of using negative feedback achieved via contact resistance modulation to minimize the effect of VT shift in the drain current of the TFT. Analytical expressions are derived for the exact value of resistance needed to compensate for the VT shift entirely. Circuit to realize this resistance using TFTs is also provided. All these are experimentally verified using fabricated organic P-type Copper Phthalocyanine (CuPc) and inorganic N-type Tin doped Zinc Oxide (ZTO) TFTs. The third part of the thesis focuses on building a robust amplifier using these TFTs which has time invariant DC voltage level and small signal gain at the output. A differential amplifier using ZTO TFTs has been built and is shown to fit all these criteria. Ideas on vertical routing in an actual sensor actuator interface using this amplifier have also been discussed such that the whole system may be “tearable” in any contour. Such a sensor actuator interface can have varied applications including wrap around thermometers and X-ray machines.

Dans les années 2000, les composants de puissance en carbure de silicium (SiC) font leur apparition sur le marché industriel offrant d'excellentes performances. Elles se traduisent par de meilleurs rendements et des fréquences de découpage plus élevées, entrainant une réduction significative du volume et de la masse des convertisseurs de puissance. Le SiC présente de plus un potentiel important de fonctionnement en haute température (>200°C) et permet donc d'envisager de placer l'électronique dans des environnements très contraints jusqu'alors inaccessibles. Pourtant les parts de marche du SiC restent limitées dans l'industrie vis à vis du manque de retour d'expérience concernant la fiabilité de ces technologies relativement nouvelles. Cette question reste aujourd'hui sans réponse et c'est avec cet objectif qu'a été menée cette étude axée sur le vieillissement et l'analyse des mécanismes de dégradation sur des composants de puissance SiC pour des applications haute température. Les tests de vieillissement ont été réalisés sur des transistors MOSFET SiC car ces composants attirent les industriels grâce à leur simplicité de commande et leur sécurité "normalement bloqué" (Normally-OFF). Néanmoins, la fiabilité de l'oxyde de grille est le paramètre limitant de cette structure. C'est pourquoi l'étude de la dérive de la tension de seuil a été mesurée avec une explication du phénomène d'instabilité du VTH. Les résultats ont montré qu'avec l'amélioration des procédés de fabrication, l'oxyde du MOSFET est robuste même pour des températures élevées (jusqu'à 300°C) atteintes grâce à un packaging approprié. Les durées de vie moyennes ont été extraites grâce à un banc de vieillissement accéléré développé pour cette étude. Des analyses macroscopiques ont été réalisées afin d'observer l'évolution des paramètres électriques en fonction du temps. Des études microscopiques sont conduites dans l'objectif d'associer l'évolution des caractéristiques électriques par rapport aux dégradations physiques internes à la puce. Pour notre véhicule de test, la défaillance se traduit par un emballement du courant de grille en régime statique et par l'apparition de fissures dans le poly-Silicium de la grille. Pour finir, une étude de comparaison avec des nouveaux transistors MOSFET a été réalisée. Ainsi l'analogie entre ces composants s'est portée sur des performances statiques, dynamiques, dérivé de la tension de seuil et sur la durée de vie moyenne dans le test de vieillissement. Le fil rouge de ces travaux de recherche est une analyse des mécanismes de dégradation avec une méthodologie rigoureuse permettant la réalisation d'une étude de fiabilité. Ces travaux peuvent servir de base pour toutes analyses d'anticipation de défaillances avec une estimation de la durée de vie extrapolée aux températures de l'application visée / Since 2000, Silicon Carbide (SiC) power devices have been available on the market offering tremendous performances. This leads to really high efficiency power systems, and allows achieving significative improvements in terms of volume and weight, i.e. a better integration. Moreover, SiC devices could be used at high temperature (>200°C). However, the SiCmarket share is limited by the lack of reliability studies. This problem has yet to be solved and this is the objective of this study : aging and failure mechanisms on power devices for high temperature applications. Aging tests have been realized on SiC MOSFETs. Due to its simple drive requirement and the advantage of safe normally-Off operation, SiCMOSFET is becoming a very promising device. However, the gate oxide remains one of the major weakness of this device. Thus, in this study, the threshold voltage shift has been measured and its instability has been explained. Results demonstrate good lifetime and stable operation regarding the threshold voltage below a 300°C temperature reached using a suitable packaging. Understanding SiC MOSFET reliability issues under realistic switching conditions remains a challenge that requires investigations. A specific aging test has been developed to monitor the electrical parameters of the device. This allows to estimate the health state and predict the remaining lifetime.Moreover, the defects in the failed device have been observed by using FIB and SEM imagery. The gate leakage current appears to reflect the state of health of the component with a runaway just before the failure. This hypothesis has been validated with micrographs showing cracks in the gate. Eventually, a comparative study has been realized with the new generations of SiCMOSFET

Speed, power and reliability of analogue integrated circuits (IC) exhibit temperature dependency through the modulation of one or several of the following variables: band gap energy of the semiconductor, mobility, carrier diffusion, current density, threshold voltage, interconnect resistance, and variability in passive components. Some of the adverse effects of temperature variations are observed in current and voltage reference circuits, and frequency drift in oscillators. Thermal instability of a voltage-controlled oscillator (VCO) is a critical design factor for radio frequency ICs, such as transceiver circuits in communication networks, data link protocols, medical wireless sensor networks and microelectromechanical resonators. For example, frequency drift in a transceiver system results in severe inter-symbol interference in a digital communications system. Minimum transconductance required to sustain oscillation is specified by Barkhausen’s stability criterion. However it is common practice to design oscillators with much more transconductance enabling self-startup. As temperature is increased, several of the variables mentioned induce additional transconductance to the oscillator. This in turn translates to a negative frequency drift. Conventional approaches in temperature compensation involve temperature-insensitive biasing proportional-to-absolute temperature, modifying the control voltage terminal of the VCO using an appropriately generated voltage. Improved frequency stability is reported when compensation voltage closely follows the frequency drift profile of the VCO. However, several published articles link the close association between oscillation amplitude and oscillation frequency. To the knowledge of this author, few published journal articles have focused on amplitude control techniques to reduce frequency drift. This dissertation focuses on reducing the frequency drift resulting from temperature variations based on amplitude control. A corresponding hypothesis is formulated, where the research outcome proposes improved frequency stability in response to temperature variations. In order to validate this principle, a temperature compensated VCO is designed in schematic and in layout, verified using a simulation program with integrated circuit emphasis tool using the corresponding process design kit provided by the foundry, and prototyped using standard complementary metal oxide semiconductor technology. Periodic steady state (PSS) analysis is performed using the open loop VCO with temperature as the parametric variable in five equal intervals from 0 – 125 °C. A consistent negative frequency shift is observed in every temperature interval (≈ 11 MHz), with an overall frequency drift of 57 MHz. However similar PSS analysis performed using a VCO in the temperature stabilised loop demonstrates a reduced negative frequency drift of 3.8 MHz in the first temperature interval. During the remaining temperature intervals the closed loop action of the amplitude control loop overcompensates for the negative frequency drift, resulting in an overall frequency spread of 4.8 MHz. The negative frequency drift in the first temperature interval of 0 to 25 °C is due to the fact that amplitude control is not fully effective, as the oscillation amplitude is still building up. Using the temperature stabilised loop, the overall frequency stability has improved to 16 parts per million (ppm)/°C from an uncompensated value of 189 ppm/°C. The results obtained are critically evaluated and conclusions are drawn. Temperature stabilised VCOs are applicable in applications or technologies such as high speed-universal serial bus, serial advanced technology attachment where frequency stability requirements are less stringent. The implications of this study for the existing body of knowledge are that better temperature compensation can be obtained if any of the conventional compensation schemes is preceded by amplitude control. / Dissertation (MEng)--University of Pretoria, 2013. / Electrical, Electronic and Computer Engineering / unrestricted