Wireless body area networks (WBANs) have tremendous potential to benefit from wireless communication technology and are expected to make sweeping changes in the future human health care and medical fields. While the prospects for WBAN products are high, meeting required device performance with a meager amount of power consumption poses significant design challenges. In order to address these issues, IEEE has recently developed a draft of IEEE 802.15.6 standard dedicated to low bit-rate short-range wireless communications on, in, or around the human body. Commercially available SoC (System-on-Chip) devices targeted for WBAN applications typically embed proprietary wireless transceivers. However, those devices usually do not meet the quality of service (QoS), low power, and/or noninterference necessary for WBAN applications, nor meet the IEEE standard specifications. This dissertation presents a design of low-power RF front-end conforming to the IEEE standard in Medical Communication Service (MICS) band of 402-405 MHz. First, we investigated IEEE 802.15.6 PHY specifications for narrow band WBAN applications. System performance analysis and simulation for an AWGN (additive white Gaussian noise) channel was conducted to obtain the BER (bit error rate) and the PER (packet error rate) as the figure of merit. Based on the system performance study, the link budget was derived as a groundwork for our RF front-end design. Next, we examined candidate RF front-end architectures suitable for MICS applications. Based on our study, we proposed to adopt a direct conversion transmitter and a low-IF receiver architecture for the RF front-end. An asynchronous wake-up receiver was also proposed, which is composed of a carrier sensing circuit and a serial code detector. Third, we proposed and implemented low-power building blocks of the proposed RF front-end. Two quadrature signal generation techniques were proposed and implemented for generation of quadrature frequency sources. The two quadrature voltage controlled oscillators (QVCOs) were designed using our proposed current-reuse VCO with two damping resistors. A stacked LNA and a down-conversion mixer were proposed for low supply and low power operation for the receiver front-end. A driver amplifier and an up-conversion mixer for the transmitter front-end were implemented. The proposed driver amplifier uses cascaded PMOS transistors to minimize the Miller effect and enhance the input/output isolation. The up-conversion mixer is based on a Gilbert cell with resistive loads. Simulation results and performance comparisons for each designed building block are presented. Finally, we present a case study on a direct VCO modulation transmitter and a super-regenerative receiver, which can also be suitable for an MICS transceiver. Several crucial building blocks including a digitally-controlled oscillator (DCO) and quench signal generators are proposed and implemented with a small number of external components. / Ph. D.

The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power consumption. Clock generators are essential components in numerous circuits, for instance, frequency synthesizers for high speed transceivers, clock sources for microprocessors, noise suppressed zero-delay buffers in system-on-chips (SOCs), and clock and data recovery (CDR) systems. Furthermore, clock generators are required to provide low jitter and high precision clocks in fully integrated image reject receivers and an ultra-wide tunability in time-interleaved applications. We explore several circuit design techniques and implementations of low jitter clock generator in this thesis. Firstly, a low jitter and wide range digital phase-locked loop (DPLL) operating 8 ~ 16 GHz is illustrated using a dual path digital loop filter (DLF). In order to mitigate the phase jitter in the phase detector (PD), we implement the separate loop filter and the output is not affected by the proportional path. For the stable operation, a 4 ~ 8 GHz linear phase interpolator (PI) is implemented in the proportional path. In addition, we design a low phase noise digitally controlled oscillator (DCO) using inductive tuning technique based on switched mutual coupling for wide operating range. The proposed DPLL implemented in 65 nm CMOS technology shows an outstanding figure-of-merit (FOM) over other state-of-art DPLLs in term of root mean square (RMS) and deterministic jitter (DJ). Secondly, we discuss a radiation-hardened-by-design (RHBD) PLL using a feedback voltage-controlled oscillator (FBVCO) in order to reduce DJ due to the radiation attack on the control voltage. Different from a conventional open loop VCO, the proposed FBVCO has a negative control loop and is composed of an open loop VCO, an integrator and a switched-capacitor resistor. Since the input to output of the FBVCO has a low-pass characteristic, any disturbance on the control voltage should be filtered and cannot affect the output phase. We are able to reduce the output frequency variation approximately 75% compared to the conventional PLL when the radiation pulse strikes on the control voltage. The proposed RHBD PLL is implemented in 130 nm and consumes 6.2 mW at 400 MHz operating frequency. Thirdly, a novel adaptive-bandwidth PLL is illustrated to optimize the jitter performance in a wide operating frequency range. We achieve a constant ratio of bandwidth and reference frequency with a closed loop VCO and an overdamping system with a charge pump (CP) current proportional to the VCO frequency for the adaptive-bandwidth technique. The proposed adaptive-bandwidth PLL presents 0.6% RMS jitter over the entire frequency range from 320 MHz to 2.56 GHz, which is 70% smaller than the conventional fixed-bandwidth PLL. Finally, we have developed a new feedback DCO to achieve a linear gain of DCO so that the DPLL can provide stability and a wide operating range in different process variations. Due to the negative feedback loop of the proposed DCO, the feedback DCO presents a linear gain from an input digital word to an output frequency. Moreover, we can control the bandwidth of the feedback DCO to optimize the total output phase noise in DPLL. In simulation, we can obtain 17 MHz/LSB of the peak-to-peak gain of the feedback DCO, which is reduced 96% over the conventional DCO.

No description available.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.

Wireless communication is witnessing tremendous growth with the proliferation of various standards covering wide, local, and personal area networks, which operate at different frequency bands. Future wireless terminals will not only need to support multiple standards, but also need to be multi-functional to keep pace with the demands of the consumers. For such an implementation, the local oscillator (LO) turns out to be the bottleneck, which must exhibit frequency agility by generating a very wide range of carrier frequencies in order to access all the specified communication standards. This dissertation presents various design techniques to realize compact low-cost low-power and broadband oscillators in silicon-based technologies. The two most suitable techniques for broadband signal generation: (1) Use of widely tunable active inductor, and (2) Use of switched resonator have been thoroughly evaluated. A fully reconfigurable active inductor with a widely tunable feedback resistor has been proposed. Using the proposed tunable active inductor in a VCO generates frequency tuning ranges higher than 100%, and helps achieve the highest PFTN Figure-of-Merit among Si-based active inductor VCOs reported in literature till date. The large-signal non-linearity of the active inductor has been utilized to develop the first reported broadband harmonic active inductor-based VCO. The degradation of phase noise due to active inductors is partially solved by a noise optimization guideline for active inductors. Utilizing the low saturation voltage of HBT technologies and high-Q short line inductors seems to be very useful to reduce power consumption of cross-coupled VCOs while achieving low phase noise performance simultaneously.

In this thesis, we present a new continuously variable high frequency standing wave oscillator and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by coarse and fine tuning. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator ring were extracted with skin effect accounted for. Our PLL provides a frequency locking range from 6 GHz to 9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56 percent. These numbers are significant improvements over the prior art in standing wave based PLLs.

High-speed serial data links are quickly gaining in popularity and replacing the conventional parallel data links in recent years when the data rate of communication exceeds one gigabits per second. Compared with parallel data links, serial data links are able to achieve higher data rate and longer transfer distance. This dissertation is focused on the design of CMOS integrated phase-locked loops (PLLs) and relevant building blocks used in multi-gigabits serial data link transceivers. Firstly, binary phase-locked loops (BPLLs, i.e., PLLs based on binary phase detectors) are modeled and analyzed. The steady-state behavior of BPLLs is derived with combined discrete-time and continuous-time analysis. The jitter performance characteristics of BPLLs are analyzed. Secondly, a 10 Gbps clock and data recovery (CDR) chip for SONET OC- 192, the mainstream standard for optical serial data links, is presented. The CDR is based on a novel referenceless dual-loop half-rate architecture. It includes a binary phase-locked loop based on a quad-level phase detector and a linear frequency-locked loop based on a linear frequency detector. The proposed architecture enables the CDR to achieve large locking range and small jitter generation at the same time. The prototype is implemented in 0.18 μm CMOS technology and consumes 250 mW under 1.8 V supply. The jitter generation is 0.5 ps-rms and 4.8 ps-pp. The jitter peaking and jitter tolerance performance exceeds the specifications defined by SONET OC-192 standard. Thirdly, a fully-differential divide-by-eight injection-locked frequency divider with low power dissipation is presented. The frequency divider consists of a four-stage ring of CML (current mode logic) latches. It has a maximum operating frequency of 18 GHz. The ratio of locking range over center frequency is up to 50%. The prototype chip is implemented in 0.18 μm CMOS technology and consumes 3.6 mW under 1.8 V supply. Lastly, the design and optimization techniques of fully differential charge pumps are discussed. Techniques are proposed to minimize the nonidealities associated with a fully differential charge pump, including differential mismatch, output current variation, low-speed glitches and high-speed glitches. The performance improvement brought by the techniques is verified with simulations of schematics designed in 0.35 μm CMOS technology.

No description available.

Η ανάγκη για ολοκληρωμένα κυκλώματα που λειτουργούν σε υψηλές συχνότητες/ταχύτητες πηγάζει από το γεγονός ότι οι τηλεπικοινωνιακές εφαρμογές νέας γενιάς βασίζονται στη μετάδοση και τη λήψη δεδομένων με πολύ μεγάλους ρυθμούς. Οι υλοποιήσεις των εφαρμογών αυτών σε τεχνολογίες πυριτίου παρουσιάζουν μεγάλες σχεδιαστικές προκλήσεις. Στα πλαίσια της παρούσης διδακτορικής διατριβής, έχοντας κατά νου τις παραπάνω προκλήσεις, αρχικά παρουσιάζεται μια αναλυτική διαδικασία για την εξαγωγή των παραμέτρων μετάδοσης διαφορικών γραμμών μεταφοράς υλοποιημένων σε τεχνολογία πυριτίου. Η μέθοδος αυτή βασίζεται στη χρήση των παραμέτρων σκέδασης μεικτού ρυθμού και έχει το πλεονέκτημα ότι εξάγει τα χαρακτηριστικά των διαφορικών γραμμών μεταφοράς χωρίς τη χρήση επαναληπτικών μεθόδων. Ένα άλλο θέμα που πραγματεύεται η παρούσα διατριβή είναι μια μεθοδολογία βαθμονόμησης (calibration) για την αύξηση της ακρίβειας ηλεκτρομαγνητικού εξομοιωτή στην εξαγωγή των παραμέτρων που έχουν παθητικά στοιχεία (γραμμές μεταφοράς και σπειροειδείς επαγωγοί υλοποιημένα σε τεχνολογία πυριτίου). Οι δύο παραπάνω μεθοδολογίες χρησιμοποιήθηκαν για τη σχεδίαση και την υλοποίηση πλήρως διαφορικού κατανεμημένου ταλαντωτή ελεγχόμενου από τάση σε τεχνολογία πυριτίου 0.35μm SiGe BiCMOS. Για τη ρύθμιση της συχνότητας χρησιμοποιείται η τεχνική της μεταβολής καθυστέρησης με την αρωγή θετικής ανάδρασης. Η συνεισφορά της παρούσης διδακτορικής διατριβής είναι ότι ο παραπάνω ταλαντωτής είναι ο πρώτος πλήρως ολοκληρωμένος κατανεμημένος διαφορικός ταλαντωτής. / The demand for high speed/high frequency integrated circuits stems from the fact that modern communication applications require high bit rate data transfer. The implementations of these applications on silicon based technologies impose several design challenges. This dissertation tries to address some of these issues. First, we propose a direct parameter extraction procedure for the case of symmetrical differential transmission lines. This method is based on the mixed-mode S-parameter theory and its main advantage is the fact that it doesn’t use any kind repetitive algorithms. Another issue that this dissertation addresses is a calibration methodology for the augmentation of the parameter extraction accuracy of high frequency passive elements (transmission lines and spiral inductors) when an electromagnetic simulator is used. The abovementioned methodologies were utilized in the design and implementation of a fully integrated differential distributed voltage controlled oscillator in a 0.35 μm SiGe BiCMOS technology. As a frequency tuning technique the delay variation by positive feedback is used. The main contribution of this dissertation is the fact that this oscillator is the first fully integrated differential distributed oscillator.

A Voltage Controlled Oscillator (VCO) based pixel and array architecture is reported using amorphous silicon (a-Si) technology for large area digital imaging applications. The objectives of this research are to (a) demonstrate photon quantum noise limited pixel operation of less than 30 input referred noise electrons, (b) theoretically explore the use of the proposed VCO pixel architecture for photon quantum noise limited large area imaging applications, more specifically protein crystallography using a-Si, (c) to implement and demonstrate experimentally a quantum noise limited (VCO) pixel, a small prototype of quantum noise limited (VCO) pixelated array and a quantum noise limited (VCO) pixel integrated with direct detection selenium for energies compatible with a protein crystallography application. Electronic noise (phase noise) and metastability performance of VCO pixels in low cost, widely available a-Si technology will be theoretically calculated and measured for the first time in this research. The application of a VCO pixel architecture in thin film technologies to large area imaging modalities will be examined and a small prototype a-Si array integrated with an overlying selenium X-ray converter will be demonstrated for the first time. A-Si and poly-Si transistor technologies are traditionally considered inferior in performance to crystalline silicon, the dominant semiconductor technology today. This work v aims to extend the reach of low cost, thin film transistor a-Si technology to high performance analog applications (i.e. very low input referred noise) previously considered only the domain of crystalline silicon type semiconductor. The proposed VCO pixel architecture can enable large area arrays with quantum noise limited pixels using low cost thin film transistor technologies.