Le travail présenté dans ce mémoire traite de l’étude comportementale, de la conception et de la validation d’une nouvelle architecture, basée sur le couplage d’O.C.T différentiels, appliquée à la commande électronique de l’orientation du diagramme de rayonnement d’un réseau d’antennes linéaire. Après avoir optimisé la structure de l’O.C.T différentiel, qui constitue le corps du circuit de commande, selon une méthode graphique qui visualise les différentes contraintes imposées par le système afin de minimiser son bruit de phase et sa consommation, l’O.C.T à sorties différentielles a été réalisé en technologie NXP BiCMOS SiGe 0,25 μm puis mesuré en boîtier. Etant donné que la direction de rayonnement d’une antenne réseau dépend de la valeur du déphasage imposé entre les signaux envoyés sur deux antennes adjacentes, les équations théoriques modélisant deux O.C.T couplés et permettant d’extraire les amplitudes et le déphasage entre les différents signaux ont été décrites. La dernière étape a alors consisté en la réalisation de deux réseaux constitués respectivement de deux et de quatre O.C.T couplés au moyen d’une résistance puis d’un transistor MOS fonctionnant en zone ohmique. L’approche de couplage proposée a été validée en se basant sur les résultats de mesures effectués. De plus, l’impact de l’utilisation de structures différentielles sur la plage de déphasage obtenue et donc sur le dépointage réalisé a également été présenté ce qui nous a permis de conclure sur l’efficacité du circuit de commande proposé. / The work presented in this thesis deals with the study, design, and validation of a new architecture based on the coupling of differential voltage controlled oscillators (VCO) applied to the beamsteering of a linear antenna array. After optimizing the differential VCO structure, with a graphical optimization approach while satisfying design constraints imposed, in order to minimize the phase noise and power consumption, the differential VCO was realized in NXP BiCMOS SiGe 0.25 µm process and then measured. Since the radiation direction of an antenna array depends on the phase difference imposed between the two signals on adjacent antennas, the theoretical equations modeling two coupled VCOs, and allowing the extraction of the amplitude and phase difference between the outputs signals have been presented. The last step was the realization of two arrays consisting respectively of two and four VCOs coupled through a resistor and a MOS transistor operating in the triode region. The proposed coupling approach is validated based on the obtained measurement results. Furthermore, the impact of the use of differential structures on the phase shift range obtained and thus on the beam-scanning range achieved was also presented allowing to conclude on the efficiency of the proposed architecture.

Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today‟s circuits design. An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point. A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 µm mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators. iv A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO. A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.

A novel scheme of optimizing the individual components of a phase locked loop (PLL) which is used for stable clock generation and synchronization of signals is considered in this work. Verilog-A is used for the high level system design of the main components of the PLL, followed by the individual component wise optimization. The design of experiments (DOE) approach to optimize the analog, 45nm voltage controlled oscillator (VCO) is presented. Also a mixed signal analysis using the analog and digital Verilog behavior of components is studied. Overall a high level system design of a PLL, a systematic optimization of each of its components, and an analog and mixed signal behavioral design approach have been implemented using cadence custom IC design tools.

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The last two decades have witnessed the CMOS processes and design techniques develop and prosper with unprecedented speed. They have been widely employed in contemporary integrated circuit (IC) commercial products resulting in highly added value. Tremendous e orts have been devoted to extend and optimize the CMOS process and its application for future wireless communication systems. Meanwhile, the last twenty years have also seen the fast booming of the wireless communication technology typically characterized by the mobile communication technology, WLAN technology, WPAN technology, etc. Nowadays, the spectral resource is getting increasingly scarce, particularly over the frequency from 0.7 to 6 GHz, whether the employed frequency band is licensed or not. To combat this dilemma, the ultra wideband (UWB) technology emerges to provide a promising solution for short-range wireless communication while using an unlicensed wide band in an overlay manner. Another trend of obtaining more spectrum is moving upwards to higher frequency bands. The WiFi-Alliance has already developed a certi cation program of the 60-GHz band. On the other side, millimeterwave (mmWave) frequency bands such as 28-GHz, 38-GHz, and 71-GHz are likely to be licensed for next generation wireless communication networks. This new trend poses both a challenge and opportunity for the mmWave integrated circuits design. This thesis combines the state-of-the-art IC and hardware technologies and design techniques to implement and propose UWB and 5G prototyping systems. First of all, by giving a thorough analysis of a transmitted reference pulse cluster (TRPC) scheme and mathematical modeling, a TRPC-UWB transceiver structure is proposed and its features and speci cations are derived. Following that, the detailed design, fabrication and veri cation of the TRPC-UWB transmitter front end and wideband voltage-controlled oscillators (VCOs) in CMOS process is presented. The TRPCUWB transmitter demonstrates a state-of-the-art energy e ciency of 38.4 pJ/pulse. Secondly, a novel system architecture named distributed phased array based MIMO (DPA-MIMO) is proposed as a solution to overcome design challenges for the future 5G cellular user equipment (UE) design. In addition, a prototyping design of on-chip mmWave antenna with radiation e ciency enhancement is presented for the IEEE 802.11ad application. Furthermore, two wideband K-band VCO prototypes based on two di erent topologies are designed and fabricated in a standard CMOS process. They both show good performance at center frequencies of 22.3 and 26.1 GHz. Finally, two CMOS mmWave VCO prototypes working at the potential future 5G frequency bands are presented with measurement results. / Graduate / 2018-04-30 / amenghym@gmail.com

Depuis 2002, différentes bandes de fréquences de plusieurs GHz dites « Ultra-Large Bande » (ULB), généralement comprises entre 3,1GHz et 10,6GHz, ont été libérées de par le monde pour la transmission d’informations sans fil. La largeur de ces bandes est telle qu’il devient envisageable d’utiliser des impulsions comme support de l’information en lieu et place d’une porteuse modulée comme cela est le cas habituellement. En effet, le spectre d’une impulsion étant inversement proportionnel à sa durée, une large plage de fréquences est requise pour la transmission d’informations via des impulsions. Cependant, il devient possible d’accroitre les débits en rapprochant les impulsions émises lorsque ceci est nécessaire, tout en offrant la possibilité d’éteindre les circuits et donc réduire la consommation lorsque deux impulsions sont suffisamment éloignées dans le temps.Le travail de recherche de cette thèse est dans ce contexte de proposer une structure d’émetteur impulsionnel reconfigurable disposant d’un contrôle suffisamment fin pour s’adapter aux différents canaux des standards IEEE 802.15.4 et 802.15.6 et ce, en n’utilisant que des circuits numériques pour les besoins des applications faibles coût. Pour cela, une étude théorique sur la mise en forme des impulsions requises est faite. Puis, il est question de la conception des différentes fonctions nécessaires à la mise en œuvre d’un émetteur impulsionnel reconfigurable, telles qu’un oscillateur contrôlé en tension pour la bande 3,1GHz-10,6GHz à démarrage rapide et que le circuit de mise en forme des oscillations associé. / Since 2002, various frequency bands of several GHz called "Ultra-WideBand" (UWB), generally between 3,1GHz and 10,6GHz, were liberalized in the world for wireless data transmission. The width of these bands is that it becomes possible to use pulses instead of a modulated carrier to transmit data. Indeed, as the spectrum of a pulse is inversely proportional to its duration, a wide range of frequencies is required for the transmission of information via pulses. However, it becomes possible to increase the rates by moving closer the emitted pulses when this is necessary, while providing the ability to switch off the circuits and thus reduce power consumption when two pulses are sufficiently far in time.To standardize the use of UWB frequency bands, standards such as IEEE 802.15.4 and 802.15.6 standards have emerged and have chosen to cut these frequency bands in channels of 500MHz and more. The aim of this thesis is also to propose a reconfigurable pulse transmitter structure with a fine enough control to address the different channels of IEEE 802.15.4 and 802.15.6 standard and, using only digital circuits to target low cost applications. For this, a theoretical study on the shaping of pulses required is made. Then it comes to the design of the various functions necessary for the implementation of a reconfigurable pulse transmitter, such as the implementation of a voltage controlled oscillator for 3,1GHz band-10,6GHz with quick start ability and the required oscillations shaping circuit.

Le travail présenté dans ce mémoire traite de l'étude d'oscillateurs et d'Oscillateurs Contrôlés en Tension (OCT) différentiels couplés appliqués à la commande d'un réseau d’antennes linéaire. Après avoir rappelé les concepts d'antennes réseaux et d'oscillateurs, une synthèse de la théorie élaborée par R. York et donnant les équations dynamiques modélisant deux oscillateurs de Van der Pol couplés par un circuit résonnant a été présentée. Après avoir montré la limitation de cette approche concernant la prédiction de l'amplitude des oscillateurs, une nouvelle formulation des équations non linéaires décrivant les états de synchronisation a été proposée. Néanmoins, compte tenu du caractère trigonométrique et fortement non linéaire de ces équations, une nouvelle écriture facilitant la résolution numérique a été proposée. Ceci a permis l'élaboration d'un outil de Conception Assistée par Ordinateur (CAO) fournissant une cartographie de la zone de synchronisation de deux oscillateurs de Van der Pol couplés. Celle-ci permet de déterminer rapidement les fréquences d'oscillation libres nécessaires à l'obtention du déphasage souhaité. Pour ce faire, une procédure de modélisation de deux oscillateurs et OCTs différentiels couplés, par deux oscillateurs de Van der Pol couplés par une résistance a été élaborée. Les résultats fournis par l'outil de CAO proposé ont ensuite été comparés avec les résultats de simulations de deux oscillateurs et OCTs différentiels couplés obtenus avec le logiciel ADS d'Agilent. Une très bonne concordance des résultats a alors été obtenue montrant ainsi l'utilité et la précision de l'outil présenté. / The work presented in this thesis deals with the study of coupled differential oscillators and Voltage Controlled Oscillators (VCO) used to control antenna arrays. After reminding the concept of antenna arrays and oscillators, an overview of R. York's theory giving the dynamics for two Van der Pol oscillators coupled through a resonant network was presented. Then, showing the limitation of this approach regarding the prediction of the oscillators' amplitudes, a new formulation of the nonlinear equations describing the oscillators' locked states was proposed. Nevertheless, due to the trigonometric and strongly non-linear aspect of these equations, mathematical manipulations were applied in order to obtain a new system easier to solve numerically. This has allowed to the elaboration of a Computer Aided Design (CAD) tool, which provides a cartography giving the frequency locking region of two coupled differential Van der Pol oscillators. This cartography can help the designer to rapidly find the free-running frequencies of the two outermost differential oscillators or VCOs of the array required to achieve the desired phase shift. To do so, a modeling procedure of two coupled differential oscillators and VCOs as two coupled differential Van der Pol oscillators, with a resistive coupling network was performed. Then, in order to validate the results provided by our CAD tool, we compared them to the simulation results of two coupled differential oscillators and VCOs obtained with Agilent’s ADS software. Good agreements between the simulations of the circuits, the models and the theoretical results from our CAD tool were found.

The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator. The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis. Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area. Copyright / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

This work explores the topic of digital audio signal processing for modular synthesizers and the design of digital oscillator for modular standard known as Eurorack. Introduction of the theoretical part is dedicated to basic terms and blocks used in modular synthesizers. The thesis also characterizes and presents the methods of sound synthesis. The second part of the theory concerns analog and digital signal conversion made by digital signal processors DSP, focusing on ARM with focus on ARM architecture. The practical part of the thesis concerns design and construction of the digital oscillator which generates periodic waveforms without aliasing distortion. The oscillator also allows several types of modulations and waveforming and the module has several inputs for connecting control voltages or external audio signals.

Goal of this doctoral thesis is to focus to understand of behavior of working of basic electronics circuits and to appoint which parameters of these circuits is possible to control using external digital system. Further the examples of some digitally controlled analog circuits are present and the analysis of these circuits is achieved. Some of these blocks are realized and the results of that’s measuring is presented.