Because of IC technology evolution and the increase of market demand, the communication industry grows vigorously in recent years. The voltage-controlled oscillator plays a key role in the RF transceiver and provides oscillation signals needed for upconversin and downconvertion. Usually, we separate the signals into I/Q channels for modulation and demodulation in upconversin and downconvertion. Because the quality of the local oscillator influences the performance of communication system, designing a voltage-controlled oscillator that can provide two identical signals in accurate quadrature is necessary. In this thesis, a new quadrature voltage-controlled oscillator is presented. We use two identical relaxation oscillators with adjustable Schmitt triggers to construct the cross-coupled architecture. This oscillator has accurate ( <1¢X) and stable quadrature outputs which are independent of operating frequency and process variations. This oscillator circuit is fabricated in TSMC 0.35£gm CMOS Mixed-Signal process provided by National Chip Implementation Center (CIC). Our design is verified by simulation and measurement results.

The competitive market of wireless communication devices demands low power and low cost RF solutions. A quadrature local oscillator (LO) is an essential building block for most transceivers. As the CMOS technology scales deeper into the nanometer regime, design of a low-power low-voltage quadrature LO still poses a challenge for RF designers. This dissertation investigates a new quadrature LO topology featuring a transformer-based voltage controlled oscillator (VCO) stacked with a divide-by-two for low-power low-voltage wireless applications. The transformer-based VCO core adopts the Armstrong VCO configuration to mitigate the small voltage headroom and the noise coupling. The LO operating conditions, including the start-up condition, the oscillation frequency, the voltage swing and the current consumption are derived based upon a linearized small-signal model. Both linear time-invariant (LTI) and linear time-variant (LTV) models are utilized to analyze the phase noise of the proposed LO. The results indicate that the quality factor of the primary coil and the mutual inductance between the primary and the secondary coils play an important role in the trade-off between power and noise. The guidelines for determining the parameters of a transformer are developed. The proposed LO was fabricated in 65 nm CMOS technology and its die size is about 0.28 mm2. The measurement results show that the LO can work at 1 V supply voltage, and its operation is robust to process and temperature variations. In high linearity mode, the LO consumes about 2.6 mW of power typically, and the measured phase noise is -140.3 dBc/Hz at 10 MHz offset frequency. The LO frequency is tunable from 1.35 GHz to 1.75 GHz through a combination of a varactor and an 8-bit switched capacitor bank. The proposed LO compares favorably to the existing reported LOs in terms of the figure of merit (FoM). More importantly, high start-up gain, low power consumption and low voltage operation are achieved simultaneously in the proposed topology. However, it also leads to higher design complexity. The contributions of this work can be summarized as 1) proposal of a new quadrature LO topology that is suitable for low-power low-voltage wireless applications, 2) an in-depth circuit analysis as well as design method development, 3) implementation of a fully integrated LO in 65 nm CMOS technology for GPS applications, 4) demonstration of high performance for the design through measurement results. The possible future improvements include the transformer optimization and the method of circuit analysis. / Ph. D.

Advanced achievements in the area of RF circuit design led to a significant increase in availability of wireless communications in everyday life. However, the rapid growth in utilizing the RF equipment has brought several challenges in different aspects of RF circuit design. This has been motivating researchers to introduce solution to cope with these challenges and further improve the performance of the RF circuits. In this dissertation, we focus on the improvements in three aspects of the circuit design. High temperature and temperature compensated transmitter design, ultra-low phase noise signal generators, and compact and low complexity polar transmitter design. Increase in the ambient temperature can impact the performance of the entire communication system. However, the RF hardware is main part of the system that is under the impact of the temperature variations in which it can change the characteristics of the individual building blocks of the RF chain. Moreover, transistors are the main elements in the circuit whose performance variation must be consider when the design target is compensating the temperature effects. The influence of the temperature variation is studied on the transistors and the building blocks in order to find the most effective approaches to compensate these variations and stabilize the performance of the RF chain at temperatures up to 220 C. A temperature sensor is designed to sense these variations and adjust the characteristics of the circuit components (e.g. bias voltages), accordingly. Further, a new variable gain phase shifter (VGPS) architecture is introduced toward minimizing the temperature impact on its performance in a phased-array transmitter architecture. Finally, a power amplifier as the last stage in a transmitter chain is designed and the variation in its performance with temperature is compensated through the VGPS stage. The transmitter is prototyped to evaluate its performance in practice. Another contribution of this dissertation is to introduce a novel voltage-controlled oscillator (VCO) structure to reduce the phase noise level below state-of-the-art. The noise to phase noise mechanism in the introduced doubly tuned oscillator is studied using linear time-variant (LTV) theory to identify the dominant noise sources and either eliminate or suppress these noise sources by introducing effective mechanism such as impedance scaling. The designed VCO is fabricated and measurement results are carried out that justified the accuracy of the analyses and effectiveness of the introduced design approach. Lastly, we introduce a compact and simple polar transmitter architecture. This type of transmitters was firstly proposed to overcome the serious shortcomings in the IQ transmitters, such as IQ imbalance and carrier leakage. However, there is still several challenges in their design. We introduce a transmitter architecture that operates based on charge to phase translation mechanism in the oscillator. This leads to significantly reduction in the design complexity, die area, and power dissipation. Further, it eliminates a number of serious issues in the design such as sampling rate of the DACs. comprehensive post-layout simulations were also performed to evaluate its performance. / Doctor of Philosophy / To keep up with the ever-growing demand for exchanging information through a radio frequency (RF) wireless network, the specification of the communication hardware (i.e. transmitter and receiver) must be improved as the bottleneck of the system. This has been motivating engineers to introduce new and efficient approaches toward this goal. In this dissertation however, we study three aspects of the circuit design. First, variation in the ambient temperature can significantly degrade the performance of the communication system. Therefore, we study these variations on the performance of the transmitter at high temperature (i.e. above 200 C). Then, the temperature compensation approaches are introduced to minimize the impact of the temperature changes. The effectiveness of the introduced techniques are validated through measurements of the prototyped transmitter. Second, signal generators (i.e. oscillators) are the inseparable blocks of the transmitters. Phase noise is one of the most important specifications of the oscillators that can directly be translated to the quality and data rate of the communication. A new oscillator structure targeting ultra-low phase noise is introduced in the second part of this dissertation. The designed oscillator is fabricated and measured to evaluate its performance. Finally, a new polar transmitter architecture for low power applications is introduced. The transmitter offers design simplicity and compact size compared to other polar transmitter architectures while high performance.

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No description available.

Le travail présenté dans ce mémoire traite de l’étude comportementale, de la conception et de la validation d’une nouvelle architecture, basée sur le couplage d’O.C.T différentiels, appliquée à la commande électronique de l’orientation du diagramme de rayonnement d’un réseau d’antennes linéaire. Après avoir optimisé la structure de l’O.C.T différentiel, qui constitue le corps du circuit de commande, selon une méthode graphique qui visualise les différentes contraintes imposées par le système afin de minimiser son bruit de phase et sa consommation, l’O.C.T à sorties différentielles a été réalisé en technologie NXP BiCMOS SiGe 0,25 μm puis mesuré en boîtier. Etant donné que la direction de rayonnement d’une antenne réseau dépend de la valeur du déphasage imposé entre les signaux envoyés sur deux antennes adjacentes, les équations théoriques modélisant deux O.C.T couplés et permettant d’extraire les amplitudes et le déphasage entre les différents signaux ont été décrites. La dernière étape a alors consisté en la réalisation de deux réseaux constitués respectivement de deux et de quatre O.C.T couplés au moyen d’une résistance puis d’un transistor MOS fonctionnant en zone ohmique. L’approche de couplage proposée a été validée en se basant sur les résultats de mesures effectués. De plus, l’impact de l’utilisation de structures différentielles sur la plage de déphasage obtenue et donc sur le dépointage réalisé a également été présenté ce qui nous a permis de conclure sur l’efficacité du circuit de commande proposé. / The work presented in this thesis deals with the study, design, and validation of a new architecture based on the coupling of differential voltage controlled oscillators (VCO) applied to the beamsteering of a linear antenna array. After optimizing the differential VCO structure, with a graphical optimization approach while satisfying design constraints imposed, in order to minimize the phase noise and power consumption, the differential VCO was realized in NXP BiCMOS SiGe 0.25 µm process and then measured. Since the radiation direction of an antenna array depends on the phase difference imposed between the two signals on adjacent antennas, the theoretical equations modeling two coupled VCOs, and allowing the extraction of the amplitude and phase difference between the outputs signals have been presented. The last step was the realization of two arrays consisting respectively of two and four VCOs coupled through a resistor and a MOS transistor operating in the triode region. The proposed coupling approach is validated based on the obtained measurement results. Furthermore, the impact of the use of differential structures on the phase shift range obtained and thus on the beam-scanning range achieved was also presented allowing to conclude on the efficiency of the proposed architecture.

The last two decades have witnessed the CMOS processes and design techniques develop and prosper with unprecedented speed. They have been widely employed in contemporary integrated circuit (IC) commercial products resulting in highly added value. Tremendous e orts have been devoted to extend and optimize the CMOS process and its application for future wireless communication systems. Meanwhile, the last twenty years have also seen the fast booming of the wireless communication technology typically characterized by the mobile communication technology, WLAN technology, WPAN technology, etc. Nowadays, the spectral resource is getting increasingly scarce, particularly over the frequency from 0.7 to 6 GHz, whether the employed frequency band is licensed or not. To combat this dilemma, the ultra wideband (UWB) technology emerges to provide a promising solution for short-range wireless communication while using an unlicensed wide band in an overlay manner. Another trend of obtaining more spectrum is moving upwards to higher frequency bands. The WiFi-Alliance has already developed a certi cation program of the 60-GHz band. On the other side, millimeterwave (mmWave) frequency bands such as 28-GHz, 38-GHz, and 71-GHz are likely to be licensed for next generation wireless communication networks. This new trend poses both a challenge and opportunity for the mmWave integrated circuits design. This thesis combines the state-of-the-art IC and hardware technologies and design techniques to implement and propose UWB and 5G prototyping systems. First of all, by giving a thorough analysis of a transmitted reference pulse cluster (TRPC) scheme and mathematical modeling, a TRPC-UWB transceiver structure is proposed and its features and speci cations are derived. Following that, the detailed design, fabrication and veri cation of the TRPC-UWB transmitter front end and wideband voltage-controlled oscillators (VCOs) in CMOS process is presented. The TRPCUWB transmitter demonstrates a state-of-the-art energy e ciency of 38.4 pJ/pulse. Secondly, a novel system architecture named distributed phased array based MIMO (DPA-MIMO) is proposed as a solution to overcome design challenges for the future 5G cellular user equipment (UE) design. In addition, a prototyping design of on-chip mmWave antenna with radiation e ciency enhancement is presented for the IEEE 802.11ad application. Furthermore, two wideband K-band VCO prototypes based on two di erent topologies are designed and fabricated in a standard CMOS process. They both show good performance at center frequencies of 22.3 and 26.1 GHz. Finally, two CMOS mmWave VCO prototypes working at the potential future 5G frequency bands are presented with measurement results. / Graduate / 2018-04-30 / amenghym@gmail.com

Le travail présenté dans ce mémoire traite de l'étude d'oscillateurs et d'Oscillateurs Contrôlés en Tension (OCT) différentiels couplés appliqués à la commande d'un réseau d’antennes linéaire. Après avoir rappelé les concepts d'antennes réseaux et d'oscillateurs, une synthèse de la théorie élaborée par R. York et donnant les équations dynamiques modélisant deux oscillateurs de Van der Pol couplés par un circuit résonnant a été présentée. Après avoir montré la limitation de cette approche concernant la prédiction de l'amplitude des oscillateurs, une nouvelle formulation des équations non linéaires décrivant les états de synchronisation a été proposée. Néanmoins, compte tenu du caractère trigonométrique et fortement non linéaire de ces équations, une nouvelle écriture facilitant la résolution numérique a été proposée. Ceci a permis l'élaboration d'un outil de Conception Assistée par Ordinateur (CAO) fournissant une cartographie de la zone de synchronisation de deux oscillateurs de Van der Pol couplés. Celle-ci permet de déterminer rapidement les fréquences d'oscillation libres nécessaires à l'obtention du déphasage souhaité. Pour ce faire, une procédure de modélisation de deux oscillateurs et OCTs différentiels couplés, par deux oscillateurs de Van der Pol couplés par une résistance a été élaborée. Les résultats fournis par l'outil de CAO proposé ont ensuite été comparés avec les résultats de simulations de deux oscillateurs et OCTs différentiels couplés obtenus avec le logiciel ADS d'Agilent. Une très bonne concordance des résultats a alors été obtenue montrant ainsi l'utilité et la précision de l'outil présenté. / The work presented in this thesis deals with the study of coupled differential oscillators and Voltage Controlled Oscillators (VCO) used to control antenna arrays. After reminding the concept of antenna arrays and oscillators, an overview of R. York's theory giving the dynamics for two Van der Pol oscillators coupled through a resonant network was presented. Then, showing the limitation of this approach regarding the prediction of the oscillators' amplitudes, a new formulation of the nonlinear equations describing the oscillators' locked states was proposed. Nevertheless, due to the trigonometric and strongly non-linear aspect of these equations, mathematical manipulations were applied in order to obtain a new system easier to solve numerically. This has allowed to the elaboration of a Computer Aided Design (CAD) tool, which provides a cartography giving the frequency locking region of two coupled differential Van der Pol oscillators. This cartography can help the designer to rapidly find the free-running frequencies of the two outermost differential oscillators or VCOs of the array required to achieve the desired phase shift. To do so, a modeling procedure of two coupled differential oscillators and VCOs as two coupled differential Van der Pol oscillators, with a resistive coupling network was performed. Then, in order to validate the results provided by our CAD tool, we compared them to the simulation results of two coupled differential oscillators and VCOs obtained with Agilent’s ADS software. Good agreements between the simulations of the circuits, the models and the theoretical results from our CAD tool were found.

The research conducted in this dissertation studies the issues regarding the improvement of phase noise performance in a BiCMOS Silicon Germanium (SiGe) cross-coupled differential-pair voltage controlled oscillator (VCO) in a narrowband application as a result of a tail-current shaping technique. With this technique, low-frequency noise components are reduced by increasing the signal amplitude without consuming additional power, and its effect on overall phase noise performance is evaluated. The research investigates effects of the tail-current as a main contributor to phase noise, and also other effects that may influence the phase noise performance like inductor geometry and placement, transistor sizing, and the gain of the oscillator. The hypothesis is verified through design in a standard 0.35 μm BiCMOS process supplied by Austriamicrosystems (AMS). Several VCOs are fabricated on-chip to serve for a comparison and verify that the employment of tail-current shaping does improve phase noise performance. The results are then compared with mathematical models and simulated results, to confirm the hypothesis. Simulation results provided a 3.3 dBc/Hz improvement from -105.3 dBc/Hz to -108.6 dBc/Hz at a 1 MHz offset frequency from the 5 GHz carrier when employing tail-current shaping. The relatively small increase in VCO phase noise performance translates in higher modulation accuracy when used in a transceiver, therefore this increase can be regarded as significant. Parametric analysis provided an additional 1.8 dBc/Hz performance enhancement in phase noise that can be investigated in future works. The power consumption of the simulated VCO is around 6 mW and 4.1 mW for the measured prototype. The circuitry occupies 2.1 mm2 of die area. Copyright / Dissertation (MEng)--University of Pretoria, 2010. / Electrical, Electronic and Computer Engineering / unrestricted

"2009" / Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010. / Bibliography: p. 163-166. / Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion. / Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices. / Mode of access: World Wide Web. / xxii, 166 p. : ill (some col.)